R2A20111SP Power Factor Correction Controller IC REJ03F0231-0200 Rev.2.00 Sep 29, 2009 Description The R2A20111 is a power-factor correction (PFC) controller IC. This IC adopts continuous conduction mode as PFC operation. Various functions such as constant power limit, overvoltage detection, overcurrent detection, soft start, feedback-loop disconnection detection, and holding function of PFC operation through momentary outage (PFC hold function) are incorporated in a single chip. These functions reduce external circuitry. The constant power limit function allows to eliminate a significant amount of coil noise which is generated due to overcurrent detection operation in case of conventional overload. The PFC hold function enables quick recovery by continuing PFC operation after momentary outage. The hold time can be adjusted by an external capacitance. Overcurrent detection pin is separately provided. Latch mode shutdown function is incorporated. A soft-start control pin provides for the easy adjustment of soft-start operation, and can be used to prevent overshooting of the output voltage. Features • Maximum ratings ⎯ Power-supply voltage Vcc: 24 V ⎯ Operating junction temperature Tjopr: – 40 to 125°C • Electrical characteristics ⎯ VREF output voltage VREF: 5.0 V ± 3% ⎯ UVLO operation start voltage VH: 10.5 ± 0.9 V ⎯ UVLO operation stop voltage VL: 9.0 ± 0.7 V ⎯ PFC output maximum ON duty Dmax-out: 95% (typ.) • Functions ⎯ Constant power limit function ⎯ Continuous conduction mode ⎯ Hold function of PFC operation on momentary outage (PFC hold function) ⎯ Overvoltage detection ⎯ Overcurrent detection ⎯ Soft start ⎯ Feedback loop disconnection detection ⎯ IC shutdown function ⎯ Package lineup: SOP-16 Applications • • • • Flat panel display Projector Desktop PC White goods Ordering Information Part No. R2A20111SPW0 Package Name FP-16DAV REJ03F0231-0200 Rev.2.00 Sep 29, 2009 Page 1 of 7 Package Code PRSP0016DH-B Taping Spec. 2000 pcs./one taping product R2A20111SP System Diagram 150 μH Rec+ B+ T1 680k To FB B+ OUT (385V dc) 680k Q1 Rec– From OUT 470μF ×2 (450V) from auxiliary 24V VRB1 GND 4.7μ VCC 16 VREF RT 62k 5V Internal Bias 3.6V 0.65V 9 27.5V H 10.5V 5V VREF Generator UVLO L 6 VREF 0.1μ 9.0V VREF In GOOD Out CT 10 390p UVL VREF CAO 6800p 2.2k To Q1 gate Gate Driver +/– 1.0A (PEAK) Logic 7 1 470p OUT VREF IAC 82k CAMP SS 12 1.28M Multiplier 1000p CAI 2.4k VREF 22k 5 100 CLIMIT 10k CLIMIT 8 0.0165 (5W) 1.3V 100p 2.4k CGND 820k 4 EO 14 VREF 2.5V 0.033μ VREF 2.688V 2.638V VAMP FB 15 13 B+OVP 0.47μ SS 25μA From VRB1(B+ monitor1) 720k 2 0.52V GND AC-Det PFC-ON 1μ 14k 11 Circuit Ground 0.1μ 0.82V 0.79V 3 DELAY 0.22μ REJ03F0231-0200 Rev.2.00 Sep 29, 2009 Page 2 of 7 R2A20111SP Pin Arrangement OUT 1 16 VCC GND 2 15 SS DELAY 3 14 EO CGND 4 13 FB CAI 5 12 IAC VREF 6 11 PFC-ON CAO 7 10 CT CLIMIT 8 9 RT (Top view) Pin Description Pin No. Pin Name I/O 1 2 3 4 5 6 7 8 9 OUT GND DELAY CGND CAI VREF CAO CLIMIT RT Output — Input/Output Input Input/Output Output Output Input Input/Output 10 11 12 13 14 15 16 CT PFC-ON IAC FB EO SS VCC Output Input Input Input Output Output Input Function Power MOS FET gate driver output Ground Hold time adjust and IC shutdown Non-inverting input of current amplifier Inverting input of current amplifier and Current output for PFC control Reference voltage output Current amplifier output Overcurrent detection Timing resistor for settings of operational frequency, and the maximum CAI pin and DELAY pin current Timing capacitor for operational frequency adjust Detection of input AC voltage level Detection of input AC waveform Voltage amplifier input Voltage amplifier output Timing capacitor for soft-start time adjust Power supply voltage input REJ03F0231-0200 Rev.2.00 Sep 29, 2009 Page 3 of 7 R2A20111SP Absolute Maximum Ratings (Ta = 25°C) Item Symbol Supply voltage OUT peak current OUT DC current Terminal voltage CAO voltage EO voltage DELAY voltage CAI voltage RT current IAC current VREF current Power dissipation Operating junction temperature Storage temperature VCC Ipk-out Idc-out Vi-group1 Vi-group2 Vcao Veo Vdelay Vi-cs Irt Iiac Io-ref Pt Tj-opr Tstg Ratings Unit 24 ±1.0 ±0.1 –0.3 to Vcc –0.3 to Vref –0.3 to Vcaoh –0.3 to Veoh –0.3 to +6.5 –1.5 to +0.3 –200 0.6 –5 1 –40 to +125 –55 to +150 V A A V V V V V V μA mA mA W °C °C Note 3 4 5 6 Notes: 1. 2. 3. 4. Rated voltages are with reference to the GND pin. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). The transient current when driving capacitive load. This is the rated voltage for the following pin: OUT. 5. This is the rated voltage for the following pins: CGND, VREF, CLIMIT, RT, CT, PFC-ON, IAC, FB, SS 6. Thermal resistance of packages Package θja θjc Note SOP16 120°C/W — — 35°C/W REJ03F0231-0200 Rev.2.00 Sep 29, 2009 Page 4 of 7 40 × 40 × 1.6 [mm], Mounted on a glass epoxy printed board with 10% wiring density Infinite heat sink R2A20111SP Electrical Characteristics (Ta = 25°C, VCC = 12 V, RT = 27 kΩ, CT = 1000 pF) Supply VREF Oscillator Soft start Current limit VAMP CAMP Note: Item Start threshold Shutdown threshold UVLO hysteresis Startup current Symbol VH VL dVUVL Is Is temperature stability Operating current dIs/dTa Icc Output voltage Line regulation Vref Vref-line Load regulation Vref-load Temperature stability Initial accuracy dVref fout dfout/dTa Min 9.6 8.3 1.0 140 Typ 10.5 9.0 1.5 200 Max 11.4 9.7 2.0 260 Unit V V V μA Test Conditions VCC = 9.5 V — –0.3 — %/°C * 3.45 4.5 6.45 mA 4.85 — 5.00 5 5.15 20 V mV — 5 20 mV — ±80 — ppm/°C 58.5 65 71.5 kHz Measured pin: OUT — ±0.1 — %/°C Ta = –40 to 125°C * 1 IAC = 0 A, CL = 0 F Isource = 1 mA Isource = 1 mA, VCC = 12 V to 23 V Isource = 1 mA to 5 mA 1 Ta = –40 to 125°C * 1 fout temperature stability fout voltage stability fout-line –1.5 0.5 1.5 % VCC = 12 V to 18 V CT peak voltage Ramp valley voltage RT voltage Vct-H Vct-L Vrt — — 1.17 3.6 0.65 1.25 4.0 — 1.33 V V V *1 *1 Sink current Threshold voltage Iss VCL 15.0 1.222 25.0 1.3 35.0 1.378 μA V SS = 2 V Delay to output Feedback voltage Input bias current Open loop gain High voltage Low voltage Source current Sink current Transconductance Input offset voltage Open loop gain High voltage Low voltage Source current Sink current Transconductance td-CL Vfb Ifb Av-v Veoh Veol Isrc-eo Isnk-eo Gm-v Vio-ca Av-ca Vcaoh Vcaol Isrc-ca Isnk-ca Gm-c — 2.40 –0.3 — 5.2 — –180 90 150 — — 5.2 — –135 67 530 100 2.50 0 53 5.7 0.1 –120 120 200 (–10) 68 5.7 0.1 –90 90 700 200 2.60 0.3 — 6.2 0.3 –90 180 290 0 — 6.2 0.3 –67 135 1000 ns V μA dB V V μA μA μA/V mV dB V V μA μA μA/V 1. Design spec. REJ03F0231-0200 Rev.2.00 Sep 29, 2009 Page 5 of 7 CLIMIT = 2 to 0 V FB-EO Short Measured pin: FB *1 FB = 2.3 V, EO: Open FB = 2.7 V, EO: Open FB = 1.0 V, EO = 2.5 V FB = 4.0 V, EO = 2.5 V FB = 2.5 V, EO = 2.5 V *1 *1 CAO = 2.5 V CAO = 2.5 V *1 R2A20111SP Electrical Characteristics (cont.) (Ta = 25°C, VCC = 12 V, RT = 27 kΩ, CT = 1000 pF) IAC/ Multiplier OUT Item IAC pin voltage Imo current 1 Symbol Viac Imo1 Min 1.6 –61.3 Typ 2.3 –51.5 Max 3.0 –41 Unit V μA Imo current 2 Imo2 –197.9 –165 –131.5 μA EO = Vcaoh, IAC = 150 μA PFC-ON = 1.2 V Imo current 3 Imo3 –32.8 –27 –21.2 μA EO = 2.5 V, IAC = 375 μA PFC-ON = 2.5 V Imo current 4 Imo4 –110.4 –92 –73.6 μA Minimum duty cycle Maximum duty cycle Rise time Fall time Low voltage Dmin-out Dmax-out tr-out tf-out Vol1-out Vol2-out Vol3-out Voh1-out Voh2-out — 90 — — — — — 11.5 10.0 — 95 30 30 0.05 0.5 0.03 11.9 11.0 0 98 100 100 0.2 2.0 0.7 — — % % ns ns V V V V V EO = Vcaoh, IAC = 375 μA PFC-ON = 2.5 V CAO = 4.0 V CAO = 0 V CL = 1000 pF CL = 1000 pF Iout = 20 mA Iout = 200 mA (Pulse test) Iout = 10 mA, VCC = 5 V Iout = –20 mA Iout = –200 mA (Pulse test) Shut down voltage Reset voltage Shut down current PFC enable voltage PFC disable voltage Vshut Vres Ishut Von-pfc Voff-pfc 3.30 — 120 0.74 0.71 4.00 — 190 0.82 0.79 4.70 4.0 260 0.9 0.86 V V μA V V Input: DELAY Input: Vcc VCC = 9 V Input pin: PFC-ON Input pin: PFC-ON PFC disable delay threshold voltage Input current B+ OVP set voltage Vd-pfc 1.05 1.20 1.30 V Input pin: DELAY Ipfc-on dVovps –1.0 0.125 –0.2 0.188 1 0.250 μA V PFC-ON = 2 V Input pin: FB *2 B+ OVP reset voltage FB low set voltage dVovpr 0.075 0.138 0.200 V Input pin: FB * Vfbls 0.425 0.52 0.615 V Input pin: FB DELAY source current DELAY sink current Isrc-delay –47.5 –42.5 –38 μA DELAY = 1 V RT = 27 kΩ Isnk-delay — 770 — μA DELAY = 1 V 1 RT = 27 kΩ * High voltage Shut down Supervisor Notes: 1. Design spec. 2. dVovps = Vovps – Vref × 0.5 dVovpr = Vovpr – Vref × 0.5 FB Vovps Vovpr Vfbls OUT REJ03F0231-0200 Rev.2.00 Sep 29, 2009 Page 6 of 7 Vref × 0.5 Test Conditions IAC = 100 μA EO = 2.5 V, IAC = 150 μA PFC-ON = 1.2 V 2 R2A20111SP Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 8 e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F REJ03F0231-0200 Rev.2.00 Sep 29, 2009 Page 7 of 7 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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