SX1231J WIRELESS & SENSING DATASHEET SX1231J Transceiver Low Power Integrated UHF Transceiver VR_DIG RC Oscillator Mixers RFIO RSSI AFC GND Division by 2, 4 or 6 PA_BOOST PA1&2 Tank Inductor Loop Filter Frac-N PLL Synthesizer GENERAL DESCRIPTION Smart metering and IEEE15.4d/g Wireless sensor networks Home and building automation Wireless alarm and security systems Industrial monitoring and control DIO0 DIO1 DIO2 DIO3 DIO4 GND High Sensitivity: down to -120 dBm at 1.2 kbps Low current receive mode = 16 mA Robust Selectivity: 42dB at 25kHz offset Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, 80 dB Blocking Immunity, no Image Frequency response Low current sleep mode with register retention =100nA Programmable TX Power: -18 to +17 dBm in 1dB steps Constant RF performance over VDD voltage range FSK bit rates up to 300 kb/s Fully integrated synthesizer with a resolution of 61 Hz FSK, GFSK, MSK, GMSK and OOK modulations Built-in bit synchronizer for clock recovery Incoming sync word recognition 115 dB+ dynamic range RSSI Automatic RF sense with ultra-fast AFC Packet engine with CRC, AES-128, and 66-byte FIFO Built-in temperature sensor and low battery indicator ORDERING INFORMATION Active RFID tags Remote keyless entry (RKE) and automotive MARKETS RXTX KEY PRODUCT FEATURES The SX1231J is an ARIB compliant highly integrated RF transceiver which operates over all Japanese sub-GHz frequency bands. Its highly integrated digital architecture minimizes external components and provides flexibility for optimizing the system parameters and performance. The high sensitivity and exceptional blocking performance combined with optimized IIP3 maximizes the range in harshest environments. The industries lowest sleep current, fastest wake times, and low receive current extend the battery life for any application. The transmit output power is programmable up to +17dBm and delivers constant performance over the battery voltage lifetime. TrueRF™ technology enables a low-cost external component count (eliminating SAW filter) while still satisfying ARIB, FCC, and ETSI regulations. The device supports IEEE 15.4d/g mandatory modes. RESET SPI DIO5 XO 32 MHz XTAL APPLICATIONS Modulator VR_PA Ramp & Control Interpolation & Filtering PA0 Packet Engine & 66 Bytes FIFO Single to Differential Σ/Δ Modulators Control Registers - Shift Registers - SPI Interface LNA Demodulator & Bit Synchronizer VR_ANA Power Distribution System Decimation and & Filtering VBAT1&2 Japan: ARIB STD-T67 from 426 to 470 MHz Japan: ARIB STD-T108 from 915 to 930 MHz Rev 2 - April 2012 Page 1 Part Number Package Delivery MOQ / Multiple SX1231JIMLTRT QFN24 Tape & Reel 3000 pieces Pb-free, Halogen free, RoHS/WEEE compliant product www.semtech.com SX1231J WIRELESS & SENSING DATASHEET Table of Contents 1. 2. Page General Description ................................................................................................................................................ 5 1.1. Simplified Block Diagram ................................................................................................................................ 5 1.2. Pin and Marking Diagram ................................................................................................................................ 6 1.3. Pin Description ................................................................................................................................................ 7 Electrical Characteristics......................................................................................................................................... 8 2.1. ESD Notice...................................................................................................................................................... 8 2.2. Absolute Maximum Ratings ............................................................................................................................ 8 2.3. Operating Range............................................................................................................................................. 8 2.4. Chip Specification ........................................................................................................................................... 9 2.4.1. Power Consumption ................................................................................................................................... 9 2.4.2. Frequency Synthesis .................................................................................................................................. 9 2.4.3. Receiver ................................................................................................................................................... 10 2.4.4. Transmitter ............................................................................................................................................... 11 2.4.5. Digital Specification ...................................................................................................................................12 3. Chip Description.................................................................................................................................................... 13 4. Configuration and Status Registers ...................................................................................................................... 13 5. 4.1. General Description ...................................................................................................................................... 13 4.2. Common Configuration Registers ................................................................................................................. 16 4.3. Transmitter Registers .................................................................................................................................... 19 4.4. Receiver Registers ........................................................................................................................................ 20 4.5. IRQ and Pin Mapping Registers.................................................................................................................... 22 4.6. Packet Engine Registers............................................................................................................................... 24 4.7. Temperature Sensor Registers ..................................................................................................................... 27 4.8. Test Registers ............................................................................................................................................... 27 Application Information ......................................................................................................................................... 28 5.1. Reference Design ......................................................................................................................................... 28 5.2. Regulatory Compliance................................................................................................................................. 30 5.2.1. ARIB STD-T67 ......................................................................................................................................... 30 5.2.2. ARIB STD-T108 ....................................................................................................................................... 30 6. Packaging Information .......................................................................................................................................... 31 6.1. QFN 24 Encapsulation .................................................................................................................................. 31 6.2. Thermal Impedance ...................................................................................................................................... 31 6.3. Tape & Reel Specification............................................................................................................................. 32 7. References............................................................................................................................................................ 33 8. Revision History .................................................................................................................................................... 33 Rev 2 - April 2012 Page 2 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET Index of Figures Page Figure 1. Block Diagram ................................................................................................................................................ 5 Figure 2. Pin Diagram (not to scale) .............................................................................................................................. 6 Figure 3. Marking Diagram ............................................................................................................................................ 6 Figure 4. SX1231J Evaluation Module Schematics ..................................................................................................... 28 Figure 5. QFN 24 Package Outline Drawing and Land Pattern ................................................................................... 31 Figure 6. Tape & Reel Specification, QFN Package .................................................................................................... 32 Index of Tables Page Table 1. SX1231J Pinouts .............................................................................................................................................. 7 Table 2. Absolute Maximum Ratings .............................................................................................................................. 8 Table 3. Operating Range .............................................................................................................................................. 8 Table 4. Power Consumption Specification .................................................................................................................... 9 Table 5. Frequency Synthesizer Specification ................................................................................................................ 9 Table 6. Receiver Specification .................................................................................................................................... 10 Table 7. Transmitter Specification ................................................................................................................................ 11 Table 8. Digital Specification ........................................................................................................................................ 12 Table 9. Registers Summary ........................................................................................................................................ 13 Table 10. Common Configuration Registers ................................................................................................................. 16 Table 11. Transmitter Registers ................................................................................................................................... 19 Table 12. Receiver Registers ....................................................................................................................................... 20 Table 13. IRQ and Pin Mapping Registers ................................................................................................................... 22 Table 14. Packet Engine Registers .............................................................................................................................. 24 Table 15. Temperature Sensor Registers ..................................................................................................................... 27 Table 16. Test Registers .............................................................................................................................................. 27 Table 17. SX1231J Evaluation Module BOM ............................................................................................................... 29 Table 18. Revision History ............................................................................................................................................ 33 Rev 2 - April 2012 Page 3 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET Acronyms BOM BR BW CCITT CRC DAC ETSI FCC Fdev FIFO FIR FS FSK GUI IC ID IF IRQ ITU LFSR LNA LO Rev 2 - April 2012 Bill Of Materials Bit Rate Bandwidth Comité Consultatif International Téléphonique et Télégraphique - ITU Cyclic Redundancy Check Digital to Analog Converter European Telecommunications Standards Institute Federal Communications Commission Frequency Deviation First In First Out Finite Impulse Response Frequency Synthesizer Frequency Shift Keying Graphical User Interface Integrated Circuit IDentificator Intermediate Frequency Interrupt ReQuest International Telecommunication Union Linear Feedback Shift Register Low Noise Amplifier Local Oscillator Page 4 LSB MSB NRZ OOK Least Significant Bit Most Significant Bit Non Return to Zero On Off Keying PA PCB PLL Power Amplifier Printed Circuit Board Phase-Locked Loop POR RBW RF RSSI Rx SAW SPI SR Stby Tx uC VCO XO XOR Power On Reset Resolution BandWidth Radio Frequency Received Signal Strength Indicator Receiver Surface Acoustic Wave Serial Peripheral Interface Shift Register Standby Transmitter Microcontroller Voltage Controlled Oscillator Crystal Oscillator eXclusive OR www.semtech.com SX1231J WIRELESS & SENSING DATASHEET This product datasheet contains a detailed description of the SX1231J performance and functionality. Please consult the Semtech website www.semtech.com for the latest updates or errata. 1. General Description The SX1231J is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The SX1231J's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bi-directional RF links, and where stable and constant RF performance is required over the full operating range of the device down to 1.8V. Coupled with a link budget in excess of 135 dB, the advanced system features of the SX1231J include a 66 byte TX/RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU requirements. The SX1231J complies with Japanese ARIB regulatory requirements and is available in a 5x 5 mm QFN 24 lead package. 1.1. Simplified Block Diagram VR_DIG RC Oscillator Power Distribution System RFIO Demodulator & Bit Synchronizer Σ/Δ Modulators Mixers Single to Differential Decimation and & Filtering LNA RSSI AFC GND Division by 2, 4 or 6 Ramp & Control Loop Filter Frac-N PLL Synthesizer Modulator VR_PA Tank Inductor Interpolation & Filtering PA0 PA1&2 RESET SPI RXTX DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 XO 32 MHz PA_BOOST Control Registers - Shift Registers - SPI Interface VR_ANA Packet Engine & 66 Bytes FIFO VBAT1&2 XTAL GND Frequency Synthesis Transmitter Blocks Primarily Analog Receiver Blocks Control Blocks Primarily Digital Figure 1. Block Diagram Rev 2 - April 2012 Page 5 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 1.2. Pin and Marking Diagram The following diagram shows the pin arrangement of the SX1231J, top view. Figure 2. Pin Diagram (not to scale) Figure 3. Marking Diagram Notes yyww refers to the date code xxxxxx refers to the lot number Rev 2 - April 2012 Page 6 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 1.3. Pin Description Table 1 SX1231J Pinouts Pin Number Note Name Type - GROUND - Exposed ground pad 1 12 VBAT1 - Supply voltage 2 13 VR_ANA - Regulated supply voltage for analogue circuitry 3 14 VR_DIG - Regulated supply voltage for digital blocks 4 15 XTA I/O XTAL connection 5 16 XTB I/O XTAL connection 6 17 RESET I/O Reset trigger input - 18 GND - 7 19 DIO0 I/O Digital I/O, software configured 8 20 DIO1/DCLK I/O Digital I/O, software configured 9 21 DIO2/DATA I/O Digital I/O, software configured 10 22 DIO3 I/O Digital I/O, software configured 11 23 DIO4 I/O Digital I/O, software configured 12 24 DIO5 I/O Digital I/O, software configured - 25 GND - Ground 13 26 VBAT2 - Supply voltage 14 27 GND - Ground 15 28 SCK I SPI Clock input 16 1 MISO O SPI Data output 17 2 MOSI I SPI Data input 18 3 NSS I SPI Chip select input 19 4 RXTX O Rx/Tx switch control: high in Tx 20 5 GND - Ground 21 6 RFIO I/O 22 7 GND - Ground 23 8 PA_BOOST O Optional high-power PA output - 9 GND - Ground 24 10 VR_PA - Regulated supply for the PA - 11 GND - Ground QFN TSSOP 0 Description Ground RF input / output PA_BOOST can be left floating if unused Rev 2 - April 2012 Page 7 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 2. Electrical Characteristics 2.1. ESD Notice The SX1231J is a high performance radio frequency device. It satisfies: Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins. Class B of the JEDEC standard JESD22-A115-A (Machine Model) on all pins. Class IV of the JEDEC standard JESD22-C101C (Charged Device Model) on pins VR_ANA, VR_DIG, RFIO, PA_BOOST, VR_PA, Class III on all other pins. It should thus be handled with all the necessary ESD precautions to avoid any permanent damage. 2.2. Absolute Maximum Ratings Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 2 Absolute Maximum Ratings Symbol Description Min Max Unit VDDmr Supply Voltage -0.5 3.9 V Tmr Temperature -55 +115 °C Tj Junction temperature - +125 °C Pmr RF Input Level - +6 Min Max dBm 2.3. Operating Range Table 3 Operating Range Symbol Description Unit VDDop Supply voltage 1.8 3.6 V Top Operational temperature range -40 +85 °C Clop Load capacitance on digital ports - 25 pF ML RF Input Level - 0 dBm Rev 2 - April 2012 Page 8 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 2.4. Chip Specification The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VBAT1= VBAT2=VDD=3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 915 MHz, Pout = +13dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise specified. Note Unless otherwise specified, the performances in the other frequency bands are similar or better. 2.4.1. Power Consumption Table 4 Power Consumption Specification Symbol Description IDDSL Supply current in Sleep mode IDDIDLE Supply current in Idle mode IDDST Supply current in Standby mode IDDFS Conditions Min Typ Max - 0.1 1 uA RC oscillator enabled - 1.2 - uA Crystal oscillator enabled - 1.25 1.5 mA Supply current in Synthesizer mode - 9 - mA IDDR Supply current in Receive mode - 16 - mA IDDT Supply current in Transmit mode with appropriate matching, stable across VDD range - 95 45 33 20 16 - mA mA mA mA mA RFOP = +17 dBm, on PA_BOOST RFOP = +13 dBm, on RFIO pin RFOP = +10 dBm, on RFIO pin RFOP = 0 dBm, on RFIO pin RFOP = -1 dBm, on RFIO pin Unit 2.4.2. Frequency Synthesis Table 5 Frequency Synthesizer Specification Symbol Description Conditions Min Typ Max FR Synthesizer Frequency Range Programmable 424 862 - 510 1020 MHz MHz FXOSC Crystal oscillator frequency See section 5.1 - 32 - MHz TS_OSC Crystal oscillator wake-up time - 250 500 us TS_FS Frequency synthesizer wake-up time to PllLock signal - 80 150 us TS_HOP Frequency synthesizer hop time at most 10 kHz away from the target - 20 20 50 50 80 80 80 - us us us us us us us FSTEP Frequency synthesizer step - 61.0 - Hz Rev 2 - April 2012 From Standby mode 200 kHz step 1 MHz step 5 MHz step 7 MHz step 12 MHz step 20 MHz step 25 MHz step FSTEP = FXOSC/219 Page 9 Unit www.semtech.com SX1231J WIRELESS & SENSING DATASHEET FRC RC Oscillator frequency After calibration - 62.5 - kHz BRF Bit rate, FSK Programmable 1.2 - 300 kbps BRO Bit rate, OOK Programmable 1.2 - 32.768 kbps FDA Frequency deviation, FSK Programmable FDA + BRF/2 =< 500 kHz 0.6 - 300 kHz 2.4.3. Receiver All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a PN15 sequence with a BER of 0.1% (Bit Synchronizer is enabled), unless otherwise specified. The LNA impedance is set to 200 Ohms, by setting bit LnaZin in RegLna to 1. Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 dB above the nominal sensitivity level. Table 6 Receiver Specification Symbol Description Conditions Min Typ Max RFS_F FSK sensitivity, highest LNA gain Unit FDA = 5 kHz, BR = 1.2 kb/s FDA = 5 kHz, BR = 4.8 kb/s FDA = 40 kHz, BR = 38.4 kb/s - -118 -114 -105 - dBm dBm dBm FDA = 5 kHz, BR = 1.2 kb/s * - -120 - dBm BR = 4.8 kb/s - -112 -109 dBm -13 -10 - dB RFS_O OOK sensitivity, highest LNA gain CCR Co-Channel Rejection ACR Adjacent Channel Rejection Offset = +/- 25 kHz Offset = +/- 50 kHz 37 42 42 - dB dB BI Blocking Immunity Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz - 66 71 79 - dB dB dB Blocking Immunity Wanted signal at sensitivity +16dB Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz - 62 65 73 - dB dB dB AMR AM Rejection, AM modulated interferer with 100% modulation depth, fm = 1 kHz, square Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz - 66 71 79 - dB dB dB IIP2 2nd order Input Intercept Point Unwanted tones are 20 MHz above the LO Lowest LNA gain Highest LNA gain - +75 +35 - dBm dBm IIP3 3rd order Input Intercept point Unwanted tones are 1MHz and 1.995 MHz above the LO Lowest LNA gain Highest LNA gain -23 +20 -18 - dBm dBm BW_SSB Single Side channel filter BW 2.6 - 500 kHz Rev 2 - April 2012 Programmable Page 10 www.semtech.com SX1231J WIRELESS & SENSING * DATASHEET IMR_OOK Image rejection in OOK mode Wanted signal level = -106 dBm 27 30 - dB TS_RE Receiver wake-up time, from PLL locked state to RxReady RxBw = 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s - 1.7 96 - ms us TS_RE_AGC Receiver wake-up time, from PLL locked state, AGC enabled RxBw= 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s - 3.0 163 ms us TS_RE_AGC &AFC Receiver wake-up time, from PLL lock state, AGC and AFC enabled RxBw= 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s 4.8 265 ms us TS_FEI FEI sampling time Receiver is ready - 4.Tbit - - TS_AFC AFC Response Time Receiver is ready - 4.Tbit - - TS_RSSI RSSI Response Time Receiver is ready - 2.Tbit - - DR_RSSI RSSI Dynamic Range AGC enabled - -115 0 - dBm dBm Min Max Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver 2.4.4. Transmitter Table 7 Transmitter Specification Symbol Description Conditions Min Typ Max RF_OP RF output power in 50 ohms On RFIO pin Programmable with 1dB steps - +13 -18 - dBm dBm RF_OPH Max RF output power, on PA_BOOST pin With external match to 50 ohms - +17 - dBm ΔRF_OP RF output power stability From VDD=1.8V to 3.6V - +/-0.3 - dB PHN Transmitter Phase Noise 50 kHz Offset from carrier 868 / 915 MHz bands 434 / 315 MHz bands - -95 -99 - dBc/ Hz dBm Max Min ACP Transmitter adjacent channel power (measured at 25 kHz offset) BT=0.5 . Measurement conditions as defined by EN 300 220-1 V2.1.1 - - -37 TS_TR Transmitter wake up time, to the first rising edge of DCLK Frequency Synthesizer enabled, PaRamp = 10 us, BR = 4.8 kb/s. - 120 - Rev 2 - April 2012 Page 11 Unit us www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 2.4.5. Digital Specification Conditions: Temp = 25°C, VDD = 3.3V, FXOSC = 32 MHz, unless otherwise specified. Table 8 Digital Specification Symbol Description VIH Min Typ Max Digital input level high 0.8 - - VDD VIL Digital input level low - - 0.2 VDD VOH Digital output level high Imax = 1 mA 0.9 - - VDD VOL Digital output level low Imax = -1 mA - - 0.1 VDD FSCK SCK frequency - - 10 MHz tch SCK high time 50 - - ns tcl SCK low time 50 - - ns trise SCK rise time - 5 - ns tfall SCK fall time - 5 - ns tsetup MOSI setup time from MOSI change to SCK rising edge 30 - - ns thold MOSI hold time from SCK rising edge to MOSI change 60 - - ns tnsetup NSS setup time from NSS falling edge to SCK rising edge 30 - - ns tnhold NSS hold time from SCK falling edge to NSS rising edge, normal mode 30 - - ns tnhigh NSS high time between SPI accesses 20 - - ns T_DATA DATA hold and setup time 250 - - ns Rev 2 - April 2012 Conditions Page 12 Unit www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 3. Chip Description Semtech’s transceivers SX1231 and SX1231J share the architecture and functionnalities. For a complete description of the feature set, please refer to [1] 4. Configuration and Status Registers 4.1. General Description Table 9 Registers Summary Reset (built-in) Default (recom mended) Address Register Name 0x00 RegFifo 0x00 FIFO read/write access 0x01 RegOpMode 0x04 Operating modes of the transceiver 0x02 RegDataModul 0x00 Data operation mode and Modulation settings 0x03 RegBitrateMsb 0x1A Bit Rate setting, Most Significant Bits 0x04 RegBitrateLsb 0x0B Bit Rate setting, Least Significant Bits 0x05 RegFdevMsb 0x00 Frequency Deviation setting, Most Significant Bits 0x06 RegFdevLsb 0x52 Frequency Deviation setting, Least Significant Bits 0x07 RegFrfMsb 0xE4 RF Carrier Frequency, Most Significant Bits 0x08 RegFrfMid 0xC0 RF Carrier Frequency, Intermediate Bits 0x09 RegFrfLsb 0x00 RF Carrier Frequency, Least Significant Bits 0x0A RegOsc1 0x41 RC Oscillators Settings 0x0B RegAfcCtrl 0x00 AFC control in low modulation index situations 0x0C RegLowBat 0x02 Low Battery Indicator Settings 0x0D RegListen1 0x92 Listen Mode settings 0x0E RegListen2 0xF5 Listen Mode Idle duration 0x0F RegListen3 0x20 Listen Mode Rx duration 0x10 RegVersion 0x23 Semtech ID relating the silicon revision 0x11 RegPaLevel 0x9F PA selection and Output Power control 0x12 RegPaRamp 0x09 Control of the PA ramp time in FSK mode 0x13 RegOcp 0x1A Over Current Protection control 0x14 Reserved14 0x40 - 0x15 Reserved15 0xB0 - Rev 2 - April 2012 Description Page 13 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET Reset (built-in) Default (recom mended) Address Register Name 0x16 Reserved16 0x7B - 0x17 Reserved17 0x9B - 0x18 RegLna 0x08 0x88 LNA settings 0x19 RegRxBw 0x86 0x55 Channel Filter BW Control 0x1A RegAfcBw 0x8A 0x8B Channel Filter BW control during the AFC routine 0x1B RegOokPeak 0x40 OOK demodulator selection and control in peak mode 0x1C RegOokAvg 0x80 Average threshold control of the OOK demodulator 0x1D RegOokFix 0x06 Fixed threshold control of the OOK demodulator 0x1E RegAfcFei 0x10 AFC and FEI control and status 0x1F RegAfcMsb 0x00 MSB of the frequency correction of the AFC 0x20 RegAfcLsb 0x00 LSB of the frequency correction of the AFC 0x21 RegFeiMsb 0x00 MSB of the calculated frequency error 0x22 RegFeiLsb 0x00 LSB of the calculated frequency error 0x23 RegRssiConfig 0x02 RSSI-related settings 0x24 RegRssiValue 0xFF RSSI value in dBm 0x25 RegDioMapping1 0x00 Mapping of pins DIO0 to DIO3 0x26 RegDioMapping2 0x27 RegIrqFlags1 0x80 Status register: PLL Lock state, Timeout, RSSI > Threshold... 0x28 RegIrqFlags2 0x00 Status register: FIFO handling flags, Low Battery detection... 0x29 RegRssiThresh 0x2A RegRxTimeout1 0x00 Timeout duration between Rx request and RSSI detection 0x2B RegRxTimeout2 0x00 Timeout duration between RSSI detection and PayloadReady 0x2C RegPreambleMsb 0x00 Preamble length, MSB 0x2D RegPreambleLsb 0x03 Preamble length, LSB 0x2E RegSyncConfig 0x98 Sync Word Recognition control 0x2F-0x36 RegSyncValue1-8 0x37 RegPacketConfig1 0x10 Packet mode settings 0x38 RegPayloadLength 0x40 Payload length setting 0x39 RegNodeAdrs 0x00 Node address Rev 2 - April 2012 0x05 0x07 0xFF 0xE4 0x00 0x01 Description Mapping of pins DIO4 and DIO5, ClkOut frequency RSSI Threshold control Sync Word bytes, 1 through 8 Page 14 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET Default (recom mended) Reset (built-in) Address Register Name 0x3A RegBroadcastAdrs 0x00 Broadcast address 0x3B RegAutoModes 0x00 Auto modes settings 0x3C RegFifoThresh 0x3D RegPacketConfig2 0x02 Packet mode settings 0x3E-0x4D RegAesKey1-16 0x00 16 bytes of the cypher key 0x4E RegTemp1 0x01 Temperature Sensor control 0x4F RegTemp2 0x00 Temperature readout 0x58 RegTestLna 0x1B Sensitivity boost 0x59 RegTestTcxo 0x09 TCXO or XTAL input setting 0x6F RegTestDagc 0x71 RegTestAfc 0x00 0x50 + RegTest - Note 0x0F 0x8F 0x00 0x30 Description Fifo threshold, Tx start condition Fading Margin Improvement AFC offset for low modulation index AFC Internal test registers - Reset values are automatically refreshed in the chip at Power On Reset - Default values are the Semtech recommended register values, optimizing the device operation - Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 4 Rev 2 - April 2012 Page 15 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 4.2. Common Configuration Registers Table 10 Common Configuration Registers Name (Address) RegFifo (0x00) RegOpMode (0x01) RegDataModul (0x02) RegBitrateMsb (0x03) Rev 2 - April 2012 Bits Variable Name 7-0 Mode Default Description Value 0x00 FIFO data input/output Fifo rw 7 SequencerOff rw 0 6 ListenOn rw 0 5 ListenAbort w 0 4-2 Mode rw 001 1-0 7 6-5 DataMode r r rw 00 0 00 4-3 ModulationType rw 00 2 1-0 ModulationShaping r rw 0 00 7-0 BitRate(15:8) rw 0x1a Page 16 Controls the automatic Sequencer (see section 4.2 ): 0 Æ Operating mode as selected with Mode bits in RegOpMode is automatically reached with the Sequencer 1 Æ Mode is forced by the user Enables Listen mode, should be enabled whilst in Standby mode: 0 Æ Off (see section 4.3) 1 Æ On Aborts Listen mode when set together with ListenOn=0 See section 4.3.4 for details Always reads 0. Transceiver’s operating modes: 000 Æ Sleep mode (SLEEP) 001 Æ Standby mode (STDBY) 010 Æ Frequency Synthesizer mode (FS) 011 Æ Transmitter mode (TX) 100 Æ Receiver mode (RX) others Æ reserved Reads the value corresponding to the current chip mode unused unused Data processing mode: 00 Æ Packet mode 01 Æ reserved 10 Æ Continuous mode with bit synchronizer 11 Æ Continuous mode without bit synchronizer Modulation scheme: 00 Æ FSK 01 Æ OOK 10 - 11 Æ reserved unused Data shaping: in FSK: 00 Æ no shaping 01 Æ Gaussian filter, BT = 1.0 10 Æ Gaussian filter, BT = 0.5 11 Æ Gaussian filter, BT = 0.3 in OOK: 00 Æ no shaping 01 Æ filtering with fcutoff = BR 10 Æ filtering with fcutoff = 2*BR 11 Æ reserved MSB of Bit Rate (Chip Rate when Manchester encoding is enabled) www.semtech.com SX1231J WIRELESS & SENSING DATASHEET RegBitrateLsb (0x04) 7-0 BitRate(7:0) rw RegFdevMsb (0x05) 7-6 5-0 7-0 Fdev(13:8) Fdev(7:0) r rw rw RegFdevLsb (0x06) 0x0b LSB of Bit Rate (Chip Rate if Manchester encoding is enabled) FXOSC BitRate = ----------------------------------BitRate (15,0) Default value: 4.8 kb/s 00 unused 000000 MSB of the frequency deviation 0x52 LSB of the frequency deviation Fdev = Fstep × Fdev (15,0) RegFrfMsb (0x07) 7-0 Frf(23:16) rw 0xe4 Default value: 5 kHz MSB of the RF carrier frequency RegFrfMid (0x08) 7-0 Frf(15:8) rw 0xc0 Middle byte of the RF carrier frequency RegFrfLsb (0x09) 7-0 Frf(7:0) rw 0x00 LSB of the RF carrier frequency RegOsc1 (0x0A) 7 RcCalStart w 6 RcCalDone r Frf = Fstep × Frf ( 23 ;0 ) RegAfcCtrl (0x0B) 5-0 7-6 5 AfcLowBetaOn r r rw RegLowBat (0x0C) 4-0 7-5 4 LowBatMonitor r r rw LowBatOn rw LowBatTrim rw 3 2-0 Rev 2 - April 2012 Default value: Frf = 915 MHz (32 MHz XO) Triggers the calibration of the RC oscillator when set. Always reads 0. RC calibration must be triggered in Standby mode. 1 0 Æ RC calibration in progress 1 Æ RC calibration is over 000001 unused 00 unused 0 Improved AFC routine for signals with modulation index lower than 2. Refer to section 3.5.16 for details 0 Æ Standard AFC routine 1 Æ Improved AFC routine 00000 unused 000 unused Real-time (not latched) output of the Low Battery detector, when enabled. 0 Low Battery detector enable signal 0 Æ LowBat off 1 Æ LowBat on 010 Trimming of the LowBat threshold: 000 Æ 1.695 V 001 Æ 1.764 V 010 Æ 1.835 V 011 Æ 1.905 V 100 Æ 1.976 V 101 Æ 2.045 V 110 Æ 2.116 V 111 Æ 2.185 V 0 Page 17 www.semtech.com SX1231J WIRELESS & SENSING RegListen1 (0x0D) RegListen2 (0x0E) RegListen3 (0x0F) DATASHEET 7-6 ListenResolIdle rw 10 5-4 ListenResolRx rw 01 3 ListenCriteria rw 0 2-1 ListenEnd rw 01 0 7-0 ListenCoefIdle r rw 0 0xf5 Resolution of Listen mode Idle time (calibrated RC osc): 00 Æ reserved 01 Æ 64 us 10 Æ 4.1 ms 11 Æ 262 ms Resolution of Listen mode Rx time (calibrated RC osc): 00 Æ reserved 01 Æ 64 us 10 Æ 4.1 ms 11 Æ 262 ms Criteria for packet acceptance in Listen mode: 0 Æ signal strength is above RssiThreshold 1 Æ signal strength is above RssiThreshold and SyncAddress matched Action taken after acceptance of a packet in Listen mode: 00 Æ chip stays in Rx mode. Listen mode stops and must be disabled (see section 4.3). 01 Æ chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. It then goes to the mode defined by Mode. Listen mode stops and must be disabled (see section 4.3). 10 Æ chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then resumes in Idle state. FIFO content is lost at next Rx wakeup. 11 Æ Reserved unused Duration of the Idle phase in Listen mode. t ListenIdle = ListenCoefIdle ⋅ ListenResolIdle 7-0 ListenCoefRx rw 0x20 Duration of the Rx phase in Listen mode (startup time included, see section 4.2.3) t ListenRx = ListenCoefRx ⋅ ListenResolRx RegVersion (0x10) Rev 2 - April 2012 7-0 Version r 0x23 Page 18 Version code of the chip. Bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 4.3. Transmitter Registers Table 11 Transmitter Registers Name (Address) RegPaLevel (0x11) 7 6 5 4-0 Pa0On * Pa1On * Pa2On * OutputPower rw rw rw rw Default Value 1 0 0 11111 RegPaRamp (0x12) 7-4 3-0 PaRamp r rw 0000 1001 RegOcp (0x13) 7-5 4 OcpOn r rw 000 1 3-0 OcpTrim rw 1010 Bits Variable Name Mode Description Enables PA0, connected to RFIO and LNA Enables PA1, on PA_BOOST pin Enables PA2, on PA_BOOST pin Output power setting, with 1 dB steps Pout = -18 + OutputPower [dBm] , with PA0 or PA1 Pout = -14 + OutputPower [dBm] , with PA1 and PA2 (limited to the 16 upper values of OutputPower) unused Rise/Fall time of ramp up/down in FSK 0000 Æ 3.4 ms 0001 Æ 2 ms 0010 Æ 1 ms 0011 Æ 500 us 0100 Æ 250 us 0101 Æ 125 us 0110 Æ 100 us 0111 Æ 62 us 1000 Æ 50 us 1001 Æ 40 us 1010 Æ 31 us 1011 Æ 25 us 1100 Æ 20 us 1101 Æ 15 us 1110 Æ 12 us 1111 Æ 10 us unused Enables overload current protection (OCP) for the PA: 0 Æ OCP disabled 1 Æ OCP enabled Trimming of OCP current: Imax = 45 + 5 × OcpTrim ( mA ) 95 mA OCP by default Note *Power Amplifier truth table is available in Table 10. Rev 2 - April 2012 Page 19 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 4.4. Receiver Registers Table 12 Receiver Registers Name (Address) Bits Variable Name Mode Default Description Value 0x40 unused Reserved14 (0x14) 7-0 - r Reserved15 (0x15) 7-0 - r 0xB0 unused Reserved16 (0x16) 7-0 - r 0x7B unused Reserved17 (0x17) 7-0 - r 0x9B unused LnaZin rw 1 * 6 5-3 2-0 LnaCurrentGain LnaGainSelect r r rw 0 001 000 7-5 DccFreq rw 010 * RegLna (0x18) RegRxBw (0x19) 7 4-3 RxBwMant rw 10 * 2-0 RxBwExp rw 101 * LNA’s input impedance 0 Æ 50 ohms 1 Æ 200 ohms unused Current LNA gain, set either manually, or by the AGC LNA gain setting: 000 Æ gain set by the internal AGC loop 001 Æ G1 = highest gain 010 Æ G2 = highest gain – 6 dB 011 Æ G3 = highest gain – 12 dB 100 Æ G4 = highest gain – 24 dB 101 Æ G5 = highest gain – 36 dB 110 Æ G6 = highest gain – 48 dB 111 Æ reserved Cut-off frequency of the DC offset canceller (DCC): 4 × RxBw fc = ----------------------------------------DccFreq + 2 2π × 2 ~4% of the RxBw by default Channel filter bandwidth control: 00 Æ RxBwMant = 16 10 Æ RxBwMant = 24 01 Æ RxBwMant = 20 11 Æ reserved Channel filter bandwidth control: FSK Mode: FXOSC RxBw = ----------------------------------------------------------------RxBwExp + 2 RxBwMant × 2 OOK Mode: FXOSC RxBw = ----------------------------------------------------------------RxBwExp + 3 RxBwMant × 2 RegAfcBw (0x1A) Rev 2 - April 2012 7-5 4-3 2-0 DccFreqAfc RxBwMantAfc RxBwExpAfc rw rw rw 100 01 011 * Page 20 See Table 13 for tabulated values DccFreq parameter used during the AFC RxBwMant parameter used during the AFC RxBwExp parameter used during the AFC www.semtech.com SX1231J WIRELESS & SENSING RegOokPeak (0x1B) RegOokAvg (0x1C) DATASHEET 7-6 OokThreshType rw 01 5-3 OokPeakTheshStep rw 000 2-0 OokPeakThreshDec rw 000 7-6 OokAverageThreshFilt rw 10 Selects type of threshold in the OOK data slicer: 00 Æ fixed 10 Æ average 01 Æ peak 11 Æ reserved Size of each decrement of the RSSI threshold in the OOK demodulator: 000 Æ 0.5 dB 001 Æ 1.0 dB 010 Æ 1.5 dB 011 Æ 2.0 dB 100 Æ 3.0 dB 101 Æ 4.0 dB 110 Æ 5.0 dB 111 Æ 6.0 dB Period of decrement of the RSSI threshold in the OOK demodulator: 000 Æ once per chip 001 Æ once every 2 chips 010 Æ once every 4 chips 011 Æ once every 8 chips 100 Æ twice in each chip 101 Æ 4 times in each chip 110 Æ 8 times in each chip 111 Æ 16 times in each chip Filter coefficients in average mode of the OOK demodulator: 00 Æ fC ≈ chip rate / 32.π 01 Æ fC ≈ chip rate / 8.π 10 Æ fC ≈ chip rate / 4.π RegOokFix (0x1D) 5-0 7-0 OokFixedThresh r rw 11 ÆfC ≈ chip rate / 2.π 000000 unused 0110 Fixed threshold value (in dB) in the OOK demodulator. (6dB) Used when OokThresType = 00 7 6 FeiDone r r 0 0 5 4 FeiStart AfcDone w r 0 1 3 AfcAutoclearOn rw 0 2 AfcAutoOn rw 0 1 0 7-0 AfcClear AfcStart AfcValue(15:8) w w r 0 0 0x00 RegAfcLsb (0x20) 7-0 AfcValue(7:0) r 0x00 RegFeiMsb (0x21) 7-0 FeiValue(15:8) r - MSB of the measured frequency offset, 2’s complement RegFeiLsb (0x22) 7-0 FeiValue(7:0) r - LSB of the measured frequency offset, 2’s complement Frequency error = FeiValue x Fstep RegRssiConfig (0x23) 7-2 1 RssiDone r r 0 7-0 RssiStart RssiValue w r RegAfcFei (0x1E) RegAfcMsb (0x1F) RegRssiValue (0x24) Rev 2 - April 2012 unused 0 Æ FEI is on-going 1 Æ FEI finished Triggers a FEI measurement when set. Always reads 0. 0 Æ AFC is on-going 1 Æ AFC has finished Only valid if AfcAutoOn is set 0 Æ AFC register is not cleared before a new AFC phase 1 Æ AFC register is cleared before a new AFC phase 0 Æ AFC is performed each time AfcStart is set 1 Æ AFC is performed each time Rx mode is entered Clears the AfcValue if set in Rx mode. Always reads 0 Triggers an AFC when set. Always reads 0. MSB of the AfcValue, 2’s complement format LSB of the AfcValue, 2’s complement format Frequency correction = AfcValue x Fstep 000000 unused 1 0 Æ RSSI is on-going 1 Æ RSSI sampling is finished, result available 0 Trigger a RSSI measurement when set. Always reads 0. 0xFF Absolute value of the RSSI in dBm, 0.5dB steps. RSSI = -RssiValue/2 [dBm] Page 21 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 4.5. IRQ and Pin Mapping Registers Table 13 IRQ and Pin Mapping Registers Name (Address) RegDioMapping1 (0x25) RegDioMapping2 (0x26) RegIrqFlags1 (0x27) Rev 2 - April 2012 Bits Variable Name Mode Default Value 00 00 00 00 00 00 0 111 * 7-6 5-4 3-2 1-0 7-6 5-4 3 2-0 Dio0Mapping Dio1Mapping Dio2Mapping Dio3Mapping Dio4Mapping Dio5Mapping ClkOut rw rw rw rw rw rw r rw 7 ModeReady r 1 6 RxReady r 0 5 TxReady r 0 4 PllLock r 0 3 Rssi rwc 0 2 Timeout r 0 1 AutoMode r 0 0 SyncAddressMatch r/rwc 0 Page 22 Description Mapping of pins DIO0 to DIO5 See Table 20 for mapping in Continuous mode See Table 21 for mapping in Packet mode unused Selects CLKOUT frequency: 000 Æ FXOSC 001 Æ FXOSC / 2 010 Æ FXOSC / 4 011 Æ FXOSC / 8 100 Æ FXOSC / 16 101 Æ FXOSC / 32 110 Æ RC (automatically enabled) 111 Æ OFF Set when the operation mode requested in Mode, is ready - Sleep: Entering Sleep mode - Standby: XO is running - FS: PLL is locked - Rx: RSSI sampling starts - Tx: PA ramp-up completed Cleared when changing operating mode. Set in Rx mode, after RSSI, AGC and AFC. Cleared when leaving Rx. Set in Tx mode, after PA ramp-up. Cleared when leaving Tx. Set (in FS, Rx or Tx) when the PLL is locked. Cleared when it is not. Set in Rx when the RssiValue exceeds RssiThreshold. Cleared when leaving Rx. Set when a timeout occurs (see TimeoutRxStart and TimeoutRssiThresh) Cleared when leaving Rx or FIFO is emptied. Set when entering Intermediate mode. Cleared when exiting Intermediate mode. Please note that in Sleep mode a small delay can be observed between AutoMode interrupt and the corresponding enter/exit condition. Set when Sync and Address (if enabled) are detected. Cleared when leaving Rx or FIFO is emptied. This bit is read only in Packet mode, rwc in Continuous mode www.semtech.com SX1231J WIRELESS & SENSING RegIrqFlags2 (0x28) DATASHEET 7 FifoFull r 0 6 5 FifoNotEmpty FifoLevel r r 0 0 4 FifoOverrun rwc 0 3 PacketSent r 0 2 PayloadReady r 0 1 CrcOk r 0 0 LowBat rwc - RegRssiThresh (0x29) 7-0 RssiThreshold rw 0xE4 * RegRxTimeout1 (0x2A) 7-0 TimeoutRxStart rw 0x00 RegRxTimeout2 (0x2B) 7-0 TimeoutRssiThresh rw 0x00 Rev 2 - April 2012 Page 23 Set when FIFO is full (i.e. contains 66 bytes), else cleared. Set when FIFO contains at least one byte, else cleared Set when the number of bytes in the FIFO strictly exceeds FifoThreshold, else cleared. Set when FIFO overrun occurs. (except in Sleep mode) Flag(s) and FIFO are cleared when this bit is set. The FIFO then becomes immediately available for the next transmission / reception. Set in Tx when the complete packet has been sent. Cleared when exiting Tx. Set in Rx when the payload is ready (i.e. last byte received and CRC, if enabled and CrcAutoClearOff is cleared, is Ok). Cleared when FIFO is empty. Set in Rx when the CRC of the payload is Ok. Cleared when FIFO is empty. Set when the battery voltage drops below the Low Battery threshold. Cleared only when set by the user. RSSI trigger level for Rssi interrupt : - RssiThreshold / 2 [dBm] Timeout interrupt is generated TimeoutRxStart*16*Tbit after switching to Rx mode if Rssi interrupt doesn’t occur (i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxStart is disabled Timeout interrupt is generated TimeoutRssiThresh*16*Tbit after Rssi interrupt if PayloadReady interrupt doesn’t occur. 0x00: TimeoutRssiThresh is disabled www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 4.6. Packet Engine Registers Table 14 Packet Engine Registers Name (Address) Bits Variable Name Mode Default Description Value 0x00 Size of the preamble to be sent (from TxStartCondition fulfilled). (MSB byte) RegPreambleMsb (0x2c) 7-0 PreambleSize(15:8) rw RegPreambleLsb (0x2d) 7-0 PreambleSize(7:0) rw 0x03 7 SyncOn rw 1 6 FifoFillCondition rw 0 5-3 SyncSize rw 011 2-0 7-0 SyncTol SyncValue(63:56) rw rw 000 0x01 * RegSyncValue2 (0x30) 7-0 SyncValue(55:48) rw 0x01 * 2nd byte of Sync word Used if SyncOn is set and (SyncSize +1) >= 2. RegSyncValue3 (0x31) 7-0 SyncValue(47:40) rw 0x01 * 3rd byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 3. RegSyncValue4 (0x32) 7-0 SyncValue(39:32) rw 0x01 * 4th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 4. RegSyncValue5 (0x33) 7-0 SyncValue(31:24) rw 0x01 * 5th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 5. RegSyncValue6 (0x34) 7-0 SyncValue(23:16) rw 0x01 * 6th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 6. RegSyncValue7 (0x35) 7-0 SyncValue(15:8) rw 0x01 * 7th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 7. RegSyncValue8 (0x36) 7-0 SyncValue(7:0) rw 0x01 * 8th byte of Sync word. Used if SyncOn is set and (SyncSize +1) = 8. RegSyncConfig (0x2e) RegSyncValue1 (0x2f) Rev 2 - April 2012 Page 24 Size of the preamble to be sent (from TxStartCondition fulfilled). (LSB byte) Enables the Sync word generation and detection: 0 Æ Off 1 Æ On FIFO filling condition: 0 Æ if SyncAddress interrupt occurs 1 Æ as long as FifoFillCondition is set Size of the Sync word: (SyncSize + 1) bytes Number of tolerated bit errors in Sync word 1st byte of Sync word. (MSB byte) Used if SyncOn is set. www.semtech.com SX1231J WIRELESS & SENSING PacketFormat rw 0 6-5 DcFree rw 00 4 CrcOn rw 1 3 CrcAutoClearOff rw 0 2-1 AddressFiltering rw 00 0 7-0 PayloadLength rw rw 0 0x40 RegNodeAdrs (0x39) 7-0 NodeAddress rw 0x00 Defines the packet format used: 0 Æ Fixed length 1 Æ Variable length Defines DC-free encoding/decoding performed: 00 Æ None (Off) 01 Æ Manchester 10 Æ Whitening 11 Æ reserved Enables CRC calculation/check (Tx/Rx): 0 Æ Off 1 Æ On Defines the behavior of the packet handler when CRC check fails: 0 Æ Clear FIFO and restart new packet reception. No PayloadReady interrupt issued. 1 Æ Do not clear FIFO. PayloadReady interrupt issued. Defines address based filtering in Rx: 00 Æ None (Off) 01 Æ Address field must match NodeAddress 10 Æ Address field must match NodeAddress or BroadcastAddress 11 Æ reserved unused If PacketFormat = 0 (fixed), payload length. If PacketFormat = 1 (variable), max length in Rx, not used in Tx. Node address used in address filtering. RegBroadcastAdrs (0x3A) 7-0 BroadcastAddress rw 0x00 Broadcast address used in address filtering. RegAutoModes (0x3B) 7-5 EnterCondition rw 000 4-2 ExitCondition rw 000 1-0 IntermediateMode rw 00 Interrupt condition for entering the intermediate mode: 000 Æ None (AutoModes Off) 001 Æ Rising edge of FifoNotEmpty 010 Æ Rising edge of FifoLevel 011 Æ Rising edge of CrcOk 100 Æ Rising edge of PayloadReady 101 Æ Rising edge of SyncAddress 110 Æ Rising edge of PacketSent 111 Æ Falling edge of FifoNotEmpty (i.e. FIFO empty) Interrupt condition for exiting the intermediate mode: 000 Æ None (AutoModes Off) 001 Æ Falling edge of FifoNotEmpty (i.e. FIFO empty) 010 Æ Rising edge of FifoLevel or Timeout 011 Æ Rising edge of CrcOk or Timeout 100 Æ Rising edge of PayloadReady or Timeout 101 Æ Rising edge of SyncAddress or Timeout 110 Æ Rising edge of PacketSent 111 Æ Rising edge of Timeout Intermediate mode: 00 Æ Sleep mode (SLEEP) 01 Æ Standby mode (STDBY) 10 Æ Receiver mode (RX) 11 Æ Transmitter mode (TX) RegPacketConfig1 (0x37) RegPayloadLength (0x38) Rev 2 - April 2012 7 DATASHEET Page 25 www.semtech.com SX1231J WIRELESS & SENSING RegFifoThresh (0x3C) RegPacketConfig2 (0x3D) 7 DATASHEET TxStartCondition rw FifoThreshold InterPacketRxDelay rw rw 3 2 RestartRx rw w 1 AutoRxRestartOn rw 0 AesOn rw 6-0 7-4 1 * Defines the condition to start packet transmission : 0 Æ FifoLevel (i.e. the number of bytes in the FIFO exceeds FifoThreshold) 1 Æ FifoNotEmpty (i.e. at least one byte in the FIFO) 0001111 Used to trigger FifoLevel interrupt. 0000 After PayloadReady occurred, defines the delay between FIFO empty and the start of a new RSSI phase for next packet. Must match the transmitter’s PA ramp-down time. - Tdelay = 0 if InterpacketRxDelay >= 12 - Tdelay = (2InterpacketRxDelay) / BitRate otherwise 0 unused 0 Forces the Receiver in WAIT mode, in Continuous Rx mode. Always reads 0. 1 Enables automatic Rx restart (RSSI phase) after PayloadReady occurred and packet has been completely read from FIFO: 0 Æ Off. RestartRx can be used. 1 Æ On. Rx automatically restarted after InterPacketRxDelay. 0 Enable the AES encryption/decryption: 0 Æ Off 1 Æ On (payload limited to 66 bytes maximum) 0x00 1st byte of cipher key (MSB byte) RegAesKey1 (0x3E) 7-0 AesKey(127:120) w RegAesKey2 (0x3F) 7-0 AesKey(119:112) w 0x00 2nd byte of cipher key RegAesKey3 (0x40) 7-0 AesKey(111:104) w 0x00 3rd byte of cipher key RegAesKey4 (0x41) 7-0 AesKey(103:96) w 0x00 4th byte of cipher key RegAesKey5 (0x42) 7-0 AesKey(95:88) w 0x00 5th byte of cipher key RegAesKey6 (0x43) 7-0 AesKey(87:80) w 0x00 6th byte of cipher key RegAesKey7 (0x44) 7-0 AesKey(79:72) w 0x00 7th byte of cipher key RegAesKey8 (0x45) 7-0 AesKey(71:64) w 0x00 8th byte of cipher key RegAesKey9 (0x46) 7-0 AesKey(63:56) w 0x00 9th byte of cipher key RegAesKey10 (0x47) 7-0 AesKey(55:48) w 0x00 10th byte of cipher key RegAesKey11 (0x48) 7-0 AesKey(47:40) w 0x00 11th byte of cipher key RegAesKey12 (0x49) 7-0 AesKey(39:32) w 0x00 12th byte of cipher key RegAesKey13 (0x4A) 7-0 AesKey(31:24) w 0x00 13th byte of cipher key Rev 2 - April 2012 Page 26 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET RegAesKey14 (0x4B) 7-0 AesKey(23:16) w 0x00 14th byte of cipher key RegAesKey15 (0x4C) 7-0 AesKey(15:8) w 0x00 15th byte of cipher key RegAesKey16 (0x4D) 7-0 AesKey(7:0) w 0x00 16th byte of cipher key (LSB byte) 4.7. Temperature Sensor Registers Table 15 Temperature Sensor Registers Name (Address) Bits Variable Name RegTemp1 (0x4E) 7-4 3 2 RegTemp2 (0x4F) 1-0 7-0 Mode TempMeasStart r w TempMeasRunning r TempValue r r Default Description Value 0000 unused 0 Triggers the temperature measurement when set. Always reads 0. 0 Set to 1 while the temperature measurement is running. Toggles back to 0 when the measurement has completed. The receiver can not be used while measuring temperature 01 unused Measured temperature -1°C per Lsb Needs calibration for accuracy 4.8. Test Registers Table 16 Test Registers Name (Address) RegTestLna (0x58) Bits Variable Name Mode 7-0 SensitivityBoost rw RegTestTcxo (0x59) 7-0 TcxoOn rw RegTestDagc (0x6F) 7-0 ContinuousDagc rw RegTestAfc (0x71) 7-0 LowBetaAfcOffset rw Rev 2 - April 2012 Default Description Value 0x1B High sensitivity or normal sensitivity mode: 0x1B Æ Normal mode 0x2D Æ High sensitivity mode 0x09 Selects XTAL or TCXO input: 0x09 Æ Normal XTAL mode 0x19 Æ Clipped sine TCXO input 0x30 Fading Margin Improvement, refer to 3.5.4 * 0x00 Æ Normal mode 0x20 Æ Improved margin, use if AfcLowBetaOn=1 0x30 Æ Improved margin, use if AfcLowBetaOn=0 0x00 AFC offset set for low modulation index systems, used if AfcLowBetaOn=1. Offset = LowBetaAfcOffset x 488 Hz Page 27 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 5. Application Information Application information shown here is SX1231J-specific. More application information relevant to the SX1231J can be found in [1]. 5.1. Reference Design Please contact your Semtech representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors. L3 C5 L4 C3 L2 C6 L1 R6 C7 C4 VBAT1 C2 C22 GND GND GND U2 C19 OPT1 C20 VDD GND Input OPT2 Vcont C21 GND R7 J1 UPG2010TB C23 C17 L5 C8 GND GND C18 GND GND GND GND RXTX VBAT1 VBAT1 R1 GND1 Shorted_res C1 10uF GND GND 19 20 GND RXTX 21 22 GND RFIO SCK GND RESET CLKOUT XTB DIO4 R5 GND GND VBAT2 P1 18 1 2 17 Header 2 16 POD_IN1 15 14 13 VBAT2 GND C15 100nF 12 C12 100nF 25 11 TXCO-32MHz C11 100nF MISO DIO3 6 C14 VR_DIG XTA GND GND NSS DIO2 Out 3 R2 Shorted_res MOSI 9 4 Vcc EN 2 R4 5 GND 1 GND 4 Q1 VBAT2 SX1231J VR_ANA 10 C13 Vcon 24 VR_PA 3 VBAT1 DIO1 2 VBAT1 DIO0 1 7 GND 8 C10 100nF PA_BOOST U1 23 GND2 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 VDD GND DIO3 MISO RESET DIO0 NC NC NC Vcon GND Header 10X2 GND GND SCK MOSI DIO1 NSS CLKOUT DIO4 RXTX DIO1 DIO2 NC GND R3 0R Figure 4. SX1231J Evaluation Module Schematics Rev 2 - April 2012 Page 28 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET Table 17 SX1231J Evaluation Module BOM Notes - Inductor values may change when using multilayer type components, but nearly equal performance should be attained - In very cost-sensitive and/or size-constrained applications where it is acceptable to degrade the receiver sensitivity, L5 and C17 and C18 can be omitted Rev 2 - April 2012 Page 29 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 5.2. Regulatory Compliance The SX1231J performance is such that it complies with narrowband and wideband Japanese regulations. This is mostly achieved thanks to the excellent spectral purity and best in-class Local Oscillator phase noise. 5.2.1. ARIB STD-T67 The ARIB STD-T67 standard mandates narrow 12.5kHz channels at about 426, 449 and 469MHz. With the proposed reference design, Semtech recommends the following RF settings: GFSK modulation, with BT=0.5 Bit Rate = 2.4 kbps, Fdev = +/-3 kHz RxBw = 5.2 kHz, corresponding to a double side bandwidth of 10.4 kHz Pout = +10 mW, as limited by STD-T67 Under these conditions, the SX1231J fulfills all the requirements of the STD-T67 with significant margin, namely: 99% energy bandwidth is lower than 8.5 kHz Spurious emissions meet the -26 dBm limit with more than 20 dB of margin Adjacent Channel leakage power with more than 15 dB margin The observed sensitivity is typ. -118 dBm with BER=0.1%, and -120 dBm with BER=1% Spurious response rejection does not apply with SX1231J’s Direct Conversion architecture At 12.5 kHz and 25 kHz offsets, the typical selectivity is respectively 36dB and 57dB (requirement: 30dB), and can be improved to typ. 55dB, respectively 59dB with the use of a tighter internal Channel Filter (RxBw=3.9 kHz). Using a narrower filter increases the constraint on the Local Oscillator stability accordingly (TCXO performance). Other sets of bit rates and deviation frequencies may of course be possible. 5.2.2. ARIB STD-T108 The ARIB STD-T108 standard focuses on wider channels of 200 kHz or more in the 915-930 MHz band. Under these conditions, there is more flexibility as to the choice of the RF settings. The SX1231J will fulfill the requirements of the STD-T108 in Middle Power (up to 250mW), Low Power (up to 20mW) and Ultra Low Power (up to 1mW) modes. An external Power Amplifier will be required to increase the output power over +17dBm. With its spectral purity, the SX1231J can meet the 99% energy bandwidth, spectral mask, Adjacent Channel Leakage Power and Spurious emissions limits of the standard with significant margin. In particular, the SX1231J complies with the radio Type 1 (+13dBm) constraints for Smart Metering and Sensor Networks applications, under the Common Signaling Mode as defined in the IEEE 802.15.4g. Please contact your local Semtech representative for a detailed report on the STD-T67 or STD-T108 compliance of the SX1231J. Rev 2 - April 2012 Page 30 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 6. Packaging Information 6.1. QFN 24 Encapsulation The SX1231J is available in a 24-lead QFN package as show in Figure 5. A DIMENSIONS MILLIMETERS MIN NOM MAX B D DIM E PIN 1 INDICATOR (LASER MARK) A1 A2 A SEATING PLANE aaa C A A1 A2 b D D1 E E1 e L N aaa bbb 0.80 1.00 0.00 0.05 - (0.20) 0.25 0.30 0.35 4.90 5.00 5.10 3.20 3.25 3.30 4.90 5.00 5.10 3.20 3.25 3.30 0.65 BSC 0.35 0.40 0.45 24 0.08 0.10 C LxN D1 E/2 E1 2 1 N bxN e/2 bbb C A B e D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Figure 5. QFN 24 Package Outline Drawing and Land Pattern 6.2. Thermal Impedance The thermal impedance of this package, calculated from a package in still air, on a 4-layer FR4 PCB, as per the Jedec standard, is Theta ja = 23.8° C/W typ. Rev 2 - April 2012 Page 31 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 6.3. Tape & Reel Specification Figure 6. Tape & Reel Specification, QFN Package Note Single Sprocket holes Rev 2 - April 2012 Page 32 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET 7. References [1] SX1231 Datasheet. Please consult the Semtech website www.semtech.com on a regular basis for news and updates. 8. Revision History Table 18 Revision History Revision 1 Date Jan 2012 2 April 2012 Rev 2 - April 2012 Comment First FINAL datasheet version Minor edits Mention STD-T108 Page 33 www.semtech.com SX1231J WIRELESS & SENSING DATASHEET © Semtech 2012 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Contact information Semtech Corporation Wireless & Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 E-mail: [email protected] [email protected] Internet: http://www.semtech.com Rev 2 - April 2012 Page 34 www.semtech.com