SEMTECH SX1231IMLTRT

SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX1231 Transceiver
Low Power Integrated UHF Transceiver
VR_DIG
RC
Oscillator
Mixers
Σ/Δ
Modulators
RSSI
AFC
GND
Division by
2, 4 or 6
PA_BOOST
PA1&2
Loop
Filter
Frac-N PLL
Synthesizer
GENERAL DESCRIPTION
Automated Meter Reading
Wireless Sensor Networks
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
GND
KEY PRODUCT FEATURES
The SX1231 is a highly integrated RF transceiver capable of
operation over a wide frequency range, including the 433,
868 and 915 MHz license-free ISM (Industry Scientific and
Medical) frequency bands. Its highly integrated architecture
allows for a minimum of external components whilst
maintaining maximum design flexibility. All major RF
communication parameters are programmable and most of
them can be dynamically set. The SX1231 offers the unique
advantage of programmable narrow-band and wide-band
communication modes without the need to modify external
components. The SX1231 is optimized for low power
consumption while offering high RF output power and
channelized operation, suitable for both the European (ETSI
EN 300-220-1) and the North American (FCC part 15)
regulatory standards. TrueRF™ technology enables a
lowcost external component count (elimination of the SAW
filter) whilst still satisfying ETSI and FCC regulations.
Š
Š
Š
Š
Š
RESET
SPI
DIO5
XO
32 MHz
XTAL
APPLICATIONS
Modulator
Ramp &
Control
VR_PA
Tank
Inductor
Interpolation
& Filtering
PA0
Packet Engine & 66 Bytes FIFO
Single to
Differential
Control Registers - Shift Registers - SPI Interface
LNA
RFIO
Demodulator &
Bit Synchronizer
VR_ANA
Power Distribution System
Decimation and
& Filtering
VBAT1&2
Š
Š
Š
High Sensitivity: down to -120 dBm at 1.2 kbps
Š
Š
Š
Š
Š
Š
Š
Š
Š
Š
Š
Low current: Rx = 16 mA, 100nA register retention
Š
Built-in temperature sensor and Low Battery indicator
High Selectivity: 16-tap FIR Channel Filter
Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Programmable Pout: -18 to +17 dBm in 1dB steps
Constant RF performance over voltage range of chip
FSK Bit rates up to 300 kb/s
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK and OOK modulations
Built-in Bit Synchronizer performing Clock Recovery
Incoming Sync Word Recognition
115 dB+ Dynamic Range RSSI
Automatic RF Sense with ultra-fast AFC
Packet engine with CRC, AES-128 encryption and 66byte FIFO
ORDERING INFORMATION
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
Š
Š
Rev 2 - Nov 2009
Page 1
Part Number
Delivery
MOQ / Multiple
SX1231IMLTRT
Tape & Reel
3000 pieces
QFN 24 Package - Operating Range [-40;+85°C]
Pb-free, Halogen free, RoHS/WEEE compliant product
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SX1231
ADVANCED COMMUNICATIONS & SENSING
Table of Contents
1.
2.
DATASHEET
Page
General Description ................................................................................................................................................ 8
1.1.
Simplified Block Diagram ................................................................................................................................ 8
1.2.
Pin and Marking Diagram ................................................................................................................................ 9
1.3.
Pin Description .............................................................................................................................................. 10
Electrical Characteristics....................................................................................................................................... 11
2.1.
ESD Notice.................................................................................................................................................... 11
2.2.
Absolute Maximum Ratings .......................................................................................................................... 11
2.3.
Operating Range........................................................................................................................................... 11
2.4.
Chip Specification ......................................................................................................................................... 12
2.4.1. Power Consumption ................................................................................................................................. 12
2.4.2. Frequency Synthesis ................................................................................................................................ 12
2.4.3. Receiver ................................................................................................................................................... 13
2.4.4. Transmitter ............................................................................................................................................... 14
2.4.5. Digital Specification ...................................................................................................................................15
3.
Chip Description.................................................................................................................................................... 16
3.1.
Power Supply Strategy.................................................................................................................................. 16
3.2.
Low Battery Detector..................................................................................................................................... 16
3.3.
Frequency Synthesis..................................................................................................................................... 16
3.3.1. Reference Oscillator ................................................................................................................................. 16
3.3.2. CLKOUT Output ........................................................................................................................................17
3.3.3. PLL Architecture ....................................................................................................................................... 17
3.3.4. Lock Time ..................................................................................................................................................18
3.3.5. Lock Detect Indicator................................................................................................................................ 18
3.4.
Transmitter Description ................................................................................................................................. 19
3.4.1. Architecture Description ........................................................................................................................... 19
3.4.2. Bit Rate Setting ........................................................................................................................................ 19
3.4.3. FSK Modulation ........................................................................................................................................ 20
3.4.4. OOK Modulation ....................................................................................................................................... 20
3.4.5. Modulation Shaping.................................................................................................................................. 21
3.4.6. Power Amplifiers ...................................................................................................................................... 21
3.4.7. Over Current Protection ........................................................................................................................... 21
3.5.
Receiver Description ..................................................................................................................................... 22
3.5.1. Block Diagram .......................................................................................................................................... 22
3.5.2. LNA - Single to Differential Buffer ............................................................................................................ 22
3.5.3. Automatic Gain Control ............................................................................................................................ 23
3.5.4. Quadrature Mixer - ADCs - Decimators.................................................................................................... 24
3.5.5. Channel Filter ........................................................................................................................................... 25
3.5.6. DC Cancellation ....................................................................................................................................... 26
3.5.7. Complex Filter - OOK ............................................................................................................................... 26
3.5.8. RSSI ......................................................................................................................................................... 26
Rev 2 - Nov 2009
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
3.5.9. Cordic ....................................................................................................................................................... 26
3.5.10. FSK Demodulator ................................................................................................................................... 27
3.5.11. OOK Demodulator .................................................................................................................................. 27
3.5.12. Bit Synchronizer ..................................................................................................................................... 29
3.5.13. Frequency Error Indicator....................................................................................................................... 30
3.5.14. Automatic Frequency Correction ............................................................................................................ 31
3.5.15. Temperature Sensor .............................................................................................................................. 31
3.5.16. Timeout Function.................................................................................................................................... 32
4.
Operating Modes .................................................................................................................................................. 33
4.1.
Basic Modes.................................................................................................................................................. 33
4.2.
Automatic Sequencer and Wake-Up Times .................................................................................................. 33
4.2.1. Transmitter Startup Time........................................................................................................................... 34
4.2.2. Tx Start Procedure ................................................................................................................................... 34
4.2.3. Receiver Startup Time.............................................................................................................................. 34
4.2.4. Rx Start Procedure ................................................................................................................................... 36
4.2.5. Optimized Frequency Hopping Sequences .............................................................................................. 36
5.
4.3.
Listen mode ................................................................................................................................................... 37
4.4.
AutoModes .................................................................................................................................................... 40
Data Processing.................................................................................................................................................... 41
5.1.
Overview ....................................................................................................................................................... 41
5.1.1. Block Diagram .......................................................................................................................................... 41
5.1.2. Data Operation Modes ............................................................................................................................. 41
5.2.
Control Block Description.............................................................................................................................. 42
5.2.1. SPI Interface............................................................................................................................................. 42
5.2.2. FIFO ......................................................................................................................................................... 43
5.2.3. Sync Word Recognition ............................................................................................................................ 44
5.2.4. Packet Handler ......................................................................................................................................... 45
5.2.5. Control ...................................................................................................................................................... 45
5.3.
Digital IO Pins Mapping................................................................................................................................. 45
5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 46
5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 46
5.4.
Continuous Mode .......................................................................................................................................... 47
5.4.1. General Description.................................................................................................................................. 47
5.4.2. Tx Processing........................................................................................................................................... 47
5.4.3. Rx Processing .......................................................................................................................................... 48
5.5.
Packet Mode ................................................................................................................................................. 48
5.5.1. General Description.................................................................................................................................. 48
5.5.2. Packet Format .......................................................................................................................................... 49
5.5.3. Tx Processing (without AES).................................................................................................................... 51
5.5.4. Rx Processing (without AES) ................................................................................................................... 52
5.5.5. AES .......................................................................................................................................................... 52
5.5.6. Packet Filtering......................................................................................................................................... 54
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
5.5.7. DC-Free Data Mechanisms ...................................................................................................................... 55
6.
7.
Configuration and Status Registers ...................................................................................................................... 57
6.1.
General Description ...................................................................................................................................... 57
6.2.
Common Configuration Registers ................................................................................................................. 60
6.3.
Transmitter Registers .................................................................................................................................... 63
6.4.
Receiver Registers........................................................................................................................................ 64
6.5.
IRQ and Pin Mapping Registers.................................................................................................................... 67
6.6.
Packet Engine Registers............................................................................................................................... 69
6.7.
Temperature Sensor Registers ..................................................................................................................... 72
6.8.
Test Registers ............................................................................................................................................... 72
Application Information ......................................................................................................................................... 73
7.1.
Crystal Resonator Specification .................................................................................................................... 73
7.2.
Reset of the Chip .......................................................................................................................................... 73
7.2.1. POR.......................................................................................................................................................... 73
7.2.2. Manual Reset ............................................................................................................................................74
8.
9.
7.3.
RC Oscillator Calibration............................................................................................................................... 74
7.4.
Reference Design ......................................................................................................................................... 74
Packaging Information .......................................................................................................................................... 75
8.1.
Package Outline Drawing.............................................................................................................................. 75
8.2.
Recommended Land Pattern ........................................................................................................................ 75
8.3.
Thermal Impedance ...................................................................................................................................... 76
8.4.
Tape & Reel Specification............................................................................................................................. 76
Revision History .................................................................................................................................................... 77
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
Index of Figures
DATASHEET
Page
Figure 1. Block Diagram ................................................................................................................................................ 8
Figure 2. Pin Diagram .................................................................................................................................................... 9
Figure 3. Marking Diagram ............................................................................................................................................ 9
Figure 4. TCXO Connection ........................................................................................................................................ 16
Figure 5. Transmitter Block Diagram ........................................................................................................................... 19
Figure 6. Receiver Block Diagram ............................................................................................................................... 22
Figure 7. AGC Thresholds Settings ............................................................................................................................. 23
Figure 8. Cordic Extraction .......................................................................................................................................... 27
Figure 9. OOK Peak Demodulator Description ............................................................................................................ 27
Figure 10. Floor Threshold Optimization ..................................................................................................................... 28
Figure 11. Bit Synchronizer Description ...................................................................................................................... 29
Figure 12. FEI Process ................................................................................................................................................ 31
Figure 13. Temperature Sensor Response ................................................................................................................. 32
Figure 14. Tx Startup, FSK and OOK .......................................................................................................................... 34
Figure 15. Rx Startup - No AGC, no AFC .................................................................................................................... 35
Figure 16. Rx Startup - AGC, no AFC ......................................................................................................................... 35
Figure 17. Rx Startup - AGC and AFC ........................................................................................................................ 35
Figure 18. Listen Mode Sequence (no wanted signal is received) .............................................................................. 37
Figure 19. Listen Mode Sequence (wanted signal is received) ................................................................................... 39
Figure 20. Auto Modes of Packet Handler ................................................................................................................... 40
Figure 21. SX1231 Data Processing Conceptual View ............................................................................................... 41
Figure 22. SPI Timing Diagram (single access) .......................................................................................................... 42
Figure 23. FIFO and Shift Register (SR) ..................................................................................................................... 43
Figure 24. FifoLevel IRQ Source Behavior .................................................................................................................. 44
Figure 25. Sync Word Recognition .............................................................................................................................. 45
Figure 26. Continuous Mode Conceptual View ........................................................................................................... 47
Figure 27. Tx Processing in Continuous Mode ............................................................................................................ 47
Figure 28. Rx Processing in Continuous Mode ........................................................................................................... 48
Figure 29. Packet Mode Conceptual View ................................................................................................................... 49
Figure 30. Fixed Length Packet Format ...................................................................................................................... 50
Figure 31. Variable Length Packet Format .................................................................................................................. 50
Figure 32. Unlimited Length Packet Format ................................................................................................................ 51
Figure 33. CRC Implementation .................................................................................................................................. 55
Figure 34. Manchester Encoding/Decoding ................................................................................................................. 56
Figure 35. Data Whitening ........................................................................................................................................... 56
Figure 36. POR Timing Diagram ................................................................................................................................. 73
Figure 37. Manual Reset Timing Diagram ................................................................................................................... 74
Figure 38. Package Outline Drawing ........................................................................................................................... 75
Figure 39. Recommended Land Pattern ..................................................................................................................... 75
Figure 40. Tape & Reel Specification .......................................................................................................................... 76
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
Index of Tables
DATASHEET
Page
Table 1. SX1231 Pinouts .............................................................................................................................................. 10
Table 2. Absolute Maximum Ratings ............................................................................................................................ 11
Table 3. Operating Range ............................................................................................................................................ 11
Table 4. Power Consumption Specification .................................................................................................................. 12
Table 5. Frequency Synthesizer Specification .............................................................................................................. 12
Table 6. Receiver Specification .................................................................................................................................... 13
Table 7. Transmitter Specification ................................................................................................................................ 14
Table 8. Digital Specification ........................................................................................................................................ 15
Table 9. Bit Rate Examples .......................................................................................................................................... 20
Table 10. Power Amplifier Mode Selection Truth Table ............................................................................................... 21
Table 11. LNA Gain Settings ........................................................................................................................................ 22
Table 12. Receiver Performance Summary .................................................................................................................. 24
Table 13. Available RxBw Settings ............................................................................................................................... 25
Table 14. Basic Transceiver Modes ............................................................................................................................. 33
Table 15. Range of Durations in Listen Mode .............................................................................................................. 37
Table 16. Signal Acceptance Criteria in Listen Mode ................................................................................................... 38
Table 17. End of Listen Cycle Actions .......................................................................................................................... 38
Table 18. Status of FIFO when Switching Between Different Modes of the Chip ......................................................... 44
Table 19. DIO Mapping, Continuous Mode .................................................................................................................. 46
Table 20. DIO Mapping, Packet Mode ......................................................................................................................... 46
Table 21. Registers Summary ...................................................................................................................................... 57
Table 22. Common Configuration Registers ................................................................................................................. 60
Table 23. Transmitter Registers ................................................................................................................................... 63
Table 24. Receiver Registers ....................................................................................................................................... 64
Table 25. IRQ and Pin Mapping Registers ................................................................................................................... 67
Table 26. Packet Engine Registers .............................................................................................................................. 69
Table 27. Temperature Sensor Registers ..................................................................................................................... 72
Table 28. Test Registers .............................................................................................................................................. 72
Table 29. Crystal Specification ..................................................................................................................................... 73
Table 30. Revision History ............................................................................................................................................ 77
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
Acronyms
BOM
BR
BW
CCITT
CRC
DAC
ETSI
FCC
Fdev
FIFO
FIR
FS
FSK
GUI
IC
ID
IF
IRQ
ITU
LFSR
LNA
LO
Rev 2 - Nov 2009
Bill Of Materials
Bit Rate
Bandwidth
Comité Consultatif International
Téléphonique et Télégraphique - ITU
Cyclic Redundancy Check
Digital to Analog Converter
European Telecommunications Standards
Institute
Federal Communications Commission
Frequency Deviation
First In First Out
Finite Impulse Response
Frequency Synthesizer
Frequency Shift Keying
Graphical User Interface
Integrated Circuit
IDentificator
Intermediate Frequency
Interrupt ReQuest
International Telecommunication Union
Linear Feedback Shift Register
Low Noise Amplifier
Local Oscillator
Page 7
LSB
MSB
NRZ
OOK
Least Significant Bit
Most Significant Bit
Non Return to Zero
On Off Keying
PA
PCB
PLL
Power Amplifier
Printed Circuit Board
Phase-Locked Loop
POR
RBW
RF
RSSI
Rx
SAW
SPI
SR
Stby
Tx
uC
VCO
XO
XOR
Power On Reset
Resolution BandWidth
Radio Frequency
Received Signal Strength Indicator
Receiver
Surface Acoustic Wave
Serial Peripheral Interface
Shift Register
Standby
Transmitter
Microcontroller
Voltage Controlled Oscillator
Crystal Oscillator
eXclusive OR
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
This product datasheet contains a detailed description of the SX1231 performance and functionality. Please consult the
Semtech website for the latest updates or errata.
1. General Description
The SX1231 is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The
SX1231's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high
level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended
for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bi-directional
RF links, and where stable and constant RF performance is required over the full operating range of the device down to
1.8V.
The SX1231 is intended for applications over a wide frequency range, including the 433 MHz and 868 MHz European and
the 902-928 MHz North American ISM bands. Coupled with a link budget in excess of 135 dB, the advanced system
features of the SX1231 include a 66 byte TX/RX FIFO, configurable automatic packet handler, listen mode, temperature
sensor and configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU
requirements.
The SX1231 complies with both ETSI and FCC regulatory requirements and is available in a 5x 5 mm QFN 24 lead
package
1.1. Simplified Block Diagram
VR_DIG
RC
Oscillator
Power Distribution System
RFIO
Demodulator &
Bit Synchronizer
Σ/Δ
Modulators
Mixers
Single to
Differential
Decimation and
& Filtering
LNA
RSSI
AFC
GND
Division by
2, 4 or 6
Ramp &
Control
Frac-N PLL
Synthesizer
Loop
Filter
Modulator
VR_PA
Tank
Inductor
Interpolation
& Filtering
PA0
PA1&2
RESET
SPI
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
XO
32 MHz
PA_BOOST
Control Registers - Shift Registers - SPI Interface
VR_ANA
Packet Engine & 66 Bytes FIFO
VBAT1&2
XTAL
GND
Frequency Synthesis
Transmitter Blocks
Primarily Analog
Receiver Blocks
Control Blocks
Primarily Digital
Figure 1. Block Diagram
Rev 2 - Nov 2009
Page 8
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
1.2. Pin and Marking Diagram
The following diagram shows the pin arrangement of the QFN package, top view.
Figure 2. Pin Diagram
Figure 3. Marking Diagram
Notes yyww refers to the date code
xxxxxx refers to the lot number
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
1.3. Pin Description
Table 1
SX1231 Pinouts
Rev 2 - Nov 2009
Number
Name
Type
Description
0
GROUND
-
Exposed ground pad
1
VBAT1
-
Supply voltage
2
VR_ANA
-
Regulated supply voltage for analogue circuitry
3
VR_DIG
-
Regulated supply voltage for digital blocks
4
XTA
I/O
XTAL connection
5
XTB
I/O
XTAL connection
6
RESET
I/O
Reset trigger input
7
DIO0
I/O
Digital I/O, software configured
8
DIO1/DCLK
I/O
Digital I/O, software configured
9
DIO2/DATA
I/O
Digital I/O, software configured
10
DIO3
I/O
Digital I/O, software configured
11
DIO4
I/O
Digital I/O, software configured
12
DIO5
I/O
Digital I/O, software configured
13
VBAT2
-
Supply voltage
14
GND
-
Ground
15
SCK
I
SPI Clock input
16
MISO
O
SPI Data output
17
MOSI
I
SPI Data input
18
NSS
I
SPI Chip select input
19
RXTX
O
Rx/Tx switch control: high in Tx
20
GND
-
Ground
21
RFIO
I/O
22
GND
-
Ground
23
PA_BOOST
O
Optional high-power PA output
24
VR_PA
-
Regulated supply for the PA
RF input / output
Page 10
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ADVANCED COMMUNICATIONS & SENSING
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2. Electrical Characteristics
2.1. ESD Notice
The SX1231 is a high performance radio frequency device. It satisfies:
Š
Š
Š
Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins.
Class B of the JEDEC standard JESD22-A115-A (Machine Model) on all pins.
Class IV of the JEDEC standard JESD22-C101C (Charged Device Model) on pins 2-3-21-23-24, Class III on all other
pins.
It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 2
Absolute Maximum Ratings
Symbol
Description
Min
Max
Unit
VDDmr
Supply Voltage
-0.5
3.9
V
Tmr
Temperature
-55
+115
°C
Tj
Junction temperature
-
+125
°C
Pmr
RF Input Level
-
+6
Min
Max
dBm
2.3. Operating Range
Table 3
Operating Range
Symbol
Description
Unit
VDDop
Supply voltage
1.8
3.6
V
Top
Operational temperature range
-40
+85
°C
Clop
Load capacitance on digital ports
-
25
pF
ML
RF Input Level
-
0
dBm
Rev 2 - Nov 2009
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
2.4. Chip Specification
The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VBAT1=
VBAT2=VDD=3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 915 MHz, Pout = +13dBm, 2-level FSK modulation
without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise
specified.
Note
Unless otherwise specified, the performances in the other frequency bands are similar or better.
2.4.1. Power Consumption
Table 4 Power Consumption Specification
Symbol
Description
IDDSL
Supply current in Sleep mode
IDDIDLE
Supply current in Idle mode
IDDST
Supply current in Standby mode
IDDFS
Conditions
Min
Typ
Max
-
0.1
1
uA
RC oscillator enabled
-
1.2
-
uA
Crystal oscillator enabled
-
1.25
1.5
mA
Supply current in Synthesizer
mode
-
9
-
mA
IDDR
Supply current in Receive mode
-
16
-
mA
IDDT
Supply current in Transmit mode
with appropriate matching, stable across VDD range
-
95
45
33
20
16
-
mA
mA
mA
mA
mA
RFOP = +17 dBm, on PA_BOOST
RFOP = +13 dBm, on RFIO pin
RFOP = +10 dBm, on RFIO pin
RFOP = 0 dBm, on RFIO pin
RFOP = -1 dBm, on RFIO pin
Unit
2.4.2. Frequency Synthesis
Table 5 Frequency Synthesizer Specification
Symbol
Description
Conditions
Min
Typ
Max
FR
Synthesizer Frequency Range
Programmable
290
424
862
-
340
510
1020
MHz
MHz
MHz
FXOSC
Crystal oscillator frequency
See section 7.1
-
32
-
MHz
TS_OSC
Crystal oscillator wake-up time
-
250
500
us
TS_FS
Frequency synthesizer wake-up
time to PllLock signal
-
80
150
us
TS_HOP
Frequency synthesizer hop time
at most 10 kHz away from the
target
-
20
20
50
50
80
80
80
-
us
us
us
us
us
us
us
FSTEP
Frequency synthesizer step
-
61.0
-
Hz
Rev 2 - Nov 2009
From Standby mode
200 kHz step
1 MHz step
5 MHz step
7 MHz step
12 MHz step
20 MHz step
25 MHz step
FSTEP = FXOSC/219
Page 12
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FRC
RC Oscillator frequency
After calibration
-
62.5
-
kHz
BRF
Bit rate, FSK
Programmable
1.2
-
300
kbps
BRO
Bit rate, OOK
Programmable
1.2
-
32.768
kbps
FDA
Frequency deviation, FSK
Programmable
FDA + BRF/2 =< 500 kHz
0.6
-
300
kHz
2.4.3. Receiver
All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a
PN15 sequence with a BER of 0.1% (Bit Synchronizer is enabled), unless otherwise specified. The LNA impedance is set
to 200 Ohms, by setting bit LnaZin in RegLna to 1, and the AdcLowPowerOn in RegTemp is set to 1. Blocking tests are
performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR
tests is set 3 dB above the nominal sensitivity level.
Table 6
Receiver Specification
Symbol
Description
Conditions
Min
Typ
Max
RFS_F
FSK sensitivity, highest LNA gain
Unit
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s
-
-118
-114
-105
-
dBm
dBm
dBm
FDA = 5 kHz, BR = 1.2 kb/s *
-
-120
-
dBm
BR = 4.8 kb/s
-
-112
-109
dBm
-13
-10
-
dB
RFS_O
OOK sensitivity, highest LNA gain
CCR
Co-Channel Rejection
ACR
Adjacent Channel Rejection
Offset = +/- 25 kHz
Offset = +/- 50 kHz
37
42
42
-
dB
dB
BI
Blocking Immunity
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
-45
-40
-32
-
dBm
dBm
dBm
Blocking Immunity
Wanted signal at sensitivity
+16dB
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
-36
-33
-25
-
dBm
dBm
dBm
AMR
AM Rejection , AM modulated
interferer with 100% modulation
depth, fm = 1 kHz, square
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
-45
-40
-32
-
dB
dB
dB
IIP2
2nd order Input Intercept Point
Unwanted tones are 20 MHz
above the LO
Lowest LNA gain
Highest LNA gain
-
+75
+35
-
dBm
dBm
IIP3
3rd order Input Intercept point
Unwanted tones are 1MHz and
1.995 MHz above the LO
Lowest LNA gain
Highest LNA gain
-23
+20
-18
-
dBm
dBm
BW_SSB
Single Side channel filter BW
2.6
-
500
kHz
Rev 2 - Nov 2009
Programmable
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SX1231
ADVANCED COMMUNICATIONS & SENSING
*
DATASHEET
IMR_OOK
Image rejection in OOK mode
Wanted signal level = -106 dBm
27
30
-
dB
TS_RE
Receiver wake-up time, from PLL
locked state to RxReady
RxBw = 10 kHz, BR = 4.8 kb/s
RxBw = 200 kHz, BR = 100 kb/s
-
1.7
96
-
ms
us
TS_RE_AGC
Receiver wake-up time, from PLL
locked state, AGC enabled
RxBw= 10 kHz, BR = 4.8 kb/s
RxBw = 200 kHz, BR = 100 kb/s
-
3.0
163
ms
us
TS_RE_AGC
&AFC
Receiver wake-up time, from PLL
lock state, AGC and AFC enabled
RxBw= 10 kHz, BR = 4.8 kb/s
RxBw = 200 kHz, BR = 100 kb/s
4.8
265
ms
us
TS_FEI
FEI sampling time
Receiver is ready
-
4.Tbit
-
-
TS_AFC
AFC Response Time
Receiver is ready
-
4.Tbit
-
-
TS_RSSI
RSSI Response Time
Receiver is ready
-
2.Tbit
-
-
DR_RSSI
RSSI Dynamic Range
AGC enabled
-
-115
0
-
dBm
dBm
Min
Max
Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver
2.4.4. Transmitter
Table 7 Transmitter Specification
Symbol
Description
Conditions
Min
Typ
Max
RF_OP
RF output power in 50 ohms
On RFIO pin
Programmable with 1dB steps
-
+13
-18
-
dBm
dBm
RF_OPH
Max RF output power, on
PA_BOOST pin
With external match to 50 ohms
-
+17
-
dBm
ΔRF_OP
RF output power stability
From VDD=1.8V to 3.6V
-
+/-0.3
-
dB
PHN
Transmitter Phase Noise
50 kHz Offset from carrier
868 / 915 MHz bands
434 / 315 MHz bands
-
-95
-99
-
dBc/
Hz
dBm
Max
Min
ACP
Transmitter adjacent channel
power (measured at 25 kHz offset)
BT=0.5 . Measurement conditions as
defined by EN 300 220-1 V2.1.1
-
-
-37
TS_TR
Transmitter wake up time, to the
first rising edge of DCLK
Frequency Synthesizer enabled,
PaRamp = 8us, BR = 4.8 kb/s.
-
120
-
Rev 2 - Nov 2009
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
2.4.5. Digital Specification
Conditions: Temp = 25°C, VDD = 3.3V, FXOSC = 32 MHz, unless otherwise specified.
Table 8
Digital Specification
Symbol
Description
VIH
Min
Typ
Max
Digital input level high
0.8
-
-
VDD
VIL
Digital input level low
-
-
0.2
VDD
VOH
Digital output level high
Imax = 1 mA
0.9
-
-
VDD
VOL
Digital output level low
Imax = -1 mA
-
-
0.1
VDD
FSCK
SCK frequency
-
-
10
MHz
tch
SCK high time
50
-
-
ns
tcl
SCK low time
50
-
-
ns
trise
SCK rise time
-
5
-
ns
tfall
SCK fall time
-
5
-
ns
tsetup
MOSI setup time
from MOSI change to SCK rising
edge
30
-
-
ns
thold
MOSI hold time
from SCK rising edge to MOSI
change
60
-
-
ns
tnsetup
NSS setup time
from NSS falling edge to SCK rising
edge
30
-
-
ns
tnhold
NSS hold time
from SCK falling edge to NSS rising
edge, normal mode
30
-
-
ns
tnhigh
NSS high time between SPI
accesses
20
-
-
ns
T_DATA
DATA hold and setup time
250
-
-
ns
Rev 2 - Nov 2009
Conditions
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ADVANCED COMMUNICATIONS & SENSING
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3. Chip Description
This section describes in depth the architecture of the SX1231 low-power, highly integrated transceiver.
3.1. Power Supply Strategy
The SX1231 employs an advanced power supply scheme, which provides stable operating characteristics over the full
temperature and voltage range of operation. This includes the full output power of +17dBm which is maintained from 1.8 to
3.6 V.
The SX1231 can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling capacitors should
be connected, as suggested in the reference design, on VR_PA, VR_DIG and VR_ANA pins to ensure a correct operation
of the built-in voltage regulators.
3.2. Low Battery Detector
A low battery detector is also included allowing the generation of an interrupt signal in response to passing a
programmable threshold adjustable through the register RegLowBat. The interrupt signal can be mapped to any of the DIO
pins, through the programmation of RegDioMapping.
3.3. Frequency Synthesis
The LO generation on the SX1231 is based on a state-of-the-art fractional-N PLL. The PLL is fully integrated with
automatic calibration.
3.3.1. Reference Oscillator
The crystal oscillator is the main timing reference of the SX1231. It is used as a reference for the frequency synthesizer
and as a clock for the digital processing.
The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the builtin sequencer, the SX1231 optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To
manually control the startup time, the user should either wait for TS_OSC max, or monitor the signal CLKOUT which will
only be made available on the output buffer when a stable XO oscillation is achieved.
An external clock can be used to replace the crystal oscillator, for instance a tight tolerance TCXO. To do so, bit 4 at
address 0x59 should be set to 1, and the external clock has to be provided on XTA (pin 4). XTB (pin 5) should be left open.
The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an
appropriate value of decoupling capacitor, CD.
XTA
XTB
NC
TCXO
32 MHz
OP
Vcc
GND
Vcc
CD
Figure 4. TCXO Connection
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
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3.3.2. CLKOUT Output
The reference frequency, or a fraction of it, can be provided on DIO5 (pin 12) by modifying bits ClkOut in RegDioMapping2.
Two typical applications of the CLKOUT output include:
Š
To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be
made available in any operation mode except Sleep mode and is automatically enabled at power on reset.
Š
To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the
initial crystal tolerance.
Note
to minimize the current consumption of the SX1231, please ensure that the CLKOUT signal is disabled when not
required.
3.3.3. PLL Architecture
The frequency synthesizer generating the LO frequency for both the receiver and the transmitter is a fractional-N sigmadelta PLL. The PLL incorporates a third order loop capable of fast auto-calibration, and it has a fast switching-time. The
VCO and the loop filter are both fully integrated, removing the need for an external tight-tolerance, high-Q inductor in the
VCO tank circuit.
3.3.3.1. VCO
The VCO runs at 2, 4 or 6 times the RF frequency (respectively in the 915, 434 and 315 MHz bands) to reduce any LO
leakage in receiver mode, to improve the quadrature precision of the receiver, and to reduce the pulling effects on the VCO
during transmission.
The VCO calibration is fully automated. A coarse adjustment is carried out at power on reset, and a fine tuning is
performed each time the SX1231 PLL is activated. Automatic calibration times are fully transparent to the end-user, as their
processing time is included in the TS_TE and TS_RE specifications.
3.3.3.2. PLL Bandwidth
The bandwidth of the SX1231 Fractional-N PLL is wide enough to allow for:
Š
Š
High speed FSK modulation, up to 300 kb/s, inside the PLL bandwidth
Very fast PLL lock times, enabling both short startup and fast hop times required for frequency agile applications
3.3.3.3. Carrier Frequency and Resolution
The SX1231 PLL embeds a 19-bit sigma-delta modulator and its frequency resolution, constant over the whole frequency
range, and is given by:
F XOSC
F STEP = --------------19
2
The carrier frequency is programmed through RegFrf, split across addresses 0x07 to 0x09:
F RF = F STEP × Frf (23,0)
Note
The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the
least significant byte FrfLsb in RegFrfLsb is written. This allows for more complex modulation schemes such as mary FSK, where frequency modulation is achieved by changing the programmed RF frequency.
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
3.3.4. Lock Time
PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc.
When using the built-in sequencer, the SX1231 optimizes the startup time and automatically starts the receiver or the
transmitter when the PLL has locked. To manually control the startup time, the user should either wait for TS_FS max given
in the specification, or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking
range.
When performing an AFC, which usually corrects very small frequency errors, the PLL response time is approximately:
5
T PLLAFC = -------------------PLLBW
In a frequency hopping scheme, the timings TS_HOP given in the table of specifications give an order of magnitude for the
expected lock times.
3.3.5. Lock Detect Indicator
A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL reaches its
locking range. Please refer to Table 19 and Table 20 to map this interrupt to the desired pins.
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
3.4. Transmitter Description
The transmitter of SX1231 comprises the frequency synthesizer, modulator and power amplifier blocks.
3.4.1. Architecture Description
LNA
Receiver Chain
RFIO
PA0
Local
Oscillator
PA1
PA_BOOST
PA2
Figure 5. Transmitter Block Diagram
3.4.2. Bit Rate Setting
When using the SX1231 in Continuous mode, the data stream to be transmitted can be input directly to the modulator via
pin 9 (DIO2/DATA) in an asynchronous manner, unless Gaussian filtering is used, in which case the DCLK signal on pin 10
(DIO1/DCLK) is used to synchronize the data stream. See section 3.4.5 for details on the Gaussian filter.
In Packet mode or in Continuous mode with Gaussian filtering enabled (refer to section 5.5 for details), the Bit Rate (BR) is
controlled by bits BitRate in RegBitrate:
F XOSC
BR = -------------------BitRate
Amongst others, the following Bit Rates are accessible:
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SX1231
ADVANCED COMMUNICATIONS & SENSING
Table 9
DATASHEET
Bit Rate Examples
BitRate
(15:8)
BitRate
(7:0)
(G)FSK
(G)MSK
OOK
Actual BR
(b/s)
0x68
0x2B
1.2 kbps
1.2 kbps
1200.015
0x34
0x15
2.4 kbps
2.4 kbps
2400.060
0x1A
0x0B
4.8 kbps
4.8 kbps
4799.760
0x0D
0x05
9.6 kbps
9.6 kbps
9600.960
0x06
0x83
19.2 kbps
19.2 kbps
19196.16
0x03
0x41
38.4 kbps
38415.36
0x01
0xA1
76.8 kbps
76738.60
0x00
0xD0
153.6 kbps
153846.1
Classical modem baud rates
(multiples of 0.9 kbps)
0x02
0x2C
57.6 kbps
57553.95
0x01
0x16
115.2 kbps
115107.9
Round bit rates
(multiples of 12.5, 25 and
50 kbps)
0x0A
0x00
12.5 kbps
12.5 kbps
12500.00
0x05
0x00
25 kbps
25 kbps
25000.00
0x80
0x00
50 kbps
50000.00
0x01
0x40
100 kbps
100000.0
0x00
0xD5
150 kbps
150234.7
0x00
0xA0
200 kbps
200000.0
0x00
0x80
250 kbps
250000.0
0x00
0x6B
300 kbps
299065.4
0x03
0xD1
32.768 kbps
Type
Classical modem baud rates
(multiples of 1.2 kbps)
Watch Xtal frequency
32.768 kbps
32753.32
3.4.3. FSK Modulation
FSK modulation is performed inside the PLL bandwidth, by changing the fractional divider ratio in the feedback loop of the
PLL. The large resolution of the sigma-delta modulator, allows for very narrow frequency deviation. The frequency
deviation FDEV is given by:
F DEV = F STEP × Fdev (13,0)
To ensure a proper modulation, the following limit applies:
BR
F DEV + ------- ≤ 500kHz
2
Note
no constraint applies to the modulation index of the transmitter, but the frequency deviation must exceed 600 Hz.
3.4.4. OOK Modulation
OOK modulation is applied by switching on and off the Power Amplifier. Digital control and smoothing are available to
improve the transient power response of the OOK transmitter.
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
3.4.5. Modulation Shaping
Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrowband response of the
transmitter. Both shaping features are controlled with PaRamp bits in RegPaRamp.
Š
In FSK mode, a Gaussian filter with BT = 0.3, 0.5 or 1 is used to filter the modulation stream, at the input of the sigmadelta modulator. If the Gaussian filter is enabled when the SX1231 is in Continuous mode, DCLK signal on pin 10
(DIO1/DCLK) will trigger an interrupt on the uC each time a new bit has to be transmitted. Please refer to section 5.4.2
for details.
Š
When OOK modulation is used, the PA bias voltages are ramped up and down smoothly when the PA is turned on and
off, to reduce spectral splatter.
Note
the transmitter must be restarted if the PaRamp setting is changed, in order to recalibrate the built-in filter.
3.4.6. Power Amplifiers
Three power amplifier blocks are embedded in the SX1231. The first one, herein referred to as PA0, can generate up to
+13 dBm into a 50 ohm load. PA0 shares a common front-end pin RFIO (pin 21) with the receiver LNA.
PA1 and PA2 are both connected to pin PA_BOOST (pin 23), allowing for two distinct power ranges:
Š
Š
A low power mode, where -18 dBm < Pout < 13 dBm, with PA1 enabled
A higher power mode, when PA1 and PA2 are combined, providing up to +17 dBm to a matched load.
When PA1 and PA2 are combined to deliver +17 dBm to the antenna, a specific impedance matching / harmonic filtering
design is required to ensure impedance transformation and regulatory compliance.
All PA settings are controlled by RegPaLevel, and the truth table of settings is given in Table 10.
Table 10 Power Amplifier Mode Selection Truth Table
Pa0On
Pa1On
Pa2On
1
0
0
0
1
0
1
Mode
Power Range
Pout Formula
PA0 output on pin RFIO
-18 to +13 dBm
-18 dBm + OutputPower
0
PA1 enabled on pin PA_BOOST
-18 to +13 dBm
-18 dBm + OutputPower
1
PA1 and PA2 combined on pin PA_BOOST
-14 to +17 dBm
-14 dBm + OutputPower
Other combinations
Reserved
Notes - To ensure correct operation at the highest power levels, please make sure to adjust the Over Current Protection
Limit accordingly in RegOcp.
- If PA_BOOST pin is not used (+13dBm applications and less), the pin can be left floating.
3.4.7. Over Current Protection
An over current protection block is built-in the chip. It helps preventing surge currents required when the transmitter is used
at its highest power levels, thus protecting the battery that may power the application. The current clamping value is
controlled by OcpTrim bits in RegOcp, and is calculated with the following formula:
Imax = 45 + 5 × OcpTrim ( mA )
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
3.5. Receiver Description
The SX1231 features a digital receiver with the analog to digital conversion process being performed directly following the
LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation is,
however, demodulated by a low-IF architecture. All the filtering, demodulation, gain control, synchronization and packet
handling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected. The
receiver is also capable of automatic gain calibration in order to improve precision on RSSI measurements.
3.5.1. Block Diagram
Σ/Δ
Mixers Modulators
LNA
Single to
Differential
DC
Cancellation
CORDIC
Complex
Filter
Decimator
RFIO
Channel
Filter
Module
Output
From
PA1
FSK
Demodulator
Phase
Output
RSSI
OOK
Demodulator
Processing
Rx Calibration
Reference
Bypassed
in FSK
Local
Oscillator
AFC
AGC
Figure 6. Receiver Block Diagram
The following sections give a brief description of each of the receiver blocks.
3.5.2. LNA - Single to Differential Buffer
The LNA uses a common-gate topology, which allows for a flat characteristic over the whole frequency range. It is
designed to have an input impedance of 50 Ohms or 200 Ohms (as selected with bit LnaZin in RegLna), and the parasitic
capacitance at the LNA input port is cancelled with the external RF choke. A single to differential buffer is implemented to
improve the second order linearity of the receiver.
The LNA gain, including the single-to-differential buffer, is programmable over a 48 dB dynamic range, and control is either
manual or automatic with the embedded AGC function.
Note
In the specific case where the LNA gain is manually set by the user, the receiver will not be able to properly handle
FSK signals with a modulation index smaller than 2 at an input power greater than the 1dB compression point,
tabulated in section 3.5.3.
Table 11 LNA Gain Settings
LnaGainSelect
000
001
010
011
100
101
110
111
Rev 2 - Nov 2009
LNA Gain
Any of the below, set by the AGC loop
Max gain
Max gain - 6 dB
Max gain - 12 dB
Max gain - 24 dB
Max gain - 36 dB
Max gain - 48 dB
Reserved
Page 22
Gain Setting
G1
G2
G3
G4
G5
G6
-
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ADVANCED COMMUNICATIONS & SENSING
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The current consumption of the LNA can be reduced at the expense of its performance by setting the bit LnaLowPowerOn
in RegLna. In the same way the consumption of the AD converter can be reduced by setting AdcLowPowerOn in
RegTemp1.
3.5.3. Automatic Gain Control
By default (LnaGainSelect = 000), the LNA gain is controlled by a digital AGC loop in order to obtain the optimal sensitivity/
linearity trade-off.
Regardless of the data transfer mode (Packet or Continuous), the following series of events takes place when the receiver
is enabled:
Š
The receiver stays in WAIT mode, until RssiValue exceeds RssiThreshold for two consecutive samples. Its power
consumption is the receiver power consumption.
Š
When this condition is satisfied, the receiver automatically selects the most suitable LNA gain, optimizing the sensitivity/
linearity trade-off.
Š
The programmed LNA gain, read-accessible with LnaCurrentGain in RegLna, is carried on for the whole duration of the
packet, until one of the following conditions is fulfilled:
Š
Packet mode: if AutoRxRestartOn = 0, the LNA gain will remain the same for the reception of the following packet. If
AutoRxRestartOn = 1, after the controller has emptied the FIFO the receiver will re-enter the WAIT mode described
above, after a delay of InterPacketRxDelay, allowing for the distant transmitter to ramp down, hence avoiding a false
RSSI detection.
Š
Continuous mode: upon reception of valid data, the user can decide to either leave the receiver enabled with the same
LNA gain, or to restart the procedure, by setting RestartRx bit to 1, resuming the WAIT mode of the receiver, described
above.
Notes - the first RSSI sample exceeding RssiThreshold must be confirmed by a second one sample, unless FastRx in
RegRssiConfig is set to 1.
- the AGC procedure must be performed while receiving preamble in FSK mode
- in OOK mode, the AGC will give better results if performed while receiving a constant “1” sequence
G1
AgcStep2
G2
AgcStep3
G3
Å
AgcStep4
AgcStep5
G4
G5
Higher Sensitivity
Lower Linearity
Lower Noise Figure
Ag
cT
hr
es
h5
Ag
cT
hr
es
h4
Å
Å
Ag
cT
hr
es
h3
Th
re
sh
2
Å
Ag
c
Å
AgcStep1
Ag
c
Re
fe
r
AG
C
Å
Towards
-125 dBm
Th
re
sh
1
en
c
e
The following figure illustrates the different AGC settings available in the registers RegAgcRef, RegAgcThresh1 and
RegAgcThresh2:
Pin [dBm]
G6
Lower Sensitivity
Higher Linearity
Higher Noise Figure
Figure 7. AGC Thresholds Settings
AgcStep settings can be user modified in both Automatic and Manual AgcReference modes, but the default values give
good results.
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ADVANCED COMMUNICATIONS & SENSING
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The following table summarizes the performance (typical figures) of the complete receiver:
Table 12 Receiver Performance Summary
Input Power
Pin
Gain
Setting
Pin < AgcThresh1
AgcThresh1 < Pin < AgcThresh2
AgcThresh2 < Pin < AgcThresh3
AgcThresh3 < Pin < AgcThresh4
AgcThresh4 < Pin < AgcThresh5
AgcThresh5 < Pin
G1
G2
G3
G4
G5
G6
P-1dB
[dBm]
-37
-31
-26
-14
>-6
>0
Receiver Performance (typ)
NF
IIP3
IIP2
[dB]
[dBm]
[dBm]
7
13
18
27
36
44
-18
-15
-8
-1
+13
+20
+35
+40
+48
+62
+68
+75
3.5.3.1. RssiThreshold Setting
For correct operation of the AGC, RssiThreshold in RegRssiThresh must be set to the sensitivity of the receiver. The
receiver will remain in WAIT mode until RssiThreshold is exceeded.
3.5.3.2. AGC Reference Setting
By default, the AGC reference level is automatically computed (AgcAutoReferenceOn = 1), according to:
AGC Reference [dBm] = -174 + NF + DemodSnr +10.log(2*RxBw) + AgcSnrMargin [dBm]
With:
Š NF = 7dB:
Š
Š
Š
LNA’s Noise Figure at maximum gain
DemodSnr = 8 dB: SNR needed by the demodulator
RxBw:
Single sideband channel filter bandwidth
AgcSnrMargin:
in dB, set in RegAgcThresh1
Fading margin can be adjusted through AgcSnrMargin. Sufficient margin must be taken to ensure reliable operation of the
SX1231 receiver, when the incoming signal level during the RSSI evaluation (WAIT mode) is close to AgcThresh1.
Note
When the AGC reference level is manually set by the user (AgcAutoReferenceOn=0) with AgcReferenceLevel in
RegAgcRef, the user should manually account for its optimal fading margin.
3.5.4. Quadrature Mixer - ADCs - Decimators
The mixer is inserted between output of the RF buffer stage and the input of the analog to digital converter (ADC) of the
receiver section. This block is designed to translate the spectrum of the input RF signal to base-band, and offer both high
IIP2 and IIP3 responses.
In the lower bands of operation (290 to 510 MHz), the multi-phase mixing architecture with weighted phases improves the
rejection of the LO harmonics in receiver mode, hence increasing the receiver immunity to out-of-band interferers.
The I and Q digitalization is made by two 5th order continuous-time Sigma-Delta Analog to Digital Converters (ADC). Their
gain is not constant over temperature, but the whole receiver is calibrated before reception, so that this inaccuracy has no
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
impact on the RSSI precision. The ADC output is one bit per channel. It needs to be decimated and filtered afterwards. This
ADC can also be used for temperature measurement, please refer to section 3.5.15 for more details.
The decimators decrease the sample rate of the incoming signal in order to optimize the area and power consumption of
the following receiver blocks.
3.5.5. Channel Filter
The role of the channel filter is to filter out the noise and interferers outside of the channel. Channel filtering on the SX1231
is implemented with a 16-tap Finite Impulse Response (FIR) filter, providing an outstanding Adjacent Channel Rejection
performance, even for narrowband applications.
Note
to respect oversampling rules in the decimation chain of the receiver, the Bit Rate cannot be set at a higher value
than 2 times the single-side receiver bandwidth (BitRate < 2 x RxBw)
The single-side channel filter bandwidth RxBw is controlled by the parameters RxBwMant and RxBwExp in RegRxBw:
Š
When FSK modulation is enabled:
FXOSC
RxBw = ----------------------------------------------------------------RxBwExp + 2
RxBwMant × 2
Š
When OOK modulation is enabled:
FXOSC
RxBw = ----------------------------------------------------------------RxBwExp + 3
RxBwMant × 2
The following channel filter bandwidths are accessible (oscillator is mandated at 32 MHz):
Table 13 Available RxBw Settings
Rev 2 - Nov 2009
RxBwMant
(binary/value)
RxBwExp
(decimal)
10b / 24
01b / 20
00b / 16
10b / 24
01b / 20
00b / 16
10b / 24
01b / 20
00b / 16
10b / 24
01b / 20
00b / 16
10b / 24
01b / 20
00b / 16
10b / 24
01b / 20
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
RxBw (kHz)
FSK
OOK
ModulationType=00 ModulationType=01
2.6
1.3
3.1
1.6
3.9
2.0
5.2
2.6
6.3
3.1
7.8
3.9
10.4
5.2
12.5
6.3
15.6
7.8
20.8
10.4
25.0
12.5
31.3
15.6
41.7
20.8
50.0
25.0
62.5
31.3
83.3
41.7
100.0
50.0
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00b / 16
10b / 24
01b / 20
00b / 16
10b / 24
01b / 20
00b / 16
2
1
1
1
0
0
0
DATASHEET
125.0
166.7
200.0
250.0
333.3
400.0
500.0
62.5
83.3
100.0
125.0
166.7
200.0
250.0
3.5.6. DC Cancellation
DC cancellation is required in zero-IF architecture transceivers to remove any DC offset generated through self-reception.
It is built-in the SX1231 and its adjustable cutoff frequency fc is controlled in RegRxBw:
4 × RxBw fc = ----------------------------------------DccFreq + 2
2π × 2
The default value of DccFreq cutoff frequency is typically 4% of the RxBw (channel filter BW). The cutoff frequency of the
DCC can however be increased to slightly improve the sensitivity, under wider modulation conditions. It is advised to adjust
the DCC setting while monitoring the receiver sensitivity.
3.5.7. Complex Filter - OOK
In OOK mode the SX1231 is modified to a low-IF architecture. The IF frequency is automatically set to half the single side
bandwidth of the channel filter (FIF = 0.5 x RxBw). The Local Oscillator is automatically offset by the IF in the OOK receiver.
A complex filter is implemented on the chip to attenuate the resulting image frequency by typically 30 dB.
Note
this filter is automatically bypassed when receiving FSK signals (ModulationType = 00 in RegDataModul).
3.5.8. RSSI
The RSSI block evaluates the amount of energy available within the receiver channel bandwidth. Its resolution is 0.5 dB,
and it has a wide dynamic range to accommodate both small and large signal levels that may be present. Its acquisition
time is very short, taking only 2 bit periods. The RSSI sampling must occur during the reception of preamble in FSK, and
constant “1” reception in OOK.
Note
The receiver is capable of automatic gain calibration, in order to improve the precision of its RSSI measurements.
This function injects a known RF signal at the LNA input, and calibrates the receiver gain accordingly. This
calibration is automatically performed during the PLL start-up, making it a transparent process to the end-user.
3.5.9. Cordic
The Cordic task is to extract the phase and the amplitude of the modulation vector (I+j.Q). This information, still in the
digital domain is used:
Š
Š
Phase output: used by the FSK demodulator and the AFC blocks.
Amplitude output: used by the RSSI block, for FSK demodulation, AGC and automatic gain calibration purposes.
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Q(t)
Real-time
Magnitude
Real-time Phase
I(t)
Figure 8. Cordic Extraction
3.5.10. FSK Demodulator
The FSK demodulator of the SX1231 is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is
most efficient when the modulation index of the signal is greater than 0.5 and below 10:
2 × F DEV
0.5 ≤ β = ---------------------- ≤ 10
BR
The output of the FSK demodulator can be fed to the Bit Synchronizer (described in section 3.5.12), to provide the
companion processor with a synchronous data stream in Continuous mode.
3.5.11. OOK Demodulator
The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes
are available, configured through bits OokThreshType in RegOokPeak.
The recommended mode of operation is the "Peak" threshold mode, illustrated in Figure 9:
RSSI
[dBm]
‘’Peak -6dB’’ Threshold
‘’Floor’’ threshold defined by
OokFixedThresh
Noise floor of
receiver
Time
Zoom
Zoom
Decay in dB as defined in
OokPeakThreshStep
Fixed 6dB difference
Period as defined in
OokPeakThreshDec
Figure 9. OOK Peak Demodulator Description
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In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of
an input signal, or during the reception of a logical "0", the acquired peak value is decremented by one
OokPeakThreshStep every OokPeakThreshDec period.
When the RSSI output is null for a long time (for instance after a long string of "0" received, or if no transmitter is present),
the peak threshold level will continue falling until it reaches the "Floor Threshold", programmed in OokFixedThresh.
The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in
applications in which sudden signal drops are awaited during a reception, the three parameters should be optimized
accordingly.
Note
For a correct operation of the peak threshold mode of the OOK demodulator, set 0x0c at address 0x6e.
3.5.11.1. Optimizing the Floor Threshold
OokFixedThresh determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals
(i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly.
Note that the noise floor of the receiver at the demodulator input depends on:
Š
Š
Š
Š
The noise figure of the receiver.
The gain of the receive chain from antenna to base band.
The matching - including SAW filter if any.
The bandwidth of the channel filters.
It is therefore important to note that the setting of OokFixedThresh will be application dependant. The following procedure
is recommended to optimize OokFixedThresh.
Set SX1231 in OOK Rx mode
Adjust Bit Rate, Channel filter BW
Default OokFixedThresh setting
No input signal
Continuous Mode
Monitor DIO2/DATA pin
Increment
OokFixedThresh
Glitch activity
on DATA ?
Optimization complete
Figure 10. Floor Threshold Optimization
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The new floor threshold value found during this test should be the value used for OOK reception with those receiver
settings.
3.5.11.2. Optimizing OOK Demodulator for Fast Fading Signals
A sudden drop in signal strength can cause the bit error rate to increase. For applications where the expected signal drop
can be estimated, the following OOK demodulator parameters OokPeakThreshStep and OokPeakThreshDec can be
optimized as described below for a given number of threshold decrements per bit. Refer to RegOokPeak to access those
settings.
3.5.11.3. Alternative OOK Demodulator Threshold Modes
In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors:
Š
Š
Fixed Threshold: The value is selected through OokFixedThresh
Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with
DC-free encoded data.
3.5.12. Bit Synchronizer
The Bit Synchronizer is a block that provides a clean and synchronized digital output, free of glitches. Its output is made
available on pin DIO1/DCLK in Continuous mode and can be disabled through register settings. However, for optimum
receiver performance its use when running Continuous mode is strongly advised.
The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in
RegBitrate.
Raw demodulator
output
(FSK or OOK)
DATA
BitSync Output
To pin DATA and
DCLK in continuous
mode
DCLK
Figure 11. Bit Synchronizer Description
To ensure correct operation of the Bit Synchronizer, the following conditions have to be satisfied:
Š
Š
A preamble (0x55 or 0xAA) of 12 bits is required for synchronization (from the RxReady interrupt)
The subsequent payload bit stream must have at least one transition form '0' to '1' or '1' to '0 every 16 bits during data
transmission
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Š
DATASHEET
The bit rate matching between the transmitter and the receiver must be better than 6.5 %.
Notes - If the Bit Rates of transmitter and receiver are known to be the same, the SX1231 will be able to receive an infinite
unbalanced sequence (all “0s” or all ”1s”) with no restriction.
- If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the
BitSync can withstand can be estimated as follows:
- This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily
achievable (crystal tolerance is in the range of 50 to 100 ppm).
3.5.13. Frequency Error Indicator
This function provides information about the frequency error of the local oscillator (LO) compared with the carrier frequency
of a modulated signal at the input of the receiver. When the FEI block is launched, the frequency error is measured and the
signed result is loaded in FeiValue in RegFei, in 2’s complement format. The time required for an FEI evaluation is 4 times
the bit period.
To ensure a proper behavior of the FEI:
Š
Š
The operation must be done during the reception of preamble
The sum of the frequency offset and the 20 dB signal bandwidth must be lower than the base band filter bandwidth
The 20 dB bandwidth of the signal can be evaluated as follows (double-side bandwidth):
BR
BW 20 dB = 2 × ⎛⎝ F DEV + -------⎞⎠
2
The frequency error, in Hz, can be calculated with the following formula:
FEI = F STEP × FeiValue
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SX1231 in Rx mode
Preamble-modulated input signal
Signal level > Sensitivity
Set FeiStart
=1
FeiDone
=1
No
Yes
Read
FeiValue
Figure 12. FEI Process
3.5.14. Automatic Frequency Correction
The AFC is based on the FEI block, and therefore the same input signal and receiver setting conditions apply. When the
AFC procedure is done, AfcValue is directly subtracted to the register that defines the frequency of operation of the chip,
FRF. The AFC can be launched:
Š
Š
Each time the receiver is enabled, if AfcAutoOn = 1
Upon user request, by setting bit AfcStart in RegAfcFei, if AfcAutoOn = 0
When the AFC is automatically triggered (AfcAutoOn = 1), the user has the option to:
Š
Š
Clear the former AFC correction value, if AfcAutoClearOn = 1
Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the LO keeps
on drifting in the “same direction”. Ageing compensation is a good example.
The SX1231 offers an alternate receiver bandwidth setting during the AFC phase, to accommodate large LO drifts. If the
user considers that the received signal may be out of the receiver bandwidth, a higher channel filter bandwidth can be
programmed in RegAfcBw, at the expense of the receiver noise floor, which will impact upon sensitivity.
3.5.15. Temperature Sensor
When temperature is measured, the receiver ADC is used to digitize the sensor response. Most receiver blocks are
disabled, and temperature measurement can only be triggered in Standby or Frequency Synthesizer modes.
The response of the temperature sensor is -1°C / Lsb. A CMOS temperature sensor is not accurate by nature, therefore it
should be calibrated at ambient temperature for precise temperature readings.
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TempValue
-1°C/Lsb
TempValue(t)
TempValue(t)-1
Returns 150d (typ.)
Needs calibration
-40°C
t t+1
Ambient
+85°C
Figure 13. Temperature Sensor Response
3.5.16. Timeout Function
The SX1231 includes a Timeout function, which allows it to automatically shut-down the receiver after a receive sequence
and therefore save energy.
Š
Timeout interrupt is generated TimeoutRxStart x 8 x Tbit after switching to RX mode if RssiThreshold flag does not raise
within this time frame
Š
Timeout interrupt is generated TimeoutRssiThresh x 8 x Tbit after RssiThreshold flag has been raised.
This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power
mode.
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4. Operating Modes
4.1. Basic Modes
The circuit can be set in 5 different basic modes which are described in Table 14.
By default, when switching from a mode to another one, the sub-blocks are woken up according to a pre-defined and
optimized sequence. Alternatively, these operating modes can be selected directly by disabling the automatic sequencer
(SequencerOff in RegOpMode = 1).
Table 14 Basic Transceiver Modes
ListenOn
in RegOpMode
0
0
0
0
0
1
Mode
in RegOpMode
000
001
010
011
100
x
Selected mode
Enabled blocks
Sleep Mode
Stand-by Mode
FS Mode
Transmit Mode
Receive Mode
Listen Mode
None
Top regulator and crystal oscillator
Frequency synthesizer
Frequency synthesizer and transmitter
Frequency synthesizer and receiver
See Listen Mode, section 4.3
4.2. Automatic Sequencer and Wake-Up Times
By default, when switching from one operating mode to another, the circuit takes care of the sequence of events in such a
way that the transition timing is optimized. For example, when switching from Sleep mode to Transmit mode, the SX1231
goes first to Standby mode (XO started), then to frequency synthesizer mode, and finally, when the PLL has locked, to
transmit mode. Entering transmit mode is also made according to a predefined sequence starting with the wake-up of the
PA regulator before applying a ramp-up on the PA and generating the DCLK clock.
Š
The crystal oscillator wake-up time, TS_OSC, is directly related to the time for the crystal oscillator to reach its steady
state. It depends notably on the crystal characteristics.
Š
The frequency synthesizer wake-up time, TS_FS, is directly related to the time needed by the PLL to reach its steady
state. The signal PLL_LOCK, provided on an external pin, gives an indication of the lock status. It goes high when the
PLL reaches its locking range.
Four specific cases can be highlighted:
Š
Š
Š
Š
Transmitter Wake Up time from Sleep mode
= TS_OSC + TS_FS + TS_TR
Receiver Wake Up time from Sleep mode
= TS_OSC + TS_FS + TS_RE
Receiver Wake Up time from Sleep mode, AGC enabled
= TS_OSC + TS_FS + TS_RE_AGC
Receiver Wake Up time from Sleep mode, AGC and AFC enabled
= TS_OSC + TS_FS + TS_RE_AGC&AFC
These timings are details in sections 4.2.1 and 4.2.3.
In applications where the target average power consumption, or the target startup time, do not require setting the SX1231
in the lowest power modes (Sleep or Standby), the respective timings TS_OSC and TS_FS in the former equations can be
omited.
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4.2.1. Transmitter Startup Time
The transmitter wake-up time, TS_TR, is given by the sequence controlled by the digital part. It is a pure digital delay which
depends on the bit rate and the ramp-up time. In FSK mode, this time can be derived from the following equation.
1
TS _ TR = 5μs + 1.25 × PaRamp + × Tbit
2
,
where PaRamp is the ramp-up time programmed in RegPaRamp and Tbit is the bit time.
In OOK mode, this equation can be simplified to the following:
1
TS _ TR = 5μs + × Tbit
2
Tx startup request
(sequencer or user)
XO Started and PLL is locked
TS_TR
Analog
group delay
0.5 x Tbit
1.25 x PaRamp
(only in FSK
mode)
Transmission of Packet
5 us
ModeReady
TxReady
Figure 14. Tx Startup, FSK and OOK
4.2.2. Tx Start Procedure
As described in the former section, ModeReady and TxReady interrupts warn the uC that the transmitter is ready to
transmit data
Š
In Continuous mode, the preamble bits preceding the payload can be applied on the DIO2/DATA pin immediately after
any of these interrupts have fired. The DCLK signal, activated on pin DIO1/DCLK can also be used to start toggling the
DATA pin, as described on Figure 27.
Š
In Packet mode, the SX1231 will automatically modulate the RF signal with preamble bytes as soon as TxReady or
ModeReady happen. The actual packet transmission (starting with the number of preambles specified in PreambleSize)
will start when the TxStartCondition is fulfilled.
4.2.3. Receiver Startup Time
It is highly recommended to use the built-in sequencer of the SX1231, to optimize the delays when setting the chip in
receive mode. It guarantees the shortest startup times, hence the lowest possible energy usage, for battery operated
systems.
The startup times of the receiver can be calculated from the following:
Rev 2 - Nov 2009
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Rx startup request
(sequencer or user)
XO Started and PLL is locked
DATASHEET
TS_RE
Analog FE’s
group delay
Channel Filter’s
group delay
DC Cutoff’s
group delay
RSSI
sampling
RSSI
sampling
Tana
Tcf
Tdcc
Trssi
Trssi
Reception of Packet
ModeReady
RxReady
Figure 15. Rx Startup - No AGC, no AFC
Rx startup request
(sequencer or user)
XO Started and PLL is locked
The LNA gain is adjusted by
the AGC, according to the
RSSI result
TS_RE_AGC
Analog FE’s
group delay
Channel Filter’s
group delay
DC Cutoff’s
group delay
RSSI
sampling
RSSI
sampling
Channel Filter’s
group delay
DC Cutoff’s
group delay
RSSI
sampling
Tana
Tcf
Tdcc
Trssi
Trssi
Tcf
Tdcc
Trssi
Reception of Packet
ModeReady
RxReady
Figure 16. Rx Startup - AGC, no AFC
Rx startup request
(sequencer or user)
XO Started and
PLL is locked
The LNA gain is adjusted by
the AGC, according to the
RSSI result
TS_RE_AGC&AFC
Carrier Frequency is adjusted
by the AFC
Analog FE’s
group delay
Channel Filter’s
group delay
DC Cutoff’s
group delay
RSSI
sampling
RSSI
sampling
Channel Filter’s
group delay
DC Cutoff’s
group delay
RSSI
sampling
AFC
PLL
lock
Channel Filter’s
group delay
DC Cutoff’s
group delay
Tana
Tcf
Tdcc
Trssi
Trssi
Tcf
Tdcc
Trssi
Tafc
Tpllafc
Tcf
Tdcc
Reception of Packet
ModeReady
RxReady
Figure 17. Rx Startup - AGC and AFC
The different timings shown above are as follows:
Š
Š
Š
Š
Š
Š
Š
Group delay of the analog front end:
Tana = 10 us
Channel filter’s group delay in FSK mode:
Tcf = 21 / (4.RxBw)
Channel filter’s group delay in OOK mode:
Tcf = 34 / (4.RxBw)
DC Cutoff’s group delay:
Tdcc = max(8 , 2^(round(log2(8.RxBw.Tbit)+1)) / (4.RxBw)
PLL lock time after AFC adjustment:
Tpllafc = 5 / PLLBW (PLLBW = 300 kHz)
AFC sample time:
Tafc = 4 x Tbit
RSSI sample time:
Trssi = 2 x int(4.RxBw.Tbit)/(4.RxBw)
Rev 2 - Nov 2009
Page 35
(also denoted TS_AFC in the general specification)
(aka TS_RSSI)
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ADVANCED COMMUNICATIONS & SENSING
Note
DATASHEET
For time-critical applications, a single RSSI evaluation can be done prior to the reception (AGC disabled), or prior
to the AGC procedure. This can be achieved by setting bit FastRx in RegRssiConfig to 1, and saves the equivalent
of 2 x Tbit
4.2.4. Rx Start Procedure
As described in the former sections, the RxReady interrupt warns the uC that the receiver is ready.
Š
In Continuous mode with Bit Synchronizer, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of
received preamble (see section 3.5.12 for details), before the reception of correct Data, or Sync Word (if enabled) can
occur.
Š
In Continuous mode without Bit Synchronizer, valid data will be available on DIO2/DATA right after the RxReady
interrupt.
Š
In Packet mode, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble (see
section 3.5.12 for details), before the reception of correct Data, or Sync Word (if enabled) can occur.
4.2.5. Optimized Frequency Hopping Sequences
In a frequency hopping-like application, it is required to turn off the transmitter when hopping from one channel to another,
to avoid spectral splatter and obtain the best spectral purity.
Š
Transmitter hop from Ch A to Ch B: it is advised to step through the Rx mode:
(0) SX1231 is in Tx mode in Ch A
(1) Program the SX1231 in Rx mode
(2) Change the carrier frequency in the RegFrf registers
(3) Wait for TS_HOP (timing corresponding the frequency offset, the PllLock flag can also be used)
(4) Turn the transceiver back to Tx mode
(5) Respect the Tx start procedure, described in section 4.2.2
Š
Receiver hop from Ch A to Ch B:
(0) SX1231 is in Rx mode in Ch A
(1) Program the SX1231 in FS mode
(2) Change the carrier frequency in the RegFrf registers
(3) Wait for TS_HOP (timing corresponding the frequency offset, the PllLock flag can also be used)
(4) Turn the transceiver back to Rx mode
(5) Respect the Rx start procedure, described in section 4.2.4
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4.3. Listen mode
The circuit can be set to Listen mode, by setting ListenOn in RegOpMode to 1. In this mode, SX1231 spends most of the
time in Idle mode, during which only the RC oscillator runs. Periodically the receiver is woken up and listens for an RF
signal. If a wanted signal is detected, the receiver is kept on and the data is demodulated.
Otherwise, if a wanted signal hasn't been detected after a pre-defined period of time, the receiver is disabled until the next
time period.
This periodical Rx wake-up requirement is very common in low power applications. On SX1231 it is handled locally by the
Listen mode block without using uC resources or energy.
The simplified timing diagram of this procedure is illustrated in Figure 18.
tListenIdle
Rx
Idle
Rx
tListenRx
time
tListenRx
Figure 18. Listen Mode Sequence (no wanted signal is received)
The duration of the idle phase is given by tListenIdle. The time during which the receiver is on and waits for a signal is given
by tListenRx. tListenRx includes the wake-up time of the receiver, described in section 4.2.3. This duration can be
programmed in the configuration registers via the serial interface.
Both time periods tListenRx and tListenIdle (denoted tListenX in the following text) are fixed by two parameters from the
configuration register and are calculated as follows:
t ListenX = ListenCoefX ⋅ ListenResol
where ListenResol gives the Rx/Idle common resolution and is programmable on three values (1, 2 and 3), whereas
ListenCoefX is an integer between 1 and 255. All parameters are located in RegListen registers.
The timing ranges are tabulated in Table 15 below.
Table 15 Range of Durations in Listen Mode
Rev 2 - Nov 2009
ListenResol
Min duration
( ListenCoef = 1 )
Max duration
( ListenCoef = 255 )
0101
1010
1111
64 us
4.1 ms
0.26 s
16 ms
1.04 s
67 s
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Notes - the accuracy of the typical timings given in Table 15 will depend in the RC oscillator calibration
- RC oscillator calibration is required, and must be performed at power up. See section 7.3 for details
- the default ListenResol setting 1001 is reserved
The criteria taken for detecting a wanted signal and hence deciding to maintain the receiver on is defined by ListenCriteria
in RegListen1.
Table 16 Signal Acceptance Criteria in Listen Mode
ListenCriteria
Input Signal Power
>= RssiThreshold
SyncAddressMatch
0
1
Required
Required
Not Required
Required
The action taken after detection of a packet, is defined by ListenEnd in RegListen3, as described in the table below.
Table 17 End of Listen Cycle Actions
ListenEnd
00
01
10
Rev 2 - Nov 2009
Description
Chip stays in Rx mode. Listen mode stops and must be disabled.
Chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. It then goes to the
mode defined by Mode. Listen mode stops and must be disabled.
Chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then
resumes in Idle state. FIFO content is lost at next Rx wakeup.
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Upon detection of a valid packet, the sequencing is altered, as shown below:
PayloadReady
ListenCriteria
passed
Idle
Rx
Idle
Rx
Idle
Rx
ListenEnd = 00
Listen Mode
Mode
ListenEnd = 01
Listen Mode
Idle
Rx
ListenEnd = 10
Listen Mode
Figure 19. Listen Mode Sequence (wanted signal is received)
For all three ListenEnd settings (i.e. even for 00 and 01) disabling Listen mode can be done anytime by writing all together
in a single SPI write command (same register) :
Š
Š
Š
ListenOn to 0
ListenAbort to 1
Mode to the wanted operation mode
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4.4. AutoModes
Automatic modes of packet handler can be enabled by configuring the related parameters in RegAutoModes.
The intermediate mode of the chip is called IntermediateMode and the enter and exit conditions to/from this intermediate
mode can be configured through the parameters EnterCondition & ExitCondition.
The enter and exit conditions cannot be used independently of each other i.e. both should be enabled at the same time.
The initial and the final state is the one configured in Mode in RegOpMode. The initial & final states can be different by
configuring the modes register while the chip is in intermediate mode. The pictorial description of the auto modes is shown
below.
Intermediate State
defined by IntermediateMode
ExitCondition
EnterCondition
Initial state defined
By Mode in RegOpMode
Final state defined
By Mode in RegOpMode
Figure 20. Auto Modes of Packet Handler
Some typical examples of AutoModes usage are described below :
Š
Automatic transmission (AutoTx) : Mode = Sleep, IntermediateMode = Tx, EnterCondition = FifoLevel, ExitCondition =
PacketSent
Š
Automatic reception (AutoRx) : Mode = Rx, IntermediateMode = Sleep, EnterCondition = CrcOk, ExitCondition = falling
edge of FifoNotEmpty
Š
Automatic reception of acknowledge (AutoRxAck): Mode = Tx, IntermediateMode = Rx, EnterCondition = PacketSent,
ExitCondition = CrcOk
Š
...
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5. Data Processing
5.1. Overview
5.1.1. Block Diagram
Figure below illustrates the SX1231 data processing circuit. Its role is to interface the data to/from the modulator/
demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers.
The circuit contains several control blocks which are described in the following paragraphs.
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Tx/Rx
CONTROL
Data
Rx
SYNC
RECOG.
PACKET
HANDLER
FIFO
(+SR)
SPI
NSS
SCK
MOSI
MISO
Tx
Potential datapaths (data operation mode dependant)
Figure 21. SX1231 Data Processing Conceptual View
The SX1231 implements several data operation modes, each with their own data path through the data processing section.
Depending on the data operation mode selected, some control blocks are active whilst others remain disabled.
5.1.2. Data Operation Modes
The SX1231 has two different data operation modes selectable by the user:
Š
Continuous mode: each bit transmitted or received is accessed in real time at the DIO2/DATA pin. This mode may be
used if adequate external signal processing is available.
Š
Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically
built with preamble, Sync word, and optional AES, CRC, and DC-free encoding schemes The reverse operation is
performed in reception. The uC processing overhead is hence significantly reduced compared to Continuous mode.
Depending on the optional features activated (CRC, AES, etc) the maximum payload length is limited to FIFO size, 255
bytes or unlimited.
Each of these data operation modes is described fully in the following sections.
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5.2. Control Block Description
5.2.1. SPI Interface
The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL
= 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented.
Three access modes to the registers are provided:
Š
SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and
a read byte is received for the read access. The NSS pin goes low at the begin of the frame and goes high after the data
byte.
Š
BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally
between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the
beginning of the frame and stay low between each byte. It goes high only after the last byte transfer.
Š
FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the
FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data
byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the
last byte transfer.
Figure below shows a typical SPI single access to a register.
Figure 22. SPI Timing Diagram (single access)
MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the
rising edge of SCK. MISO is generated by the slave on the falling edge of SCK.
A transfer always starts by the NSS pin going low. MISO is high impedance when NSS is high.
The first byte is the address byte. It is made of:
Š
Š
wnr bit, which is 1 for write access and 0 for read access
7 bits of address, MSB first
The second byte is a data byte, either sent on MOSI by the master in case of a write access, or received by the master on
MISO in case of read access. The data byte is transmitted MSB first.
Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without rising NSS and
re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read at the
FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented at each new
byte received.
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The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is
actually a special case of FIFO / BURST mode with only 1 data byte transferred.
During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written
register before the write operation.
5.2.2. FIFO
5.2.2.1. Overview and Shift Register (SR)
In packet mode of operation, both data to be transmitted and that has been received are stored in a configurable FIFO
(First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management.
The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A
shift register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs
them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data
from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.
FIFO
byte1
byte0
8
Data Tx/Rx
SR (8bits)
1
MSB
LSB
Figure 23. FIFO and Shift Register (SR)
Note
When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from
all modes except from Tx)
5.2.2.2. Size
The FIFO size is fixed to 66 bytes.
5.2.2.3. Interrupt Sources and Flags
Š
FifoNotEmpty: FifoNotEmpty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note
that when retrieving data from the FIFO, FifoNotEmpty is updated on NSS falling edge, i.e. when FifoNotEmpty is
updated to low state the currently started read operation must be completed. In other words, FifoNotEmpty state must
be checked after each read operation for a decision on the next one (FifoNotEmpty = 1: more byte(s) to read;
FifoNotEmpty = 0: no more byte to read).
Š
Š
FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
Š
Š
FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the user (in Tx or Standby modes) or the SR (in
Rx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will
also be cleared.
PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.
FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below.
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FifoLevel
1
0
B
B+1
# of bytes in FIFO
Figure 24. FifoLevel IRQ Source Behavior
Note
- FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be
dynamically updated by only changing the FifoThreshold parameter
- FifoLevel interrupt is valid as long as FifoFull does not occur. An empty FIFO will restore its normal operation
5.2.2.4. FIFO Clearing
Table below summarizes the status of the FIFO when switching between different modes
Table 18 Status of FIFO when Switching Between Different Modes of the Chip
From
Stdby
Sleep
Stdby/Sleep
Stdby/Sleep
Rx
Rx
Tx
To
Sleep
Stdby
Tx
Rx
Tx
Stdby/Sleep
Any
FIFO status
Not cleared
Not cleared
Not cleared
Cleared
Cleared
Not cleared
Cleared
Comments
To allow the user to write the FIFO in Stdby/Sleep before Tx
To allow the user to read FIFO in Stdby/Sleep mode after Rx
5.2.3. Sync Word Recognition
5.2.3.1. Overview
Sync word recognition (also called Pattern recognition) is activated by setting SyncOn in RegSyncConfig. The bit
synchronizer must also be activated in continuous mode (automatically done in Packet mode) .
The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync
word and sets SyncAddressMatch when a match is detected. This is illustrated in Figure 25 below.
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Rx DATA
Bit N-x =
(NRZ)
Sync_value[x]
DATASHEET
Bit N-1 =
Bit N =
Sync_value[1] Sync_value[0]
DCLK
SyncAddressMatch
Figure 25. Sync Word Recognition
During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and
the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync
word.
When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be
processed accordingly.
SyncAddressMatch is cleared when leaving Rx or FIFO is emptied.
5.2.3.2. Configuration
Š
Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode this
field is also used for Sync word generation in Tx mode.
Š
Š
Error tolerance: The number of errors tolerated in the Sync word recognition can be set from 0 to 7 bits to via SyncTol.
Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync word
generation in Tx mode.
Note
SyncValue choices containing 0x00 bytes are not allowed
5.2.4. Packet Handler
The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5.
5.2.5. Control
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration
registers.
5.3. Digital IO Pins Mapping
Six general purpose IO pins are available on the SX1231, and their configuration in Continuous or Packet mode is
controlled through RegDioMapping1 and RegDioMapping2.
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5.3.1. DIO Pins Mapping in Continuous Mode
Table 19 DIO Mapping, Continuous Mode
Mode
Sleep
Stdby
FS
Rx
Tx
Diox
Mapping
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
LowBat
ModeReady
ClkOut
LowBat
ModeReady
ClkOut
LowBat
ModeReady
ClkOut
Rssi
LowBat
ModeReady
ClkOut
ClkOut
LowBat
ModeReady
LowBat
LowBat
LowBat
PllLock
Timeout
RxReady
SyncAddress
PllLock
TxReady
TxReady
TxReady
PllLock
AutoMode
AutoMode
AutoMode
Rssi
RxReady
AutoMode
Timeout
LowBat
LowBat
AutoMode
TxReady
Data
Data
Data
Data
Data
Data
Data
Data
PllLock
PllLock
PllLock
PllLock
Dclk
RxReady
LowBat
SyncAddress
Dclk
TxReady
LowBat
LowBat
LowBat
ModeReady
LowBat
ModeReady
PllLock
LowBat
ModeReady
SyncAddress
Timeout
Rssi
PllLock
PllLock
PllLock
PllLock
PllLock
5.3.2. DIO Pins Mapping in Packet Mode
Table 20 DIO Mapping, Packet Mode
Mode
Sleep
Stdby
FS
Rx
Tx
Note
Diox
Mapping
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
LowBat
ModeReady
ClkOut
LowBat
ModeReady
ClkOut
LowBat
ModeReady
ClkOut
Data
LowBat
ModeReady
ClkOut
Data
LowBat
ModeReady
LowBat
ModeReady
LowBat
ModeReady
LowBat
PllLock
Timeout
Rssi
RxReady
PllLock
ModeReady
TxReady
LowBat
PllLock
FifoFull
FifoFull
FifoFull
FifoFull
Rssi
SyncAddress
PllLock
FifoFull
TxReady
LowBat
PllLock
FifoNotEmpty
AutoMode
FifoNotEmpty
AutoMode
FifoNotEmpty
AutoMode
FifoNotEmpty
Data
LowBat
AutoMode
FifoNotEmpty
Data
LowBat
AutoMode
FifoLevel
FifoFull
FifoNotEmpty
PllLock
FifoLevel
FifoFull
FifoNotEmpty
Timeout
FifoLevel
FifoFull
FifoNotEmpty
PllLock
FifoLevel
FifoFull
FifoNotEmpty
Timeout
FifoLevel
FifoFull
FifoNotEmpty
PllLock
LowBat
ModeReady
LowBat
ModeReady
PllLock
LowBat
ModeReady
CrcOk
PayloadReady
SyncAddress
Rssi
PacketSent
TxReady
LowBat
PllLock
Received Data is only shown on the Data signal between RxReady and PayloadReady’s rising edges
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5.4. Continuous Mode
5.4.1. General Description
As illustrated in Figure 26, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on
the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive.
DIO0
DIO1/DCLK
DIO2/DATA
DIO3
DIO4
DIO5
Tx/Rx
CONTROL
Data
Rx
SYNC
RECOG.
SPI
NSS
SCK
MOSI
MISO
Figure 26. Continuous Mode Conceptual View
5.4.2. Tx Processing
In Tx mode, a synchronous data clock for an external uC is provided on DIO1/DCLK pin. Clock timing with respect to the
data is illustrated in Figure 27. DATA is internally sampled on the rising edge of DCLK so the uC can change logic state
anytime outside the grayed out setup/hold zone.
T_DATA
T_DATA
DATA
(NRZ)
DCLK
Figure 27. Tx Processing in Continuous Mode
Note
the use of DCLK is required when the modulation shaping is enabled (see section 3.4.5).
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5.4.3. Rx Processing
If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal
is provided.
Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on
DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as
illustrated below.
DATA (NRZ)
DCLK
Figure 28. Rx Processing in Continuous Mode
Note
in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the
DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode).
5.5. Packet Mode
5.5.1. General Description
In Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by the uC but stored in the FIFO and
accessed via the SPI interface.
In addition, the SX1231 packet handler performs several packet oriented tasks such as Preamble and Sync word
generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, AES
encryption/decryption, etc. This simplifies software and reduces uC overhead by performing these repetitive tasks within
the RF chip itself.
Another important feature is ability to fill and empty the FIFO in Sleep/Stdby mode, ensuring optimum power consumption
and adding more flexibility for the software.
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DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
CONTROL
Data
Rx
SYNC
RECOG.
PACKET
HANDLER
FIFO
(+SR)
SPI
NSS
SCK
MOSI
MISO
Tx
Figure 29. Packet Mode Conceptual View
Note
The Bit Synchronizer is automatically enabled in Packet mode.
5.5.2. Packet Format
5.5.2.1. Fixed Length Packet Format
Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater
than 0.
In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF
overhead (no length byte field is required). All nodes, whether Tx only, Rx only, or Tx/Rx should be programmed with the
same packet length value.
The length of the payload is limited to 255 bytes if AES is not enabled else the message is limited to 64 bytes (i.e. max 65
bytes payload if Address byte is enabled).
The length programmed in PayloadLength relates only to the payload which includes the message and the optional
address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte.
An illustration of a fixed length packet is shown below. It contains the following fields:
Š
Š
Š
Š
Š
Preamble (1010...)
Sync word (Network ID)
Optional Address byte (Node ID)
Message data
Optional 2-bytes CRC checksum
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DC free Data encoding
CRC checksum calculation
AES Enc/Dec
Preamble
0 to 65535
bytes
Sync Word
0 to 8 bytes
Address
byte
Message
Up to 255 bytes
CRC
2-bytes
Payload
(min 1 byte)
Fields added by the packet handler in Tx and processed and removed in Rx
Optional User provided fields which are part of the payload
Message part of the payload
Figure 30. Fixed Length Packet Format
5.5.2.2. Variable Length Packet Format
Variable length packet format is selected when bit PacketFormat is set to 1.
This mode is useful in applications where the length of the packet is not known in advance and can vary over time. It is then
necessary for the transmitter to send the length information together with each packet in order for the receiver to operate
properly.
In this mode the length of the payload, indicated by the length byte, is given by the first byte of the FIFO and is limited to
255 bytes if AES is not enabled else the message is limited to 64 bytes (i.e. max 66 bytes payload if Address byte is
enabled). Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2
bytes, i.e. length + address or message byte.
An illustration of a variable length packet is shown below. It contains the following fields:
Š
Š
Š
Š
Š
Š
Preamble (1010...)
Sync word (Network ID)
Length byte
Optional Address byte (Node ID)
Message data
Optional 2-bytes CRC checksum
DC free Data encoding
CRC checksum calculation
AES Enc/Dec
Preamble
0 to 65535
bytes
Sync Word
0 to 8 bytes
Length
byte
Address
byte
Message
Up to 255 bytes
CRC
2-bytes
Payload
(min 2 bytes)
Fields added by the packet handler in Tx and processed and removed in Rx
Optional User provided fields which are part of the payload
Message part of the payload
Figure 31. Variable Length Packet Format
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5.5.2.3. Unlimited Length Packet Format
Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0.
The user can then transmit and receive packet of arbitrary length and PayloadLength register is not used in Tx/Rx modes
for counting the length of the bytes transmitted/received. This mode is a replacement for the legacy buffered mode in
SX1211/SX1212 transceivers.
In Tx the data is transmitted depending on the TxStartCondition bit. On the Rx side the data processing features like
Address filtering, Manchester encoding and data whitening are not available if the sync pattern length is set to zero
(SyncOn = 0). The filling of the FIFO in this case can be controlled by the bit FifoFillCondition. The CRC detection in Rx is
also not supported in this mode of the packet handler, however CRC generation in Tx is operational. The interrupts like
CrcOk & PayloadReady are not available either.
An unlimited length packet shown in is made up of the following fields:
Š
Š
Š
Š
Š
Preamble (1010...).
Sync word (Network ID).
Optional Address byte (Node ID).
Message data
Optional 2-bytes CRC checksum (Tx only)
DC free Data encoding
Preamble
0 to 65535
bytes
Sync Word
0 to 8 bytes
Address
byte
Message
unlimited length
Payload
Fields added by the packet handler in Tx and processed and removed in Rx
Message part of the payload
Optional User provided fields which are part of the payload
Figure 32. Unlimited Length Packet Format
5.5.3. Tx Processing (without AES)
In Tx mode the packet handler dynamically builds the packet by performing the following operations on the payload
available in the FIFO:
Š
Š
Š
Add a programmable number of preamble bytes
Š
Optional DC-free encoding of the data (Manchester or whitening)
Add a programmable Sync word
Optionally calculating CRC over complete payload field (optional length byte + optional address byte + message) and
appending the 2 bytes checksum.
Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO.
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The transmission of packet data is initiated by the Packet Handler only if the chip is in Tx mode and the transmission
condition defined by TxStartCondition is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a
preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or
one until the condition is met to transmit the packet data.
The transmission condition itself is defined as:
Š
if TxStartCondition = 1, the packet handler waits until the first byte is written into the FIFO, then it starts sending the
preamble followed by the sync word and user payload
Š
If TxStartCondition = 0, the packet handler waits until the number of bytes written in the FIFO is equal to the number
defined in RegFifoThresh + 1
Š
If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then the transmission of
packet starts immediately on enabling Tx
5.5.4. Rx Processing (without AES)
In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations:
Š
Š
Š
Š
Š
Receiving the preamble and stripping it off
Detecting the Sync word and stripping it off
Optional DC-free decoding of data
Optionally checking the address byte
Optionally checking CRC and reflecting the result on CrcOk.
Only the payload (including optional address and length fields) is made available in the FIFO.
When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed
length packet format is enabled then the number of bytes received as the payload is given by the PayloadLength
parameter.
In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The
internal length counter is initialized to this received length. The PayloadLength register is set to a value which is greater
than the maximum expected length of the received packet. If the received length is greater than the maximum length stored
in PayloadLength register the packet is discarded otherwise the complete packet is received.
If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed
length is the address byte. If the address matches to the one in the NodeAddress field, reception of the data continues
otherwise it's stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the
CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the
FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode.
If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by
setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC
fails.
5.5.5. AES
AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The system proposed
can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which
retains its value in Sleep mode.
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As shown in Figure 30 and Figure 31 above the message part of the Packet can be encrypted and decrypted with the
cipher 128- cipher key stored in the configuration registers.
5.5.5.1. Tx Processing
1. User enters the data to be transmitted in FIFO in Stdby/Sleep mode and gives the transmit command.
2. On Tx command the Packet handler state machine takes over the control and If encryption is enabled then the
message inside the FIFO is read in blocks of 16 bytes (padded with 0s if needed), encrypted and stored back to FIFO.
All this processing is done in Tx mode before enabling the packet handling state machine. Only the Message part of the
packet is encrypted and preamble, sync word, length byte, address byte and CRC are not encrypted.
3. Once the encryption is done the Packet handling state machine is enabled to transmit the data.
5.5.5.2. Rx Processing
1. The data received is stored in the FIFO, The address, CRC interrupts are generated as usual because these
parameters were not encrypted.
2. Once the complete packet has been received. The data is read from the FIFO, decrypted and written back to FIFO.
The PayloadReady interrupt is issued once the decrypted data is ready in the FIFO for reading via the SPI interface.
The AES encryption/decryption cannot be used on the fly i.e. while transmitting and receiving data. Thus when AES
encryption/decryption is enabled, the FIFO acts as a simple buffer. This buffer is filled before initiating any transmission.
The data in the buffer is then encrypted before the transmission can begin. On the receive side the decryption is initiated
only once the complete packet has been received in the buffer.
The encryption/decryption process takes approximately 7.0 us per 16-byte block. Thus for a maximum of 4 blocks (i.e. 64
bytes) it can take up to 28 us for completing the cryptographic operations.
The receive side sees the AES decryption time as a sequential delay before the PayloadReady interrupt is available.
The Tx side sees the AES encryption time as a sequential delay in the startup of the Tx chain, thus the startup time of the
Tx will increase according to the length of data.
In Fixed length mode the Message part of the payload that can be encrypted/decrypted can be 64 bytes long. If the
address filtering is enabled , the length of the payload should be at max 65 bytes in this case.
In Variable length mode the Max message size that can be encrypted/decrypted is also 64 bytes when address filtering is
disabled, else it is 48 bytes. Thus, including length byte, the length of the payload is max 65 or 50 bytes (the latter when
address filtering is enabled).
If the address filtering is expected then AddressFiltering must be enabled on the transmitter side as well to prevent address
byte to be encrypted.
Crc check being performed on encrypted data, CrcOk interrupt will occur "decryption time" before PayloadReady interrupt.
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5.5.6. Packet Filtering
SX1231's packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made
available to the uC, reducing significantly system power consumption and software complexity.
5.5.6.1. Sync Word Based
Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As
previously described, the Sync word recognition block is configured (size, error tolerance, value) in RegSyncValue
registers. This information is used, both for appending Sync word in Tx, and filtering packets in Rx.
Every received packet which does not start with this locally configured Sync word is automatically discarded and no
interrupt is generated.
When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted.
5.5.6.2. Address Based
Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering, above Sync word (i.e. Sync
must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word)
and each node has its own ID (address).
Two address based filtering options are available:
Š
AddressFiltering = 01: Received address field is compared with internal register NodeAddress. If they match then the
packet is accepted and processed, otherwise it is discarded.
Š
AddressFiltering = 10: Received address field is compared with internal registers NodeAddress and BroadcastAddress.
If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with
a constant is useful for implementing broadcast in a multi-node networks
Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in
the FIFO. In addition, NodeAddress and AddressFiltering only apply to Rx. On Tx side, if address filtering is expected, the
address byte should simply be put into the FIFO like any other byte of the payload.
As address filtering requires a Sync word match, both features share the same interrupt flag SyncAddressMatch.
5.5.6.3. Length Based
In variable length Packet mode, PayloadLength must be programmed with the maximum payload length permitted. If
received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded.
Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the
FIFO.
To disable this function the user should set the value of the PayloadLength to 255.
5.5.6.4. CRC Based
The CRC check is enabled by setting bit CrcOn in RegPacketConfig1. It is used for checking the integrity of the message.
Rev 2 - Nov 2009
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Š
On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the
message
Š
On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes received.
The result of the comparison is stored in bit CrcOk.
By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function
can be disabled via CrcAutoClearOff bit and in this case, even if CRC fails, the FIFO is not cleared and only PayloadReady
interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler
and only the payload is made available in the FIFO.
The CRC is based on the CCITT polynomial as shown below. This implementation also detects errors due to leading and
trailing zeros.
data input
X15
CRC Polynomial =X16 + X12 + X5 + 1
X14
X13
X12
X11
***
X5
X4
***
X0
Figure 33. CRC Implementation
5.5.7. DC-Free Data Mechanisms
The payload to be transmitted may contain long sequences of 1's and 0's, which introduces a DC bias in the transmitted
signal. The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. It also
introduces data dependencies in the normal operation of the demodulator. Thus it is useful if the transmitted data is random
and DC free.
For such purposes, two techniques are made available in the packet handler: Manchester encoding and data whitening.
Note
Only one of the two methods should be enabled at a time.
5.5.7.1. Manchester Encoding
Manchester encoding/decoding is enabled if DcFree = 01 and can only be used in Packet mode.
The NRZ data is converted to Manchester code by coding '1' as "10" and '0' as "01".
In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit rate is half
the chip rate.
Manchester encoding and decoding is only applied to the payload and CRC checksum while preamble and Sync word are
kept NRZ. However, the chip rate from preamble to CRC is the same and defined by BitRate in RegBitRate (Chip Rate =
Bit Rate NRZ = 2 x Bit Rate Manchester).
Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from the
FIFO.
Rev 2 - Nov 2009
Page 55
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1/BR ...Sync
RF chips @ BR
User/NRZ bits
Manchester OFF
User/NRZ bits
Manchester ON
1/BR
...
1
1
1
0
1
0
0
1
0
0
1
Payload...
0
1
1
0
1
0
...
...
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
...
...
1
1
1
0
1
0
0
1
0
1
0
1
1
1
t
...
Figure 34. Manchester Encoding/Decoding
5.5.7.2. Data Whitening
Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission.
The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence.
Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved.
The whitening/de-whitening process is enabled if DcFree = 10. A 9-bit LFSR is used to generate a random sequence. The
payload and 2-byte CRC checksum is then XORed with this random sequence as shown below. The data is de-whitened
on the receiver side by XORing with the same random sequence.
Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the
FIFO.
L F S R P o ly n o m ia l = X 9 + X 5 + 1
X8
X7
X6
X5
X4
X3
T ran sm it d ata
X2
X1
X0
W hite ne d d ata
Figure 35. Data Whitening
Rev 2 - Nov 2009
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6. Configuration and Status Registers
6.1. General Description
Table 21 Registers Summary
Reset
(built-in)
Default
(recom
mended)
Address
Register Name
0x00
RegFifo
0x00
FIFO read/write access
0x01
RegOpMode
0x04
Operating modes of the transceiver
0x02
RegDataModul
0x00
Data operation mode and Modulation settings
0x03
RegBitrateMsb
0x1A
Bit Rate setting, Most Significant Bits
0x04
RegBitrateLsb
0x0B
Bit Rate setting, Least Significant Bits
0x05
RegFdevMsb
0x00
Frequency Deviation setting, Most Significant Bits
0x06
RegFdevLsb
0x52
Frequency Deviation setting, Least Significant Bits
0x07
RegFrfMsb
0xE4
RF Carrier Frequency, Most Significant Bits
0x08
RegFrfMid
0xC0
RF Carrier Frequency, Intermediate Bits
0x09
RegFrfLsb
0x00
RF Carrier Frequency, Least Significant Bits
0x0A
RegOsc1
0x41
RC Oscillators Settings
0x0B
RegOsc2
0x40
-
0x0C
RegLowBat
0x02
Low Battery Indicator Settings
0x0D
RegListen1
0x0E
RegListen2
0xF5
Listen Mode Idle duration
0x0F
RegListen3
0x20
Listen Mode Rx duration
0x10
RegVersion
0x21
Semtech ID relating the silicon revision
0x11
RegPaLevel
0x9F
PA selection and Output Power control
0x12
RegPaRamp
0x09
Control of the PA ramp time in FSK mode
0x13
RegOcp
0x14
RegAgcRef
0x40
AGC reference level and FSK polarity control
0x15
RegAgcThresh1
0xB0
AGC thresholds control
0x16
RegAgcThresh2
0x7B
AGC thresholds control
0x17
RegAgcThresh3
0x9B
AGC thresholds control
0x18
RegLna
Rev 2 - Nov 2009
0x92
0xA2
0x0B
0x08
0x1B
0x88
Description
Listen Mode settings
Over Current Protection control
LNA settings
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Address
Register Name
Reset
(built-in)
Default
(recom
mended)
0x19
RegRxBw
0x86
0x55
Channel Filter BW Control
0x1A
RegAfcBw
0x8A
0x8B
Channel Filter BW control during the AFC routine
0x1B
RegOokPeak
0x40
OOK demodulator selection and control in peak mode
0x1C
RegOokAvg
0x80
Average threshold control of the OOK demodulator
0x1D
RegOokFix
0x06
Fixed threshold control of the OOK demodulator
0x1E
RegAfcFei
0x10
AFC and FEI control and status
0x1F
RegAfcMsb
0x00
MSB of the frequency correction of the AFC
0x20
RegAfcLsb
0x00
LSB of the frequency correction of the AFC
0x21
RegFeiMsb
0x00
MSB of the calculated frequency error
0x22
RegFeiLsb
0x00
LSB of the calculated frequency error
0x23
RegRssiConfig
0x02
RSSI-related settings
0x24
RegRssiValue
0xFF
RSSI value in dBm
0x25
RegDioMapping1
0x00
Mapping of pins DIO0 to DIO3
0x26
RegDioMapping2
0x27
RegIrqFlags1
0x80
Status register: PLL Lock state, Timeout, RSSI > Threshold...
0x28
RegIrqFlags2
0x00
Status register: FIFO handling flags, Low Battery detection...
0x29
RegRssiThresh
0x2A
RegRxTimeout1
0x00
Timeout duration between Rx request and RSSI detection
0x2B
RegRxTimeout2
0x00
Timeout duration between RSSI detection and PayloadReady
0x2C
RegPreambleMsb
0x00
Preamble length, MSB
0x2D
RegPreambleLsb
0x03
Preamble length, LSB
0x2E
RegSyncConfig
0x98
Sync Word Recognition control
0x2F-0x36
RegSyncValue1-8
0x37
RegPacketConfig1
0x10
Packet mode settings
0x38
RegPayloadLength
0x40
Payload length setting
0x39
RegNodeAdrs
0x00
Node address
0x3A
RegBroadcastAdrs
0x00
Broadcast address
0x3B
RegAutoModes
0x00
Auto modes settings
0x3C
RegFifoThresh
Rev 2 - Nov 2009
0x05
0x07
0xFF
0xE4
0x00
0x0F
0x01
0x8F
Description
Mapping of pins DIO4 and DIO5, ClkOut frequency
RSSI Threshold control
Sync Word bytes, 1 through 8
Fifo threshold, Tx start condition
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Default
(recom
mended)
Reset
(built-in)
Address
Register Name
0x3D
RegPacketConfig2
0x02
Packet mode settings
0x3E-0x4D
RegAesKey1-16
0x00
16 bytes of the cypher key
0x4E
RegTemp1
0x01
Temperature Sensor control, ADC low power mode control
0x4F
RegTemp2
0x00
Temperature readout
0x58
RegTestLna
0x1B
Sensitivity boost
0x6E
RegTestOok
0x50 +
RegTest
Note
0x06
0x0C
-
Description
OOK Demodulator adjustment
Internal test registers
- Reset values are automatically refreshed in the chip at Power On Reset
- Default values are the Semtech recommended register values, optimizing the device operation
- Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 6
Rev 2 - Nov 2009
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6.2. Common Configuration Registers
Table 22 Common Configuration Registers
Name
(Address)
RegFifo
(0x00)
RegOpMode
(0x01)
RegDataModul
(0x02)
RegBitrateMsb
(0x03)
Rev 2 - Nov 2009
Bits Variable Name
7-0
Mode
Default
Description
Value
0x00 FIFO data input/output
Fifo
rw
7
SequencerOff
rw
0
6
ListenOn
rw
0
5
ListenAbort
w
0
4-2
Mode
rw
001
1-0
7
6-5
DataMode
r
r
rw
00
0
00
4-3
ModulationType
rw
00
2
1-0
ModulationShaping
r
rw
0
00
7-0
BitRate(15:8)
rw
0x1a
Page 60
Controls the automatic Sequencer (see section 4.2 ):
0 Æ Operating mode as selected with Mode bits in
RegOpMode is automatically reached with the Sequencer
1 Æ Mode is forced by the user
Enables Listen mode:
0 Æ Off (see section 4.3)
1 Æ On
Aborts Listen mode when set together with ListenOn=0
and new Mode selection in 1 SPI access (see section 4.3)
Always reads 0.
Transceiver’s operating modes:
000 Æ Sleep mode (SLEEP)
001 Æ Standby mode (STDBY)
010 Æ Frequency Synthesizer mode (FS)
011 Æ Transmitter mode (TX)
100 Æ Receiver mode (RX)
others Æ reserved
Reads the value corresponding to the current chip mode
unused
unused
Data processing mode:
00 Æ Packet mode
01 Æ reserved
10 Æ Continuous mode with bit synchronizer
11 Æ Continuous mode without bit synchronizer
Modulation scheme:
00 Æ FSK
01 Æ OOK
10 - 11 Æ reserved
unused
Data shaping:
in FSK:
00 Æ no shaping
01 Æ Gaussian filter, BT = 1.0
10 Æ Gaussian filter, BT = 0.5
11 Æ Gaussian filter, BT = 0.3
in OOK:
00 Æ no shaping
01 Æ filtering with fcutoff = BR
10 Æ filtering with fcutoff = 2*BR
11 Æ reserved
MSB of Bit Rate (Chip Rate when Manchester encoding is
enabled)
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RegBitrateLsb
(0x04)
7-0
BitRate(7:0)
rw
RegFdevMsb
(0x05)
7-6
5-0
7-0
Fdev(13:8)
Fdev(7:0)
r
rw
rw
RegFdevLsb
(0x06)
DATASHEET
0x0b
LSB of Bit Rate (Chip Rate if Manchester encoding is
enabled)
FXOSC
BitRate = ----------------------------------BitRate (15,0)
Default value: 4.8 kb/s
00
unused
000000 MSB of the frequency deviation
0x52 LSB of the frequency deviation
Fdev = Fstep × Fdev (15,0)
RegFrfMsb
(0x07)
7-0
Frf(23:16)
rw
0xe4
Default value: 5 kHz
MSB of the RF carrier frequency
RegFrfMid
(0x08)
7-0
Frf(15:8)
rw
0xc0
Middle byte of the RF carrier frequency
RegFrfLsb
(0x09)
7-0
Frf(7:0)
rw
0x00
LSB of the RF carrier frequency
RegOsc1
(0x0A)
7
RcCalStart
w
6
RcCalDone
r
5-0
7-0
-
r
r
7-5
4
LowBatMonitor
r
rw
000
-
LowBatOn
rw
0
LowBatTrim
rw
010
RegOsc2
(0x0B)
RegLowBat
(0x0C)
Frf = Fstep × Frf ( 23 ;0 )
3
2-0
Rev 2 - Nov 2009
Default value: Frf = 915 MHz (32 MHz XO)
Triggers the calibration of the RC oscillator when set.
Always reads 0. RC calibration must be triggered in
Standby mode. See calibration procedure in section 7.3
1
0 Æ RC calibration in progress
1 Æ RC calibration is over
000001 unused
0x40 unused
0
Page 61
unused
Real-time (not latched) output of the Low Battery detector,
when enabled.
Low Battery detector enable signal
0 Æ LowBat off
1 Æ LowBat on
Trimming of the LowBat threshold:
000 Æ 1.695 V
001 Æ 1.764 V
010 Æ 1.835 V
011 Æ 1.905 V
100 Æ 1.976 V
101 Æ 2.045 V
110 Æ 2.116 V
111 Æ 2.185 V
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RegListen1
(0x0D)
7-4
ListenResol
rw
1010
*
ListenCriteria
rw
0
2-1
ListenEnd
rw
01
0
7-0
ListenCoefIdle
r
rw
0
0xf5
3
RegListen2
(0x0E)
RegListen3
(0x0F)
DATASHEET
Resolution of Listen modes timings (calibrated RC osc):
0101 Æ 64 us
1010 Æ 4.1 ms
1111 Æ 262 ms
Others Æ reserved
Criteria for packet acceptance in Listen mode:
0 Æ signal strength is above RssiThreshold
1 Æ signal strength is above RssiThreshold and
SyncAddress matched
Action taken after acceptance of a packet in Listen mode:
00 Æ chip stays in Rx mode. Listen mode stops and must
be disabled (see section 4.3).
01 Æ chip stays in Rx mode until PayloadReady or
Timeout interrupt occurs. It then goes to the mode defined
by Mode. Listen mode stops and must be disabled (see
section 4.3).
10 Æ chip stays in Rx mode until PayloadReady or
Timeout interrupt occurs. Listen mode then resumes in
Idle state. FIFO content is lost at next Rx wakeup.
11 Æ Reserved
unused
Duration of the Idle phase in Listen mode.
t ListenIdle = ListenCoefIdle ⋅ ListenResol
7-0
ListenCoefRx
rw
0x20
Duration of the Rx phase in Listen mode (startup time
included, see section 4.2.3)
t ListenRx = ListenCoefRx ⋅ ListenResol
RegVersion
(0x10)
Rev 2 - Nov 2009
7-0
Version
r
0x21
Page 62
Version code of the chip. Bits 7-4 give the full revision
number; bits 3-0 give the metal mask revision number.
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6.3. Transmitter Registers
Table 23 Transmitter Registers
Name
(Address)
RegPaLevel
(0x11)
7
6
5
4-0
Pa0On
Pa1On
Pa2On
OutputPower
rw
rw
rw
rw
Default
Value
1
0
0
11111
RegPaRamp
(0x12)
7-4
3-0
PaRamp
r
rw
0000
1001
RegOcp
(0x13)
7-5
4
OcpOn
r
rw
000
1
*
3-0
OcpTrim
rw
1011
Bits Variable Name
Mode
Description
Enables PA0, connected to RFIO and LNA
Enables PA1, on PA_BOOST pin
Enables PA2, on PA_BOOST pin
Output power setting, with 1 dB steps
Pout = -18 + OutputPower [dBm] , with PA0
Pout = -14 + OutputPower [dBm] , with PA1 and PA2
unused
Rise/Fall time of ramp up/down in FSK
0000 Æ 3.4 ms
0001 Æ 2 ms
0010 Æ 1 ms
0011 Æ 500 us
0100 Æ 250 us
0101 Æ 125 us
0110 Æ 100 us
0111 Æ 62 us
1000 Æ 50 us
1001 Æ 40 us
1010 Æ 31 us
1011 Æ 25 us
1100 Æ 20 us
1101 Æ 15 us
1110 Æ 12 us
1111 Æ 10 us
unused
Enables overload current protection (OCP) for the PA:
0 Æ OCP disabled
1 Æ OCP enabled
Trimming of OCP current:
Imax = 45 + 5 × OcpTrim ( mA )
100 mA OCP by default
Rev 2 - Nov 2009
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6.4. Receiver Registers
Table 24 Receiver Registers
Name
(Address)
RegAgcRef
(0x14)
RegAgcThresh1
(0x15)
RegAgcThresh2
(0x16)
RegAgcThresh3
(0x17)
RegLna
(0x18)
Rev 2 - Nov 2009
Bits Variable Name
7
6
Mode
AgcAutoReferenceOn
r
rw
5-0
AgcReferenceLevel
rw
7-5
AgcSnrMargin
rw
4-0
AgcStep1
rw
7-4
AgcStep2
rw
3-0
AgcStep3
rw
7-4
AgcStep4
rw
3-0
AgcStep5
rw
7
LnaZin
rw
6
LnaLowPowerOn
rw
5-3
2-0
LnaCurrentGain
LnaGainSelect
r
rw
Default
Description
Value
0
unused
1
0 Æ AGC Reference is forced in AgcReferenceLevel
1 Æ AGC Reference automatically computed by the chip:
AGC Reference [dBm] = -174 + NF + DemodSnr
+10.log(2*RxBw) + AgcSnrMargin, with:
- NF = 7: LNA’s Noise Figure at maximum gain
- DemodSnr = 8 dB, SNR needed by the demodulator
- AgcSnrMargin, as set in RegAgcThresh1
- RxBw: single sideband channel filter bandwidth
000000 To be set as close as possible to the receiver sensitivity
(-80dBm) when AgcAutoReferenceOn = 0:
AGC Reference [dBm] = -80 - AgcReferenceLevel [dB]
101
SNR margin used in the receiver sensitivity calculation
(5dB) when the AgcAutoReference = 1
10000 Defines the first AGC Threshold:
(16dB) AgcThresh1 = Agc Reference + AgcStep1
0111 Defines the second AGC Threshold:
(7dB) AgcThresh2 = AgcThresh1 + AgcStep2
1011 Defines the third AGC Threshold:
(11dB) AgcThresh3 = AgcThresh2 + AgcStep3
1001 Defines the fourth AGC Threshold:
(9dB) AgcThresh4 = AgcThresh3 + AgcStep4
1011 Defines the fifth AGC Threshold:
(11dB) AgcThresh5 = AgcThresh4 + AgcStep5
1
LNA’s input impedance
*
0 Æ 50 ohms
1 Æ 200 ohms
0
LNA and mixers low-power mode:
0 Æ normal mode
1 Æ low-power mode enabled. Power consumption is
decreased
001
Current LNA gain, set either manually, or by the AGC
000
LNA gain setting:
000 Æ gain set by the internal AGC loop
001 Æ G1 = highest gain
010 Æ G2 = highest gain – 6 dB
011 Æ G3 = highest gain – 12 dB
100 Æ G4 = highest gain – 24 dB
101 Æ G5 = highest gain – 36 dB
110 Æ G6 = highest gain – 48 dB
111 Æ reserved
Page 64
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ADVANCED COMMUNICATIONS & SENSING
RegRxBw
(0x19)
DATASHEET
7-5
DccFreq
rw
010
*
4-3
RxBwMant
rw
10
*
2-0
RxBwExp
rw
101
*
Cut-off frequency of the DC offset canceller (DCC):
4 × RxBw
fc = ----------------------------------------DccFreq + 2
2π × 2
~4% of the RxBw by default
Channel filter bandwidth control:
00 Æ RxBwMant = 16
10 Æ RxBwMant = 24
11 Æ reserved
01 Æ RxBwMant = 20
Channel filter bandwidth control:
FSK Mode:
FXOSC
RxBw = ----------------------------------------------------------------RxBwExp + 2
RxBwMant × 2
OOK Mode:
FXOSC
RxBw = ----------------------------------------------------------------RxBwExp + 3
RxBwMant × 2
RegAfcBw
(0x1A)
RegOokPeak
(0x1B)
RegOokAvg
(0x1C)
7-5
4-3
2-0
7-6
DccFreqAfc
RxBwMantAfc
RxBwExpAfc
OokThreshType
rw
rw
rw
rw
100
01
011 *
01
5-3
OokPeakTheshStep
rw
000
2-0
OokPeakThreshDec
rw
000
7-6
OokAverageThreshFilt
rw
10
See Table 13 for tabulated values
DccFreq parameter used during the AFC
RxBwMant parameter used during the AFC
RxBwExp parameter used during the AFC
Selects type of threshold in the OOK data slicer:
00 Æ fixed
10 Æ average
01 Æ peak
11 Æ reserved
Size of each decrement of the RSSI threshold in the OOK
demodulator:
001 Æ 1.0 dB
000 Æ 0.5 dB
010 Æ 1.5 dB
011 Æ 2.0 dB
100 Æ 3.0 dB
101 Æ 4.0 dB
111 Æ 6.0 dB
110 Æ 5.0 dB
Period of decrement of the RSSI threshold in the OOK
demodulator:
001 Æ once every 2 chips
000 Æ once per chip
010 Æ once every 4 chips
011 Æ once every 8 chips
101 Æ 4 times in each chip
100 Æ twice in each chip
110 Æ 8 times in each chip 111 Æ 16 times in each chip
Filter coefficients in average mode of the OOK
demodulator:
00 Æ fC ≈ chip rate / 32.π
01 Æ fC ≈ chip rate / 8.π
10 Æ fC ≈ chip rate / 4.π
11 Æ fC ≈ chip rate / 2.π
RegOokFix
(0x1D)
Rev 2 - Nov 2009
5-0
7-0
OokFixedThresh
r
rw
000000 unused
0110 Fixed threshold value (in dB) in the OOK demodulator.
(6dB) Used when OokThresType = 00
Page 65
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
7
6
FeiDone
r
r
0
0
5
4
FeiStart
AfcDone
w
r
0
1
3
AfcAutoclearOn
rw
0
2
AfcAutoOn
rw
0
1
0
7-0
AfcClear
AfcStart
AfcValue(15:8)
w
w
rw
0
0
0x00
RegAfcLsb
(0x20)
7-0
AfcValue(7:0)
rw
0x00
RegFeiMsb
(0x21)
7-0
FeiValue(15:8)
r
-
MSB of the measured frequency offset, 2’s complement
RegFeiLsb
(0x22)
7-0
FeiValue(7:0)
r
-
LSB of the measured frequency offset, 2’s complement
Frequency error = FeiValue x Fstep
RegRssiConfig
(0x23)
7-4
3
FastRx
r
rw
0000
0
RegAfcFei
(0x1E)
RegAfcMsb
(0x1F)
RegRssiValue
(0x24)
Rev 2 - Nov 2009
2
1
RssiDone
r
r
0
1
0
7-0
RssiStart
RssiValue
w
r
0
0xFF
Page 66
unused
0 Æ FEI is on-going
1 Æ FEI finished
Triggers a FEI measurement when set. Always reads 0.
0 Æ AFC is on-going
1 Æ AFC has finished
Only valid if AfcAutoOn is set
0 Æ AFC register is not cleared before a new AFC phase
1 Æ AFC register is cleared before a new AFC phase
0 Æ AFC is performed each time AfcStart is set
1 Æ AFC is performed each time Rx mode is entered
Clears the AfcValue when set. Always reads 0
Triggers an AFC when set. Always reads 0.
MSB of the AfcValue, 2’s complement format
LSB of the AfcValue, 2’s complement format
Frequency correction = AfcValue x Fstep
unused
Fast or standard Rx wakeup sequence
0 Æ 2 RSSI samples over RssiThreshold are required to
start the receiver
1 Æ 1 RSSI sample over RssiThreshold is enough to start
the receiver
unused
0 Æ RSSI is on-going
1 Æ RSSI sampling is finished, result available
Trigger a RSSI measurement when set. Always reads 0.
Absolute value of the RSSI in dBm, 0.5dB steps.
RSSI = -RssiValue/2 [dBm]
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6.5. IRQ and Pin Mapping Registers
Table 25 IRQ and Pin Mapping Registers
Name
(Address)
RegDioMapping1
(0x25)
RegDioMapping2
(0x26)
RegIrqFlags1
(0x27)
Rev 2 - Nov 2009
Bits Variable Name
Mode
Default
Value
00
00
00
00
00
00
0
111
*
7-6
5-4
3-2
1-0
7-6
5-4
3
2-0
Dio0Mapping
Dio1Mapping
Dio2Mapping
Dio3Mapping
Dio4Mapping
Dio5Mapping
ClkOut
rw
rw
rw
rw
rw
rw
r
rw
7
ModeReady
r
1
6
RxReady
r
0
5
TxReady
r
0
4
PllLock
r
0
3
Rssi
rwc
0
2
Timeout
r
0
1
AutoMode
r
0
0
SyncAddressMatch
r/rwc
0
Page 67
Description
Mapping of pins DIO0 to DIO5
See Table 19 for mapping in Continuous mode
See Table 20 for mapping in Packet mode
unused
Selects CLKOUT frequency:
000 Æ FXOSC
001 Æ FXOSC / 2
010 Æ FXOSC / 4
011 Æ FXOSC / 8
100 Æ FXOSC / 16
101 Æ FXOSC / 32
110 Æ RC (automatically enabled)
111 Æ OFF
Set when the operation mode requested in Mode, is ready
- Sleep: Entering Sleep mode
- Standby: XO is running
- FS: PLL is locked
- Rx: RSSI sampling starts
- Tx: PA ramp-up completed
Cleared when changing operating mode.
Set in Rx mode, after RSSI, AGC and AFC.
Cleared when leaving Rx.
Set in Tx mode, after PA ramp-up.
Cleared when leaving Tx.
Set (in FS, Rx or Tx) when the PLL is locked.
Cleared when it is not.
Set in Rx when the RssiValue exceeds RssiThreshold.
Cleared when leaving Rx.
Set when a timeout occurs (see TimeoutRxStart and
TimeoutRssiThresh)
Cleared when leaving Rx or FIFO is emptied.
Set when entering Intermediate mode.
Cleared when exiting Intermediate mode.
Please note that in Sleep mode a small delay can be
observed between AutoMode interrupt and the
corresponding enter/exit condition.
Set when Sync and Address (if enabled) are detected.
Cleared when leaving Rx or FIFO is emptied.
This bit is read only in Packet mode, rwc in Continuous
mode
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RegIrqFlags2
(0x28)
DATASHEET
7
FifoFull
r
0
6
5
FifoNotEmpty
FifoLevel
r
r
0
0
4
FifoOverrun
rwc
0
3
PacketSent
r
0
2
PayloadReady
r
0
1
CrcOk
r
0
0
LowBat
rwc
-
RegRssiThresh
(0x29)
7-0
RssiThreshold
rw
0xE4
*
RegRxTimeout1
(0x2A)
7-0
TimeoutRxStart
rw
0x00
RegRxTimeout2
(0x2B)
7-0
TimeoutRssiThresh
rw
0x00
Rev 2 - Nov 2009
Page 68
Set when FIFO is full (i.e. contains 66 bytes), else
cleared.
Set when FIFO contains at least one byte, else cleared
Set when the number of bytes in the FIFO strictly exceeds
FifoThreshold, else cleared.
Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The
FIFO then becomes immediately available for the next
transmission / reception.
Set in Tx when the complete packet has been sent.
Cleared when exiting Tx.
Set in Rx when the payload is ready (i.e. last byte
received and CRC, if enabled and CrcAutoClearOff is
cleared, is Ok). Cleared when FIFO is empty.
Set in Rx when the CRC of the payload is Ok. Cleared
when FIFO is empty.
Set when the battery voltage drops below the Low Battery
threshold. Cleared only when set by the user.
RSSI trigger level for Rssi interrupt :
- RssiThreshold / 2 [dBm]
Timeout interrupt is generated TimeoutRxStart*16*Tbit
after switching to Rx mode if Rssi interrupt doesn’t occur
(i.e. RssiValue > RssiThreshold)
0x00: TimeoutRxStart is disabled
Timeout interrupt is generated TimeoutRssiThresh*16*Tbit
after Rssi interrupt if PayloadReady interrupt doesn’t
occur.
0x00: TimeoutRssiThresh is disabled
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6.6. Packet Engine Registers
Table 26 Packet Engine Registers
Name
(Address)
Bits Variable Name
Mode
Default
Description
Value
0x00 Size of the preamble to be sent (from TxStartCondition
fulfilled). (MSB byte)
RegPreambleMsb
(0x2c)
7-0
PreambleSize(15:8)
rw
RegPreambleLsb
(0x2d)
7-0
PreambleSize(7:0)
rw
0x03
7
SyncOn
rw
1
6
FifoFillCondition
rw
0
5-3
SyncSize
rw
011
2-0
7-0
SyncTol
SyncValue(63:56)
rw
rw
000
0x00
RegSyncValue2
(0x30)
7-0
SyncValue(55:48)
rw
0x01
*
2nd byte of Sync word
Used if SyncOn is set and (SyncSize +1) >= 2.
RegSyncValue3
(0x31)
7-0
SyncValue(47:40)
rw
0x01
*
3rd byte of Sync word.
Used if SyncOn is set and (SyncSize +1) >= 3.
RegSyncValue4
(0x32)
7-0
SyncValue(39:32)
rw
0x01
*
4th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) >= 4.
RegSyncValue5
(0x33)
7-0
SyncValue(31:24)
rw
0x01
*
5th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) >= 5.
RegSyncValue6
(0x34)
7-0
SyncValue(23:16)
rw
0x01
*
6th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) >= 6.
RegSyncValue7
(0x35)
7-0
SyncValue(15:8)
rw
0x01
*
7th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) >= 7.
RegSyncValue8
(0x36)
7-0
SyncValue(7:0)
rw
0x01
*
8th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) = 8.
RegSyncConfig
(0x2e)
RegSyncValue1
(0x2f)
Rev 2 - Nov 2009
Page 69
Size of the preamble to be sent (from TxStartCondition
fulfilled). (LSB byte)
Enables the Sync word generation and detection:
0 Æ Off
1 Æ On
FIFO filling condition:
0 Æ if SyncAddress interrupt occurs
1 Æ as long as FifoFillCondition is set
Size of the Sync word:
(SyncSize + 1) bytes
Number of tolerated errors in Sync word
1st byte of Sync word. (MSB byte)
Used if SyncOn is set.
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PacketFormat
rw
0
6-5
DcFree
rw
00
4
CrcOn
rw
1
3
CrcAutoClearOff
rw
0
2-1
AddressFiltering
rw
00
0
7-0
PayloadLength
rw
rw
0
0x40
RegNodeAdrs
(0x39)
7-0
NodeAddress
rw
0x00
Defines the packet format used:
0 Æ Fixed length
1 Æ Variable length
Defines DC-free encoding/decoding performed:
00 Æ None (Off)
01 Æ Manchester
10 Æ Whitening
11 Æ reserved
Enables CRC calculation/check (Tx/Rx):
0 Æ Off
1 Æ On
Defines the behavior of the packet handler when CRC
check fails:
0 Æ Clear FIFO and restart new packet reception. No
PayloadReady interrupt issued.
1 Æ Do not clear FIFO. PayloadReady interrupt issued.
Defines address based filtering in Rx:
00 Æ None (Off)
01 Æ Address field must match NodeAddress
10 Æ Address field must match NodeAddress or
BroadcastAddress
11 Æ reserved
unused
If PacketFormat = 0 (fixed), payload length.
If PacketFormat = 1 (variable), max length in Rx, not used
in Tx.
Node address used in address filtering.
RegBroadcastAdrs
(0x3A)
7-0
BroadcastAddress
rw
0x00
Broadcast address used in address filtering.
RegAutoModes
(0x3B)
7-5
EnterCondition
rw
000
4-2
ExitCondition
rw
000
1-0
IntermediateMode
rw
00
Interrupt condition for entering the intermediate mode:
000 Æ None (AutoModes Off)
001 Æ Rising edge of FifoNotEmpty
010 Æ Rising edge of FifoLevel
011 Æ Rising edge of CrcOk
100 Æ Rising edge of PayloadReady
101 Æ Rising edge of SyncAddress
110 Æ Rising edge of PacketSent
111 Æ Falling edge of FifoNotEmpty (i.e. FIFO empty)
Interrupt condition for exiting the intermediate mode:
000 Æ None (AutoModes Off)
001 Æ Falling edge of FifoNotEmpty (i.e. FIFO empty)
010 Æ Rising edge of FifoLevel or Timeout
011 Æ Rising edge of CrcOk or Timeout
100 Æ Rising edge of PayloadReady or Timeout
101 Æ Rising edge of SyncAddress or Timeout
110 Æ Rising edge of PacketSent
111 Æ Rising edge of Timeout
Intermediate mode:
00 Æ Sleep mode (SLEEP)
01 Æ Standby mode (STDBY)
10 Æ Receiver mode (RX)
11 Æ Transmitter mode (TX)
RegPacketConfig1
(0x37)
RegPayloadLength
(0x38)
Rev 2 - Nov 2009
7
DATASHEET
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SX1231
ADVANCED COMMUNICATIONS & SENSING
RegFifoThresh
(0x3C)
RegPacketConfig2
(0x3D)
7
TxStartCondition
rw
FifoThreshold
InterPacketRxDelay
rw
rw
3
2
RestartRx
rw
w
1
AutoRxRestartOn
rw
0
AesOn
rw
6-0
7-4
DATASHEET
1
*
Defines the condition to start packet transmission :
0 Æ FifoLevel (i.e. the number of bytes in the FIFO
exceeds FifoThreshold)
1 Æ FifoNotEmpty (i.e. at least one byte in the FIFO)
0001111 Used to trigger FifoLevel interrupt.
0000 After PayloadReady occurred, defines the delay between
FIFO empty and the start of a new RSSI phase for next
packet. Must match the transmitter’s PA ramp-down time.
- Tdelay = 0 if InterpacketRxDelay >= 12
- Tdelay = (2InterpacketRxDelay) / BitRate otherwise
0
unused
0
Forces a new RSSI phase to start a new packet reception.
Always reads 0.
1
Enables automatic Rx restart (RSSI phase) after
PayloadReady occurred and packet has been completely
read from FIFO:
0 Æ Off. RestartRx can be used.
1 Æ On. Rx automatically restarted after
InterPacketRxDelay.
0
Enable the AES encryption/decryption:
0 Æ Off
1 Æ On (payload limited to 66 bytes maximum)
0x00 1st byte of cipher key (MSB byte)
RegAesKey1
(0x3E)
7-0
AesKey(127:120)
w
RegAesKey2
(0x3F)
7-0
AesKey(119:112)
w
0x00
2nd byte of cipher key
RegAesKey3
(0x40)
7-0
AesKey(111:104)
w
0x00
3rd byte of cipher key
RegAesKey4
(0x41)
7-0
AesKey(103:96)
w
0x00
4th byte of cipher key
RegAesKey5
(0x42)
7-0
AesKey(95:88)
w
0x00
5th byte of cipher key
RegAesKey6
(0x43)
7-0
AesKey(87:80)
w
0x00
6th byte of cipher key
RegAesKey7
(0x44)
7-0
AesKey(79:72)
w
0x00
7th byte of cipher key
RegAesKey8
(0x45)
7-0
AesKey(71:64)
w
0x00
8th byte of cipher key
RegAesKey9
(0x46)
7-0
AesKey(63:56)
w
0x00
9th byte of cipher key
RegAesKey10
(0x47)
7-0
AesKey(55:48)
w
0x00
10th byte of cipher key
RegAesKey11
(0x48)
7-0
AesKey(47:40)
w
0x00
11th byte of cipher key
RegAesKey12
(0x49)
7-0
AesKey(39:32)
w
0x00
12th byte of cipher key
RegAesKey13
(0x4A)
7-0
AesKey(31:24)
w
0x00
13th byte of cipher key
RegAesKey14
(0x4B)
7-0
AesKey(23:16)
w
0x00
14th byte of cipher key
Rev 2 - Nov 2009
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
RegAesKey15
(0x4C)
7-0
AesKey(15:8)
w
0x00
15th byte of cipher key
RegAesKey16
(0x4D)
7-0
AesKey(7:0)
w
0x00
16th byte of cipher key (LSB byte)
6.7. Temperature Sensor Registers
Table 27 Temperature Sensor Registers
Name
(Address)
Bits Variable Name
RegTemp1
(0x4E)
7-4
3
RegTemp2
(0x4F)
Mode
TempMeasStart
r
w
2
TempMeasRunning
r
1
0
AdcLowPowerOn
7-0
TempValue
r
rw
r
Default
Description
Value
0000 unused
0
Triggers the temperature measurement when set. Always
reads 0.
0
Set to 1 while the temperature measurement is running.
Toggles back to 0 when the measurement has completed.
The receiver can not be used while measuring
temperature
0
unused
1
ADC low-power mode:
0 Æ normal mode
1 Æ low-power mode enabled. Power consumption is
decreased
Measured temperature
-1°C per Lsb
Needs calibration for accuracy
6.8. Test Registers
Table 28 Test Registers
Name
(Address)
RegTestLna
(0x58)
RegTestOok
(0x6E)
Rev 2 - Nov 2009
Bits Variable Name
Mode
7-0
SensitivityBoost
rw
7-0
OokDeltaThreshold
rw
Default
Description
Value
0x1B High sensitivity or normal sensitivity mode:
0x1B Æ Normal mode
0x2D Æ High sensitivity mode
0x0C Tweaks the OOK Peak Threshold
*
Page 72
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
7. Application Information
7.1. Crystal Resonator Specification
Table 29 shows the crystal resonator specification for the crystal reference oscillator circuit of the SX1231. This
specification covers the full range of operation of the SX1231 and is employed in the reference design.
Table 29 Crystal Specification
Symbol
Description
FXOSC
XTAL Frequency
RS
Conditions
Min
Typ
Max
26
-
32
MHz
XTAL Serial Resistance
-
30
140
ohms
C0
XTAL Shunt Capacitance
-
2.8
7
pF
CLOAD
External Foot Capacitance
8
16
22
pF
On each pin XTA and XTB
Unit
Notes - the initial frequency tolerance, temperature stability and ageing performance should be chosen in accordance
with the target operating temperature range and the receiver bandwidth selected.
- the loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL.
- A minimum XTAL frequency of 28 MHz is required to cover the 863-870 MHz band, 29 MHz for the 902-928 MHz
band
7.2. Reset of the Chip
A power-on reset of the SX1231 is triggered at power up. Additionally, a manual reset can be issued by controlling pin 6.
7.2.1. POR
If the application requires the disconnection of VDD from the SX1231, despite of the extremely low Sleep Mode current, the
user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 6
(Reset) should be left floating during the POR sequence.
VDD
Pin 6
(output)
Undefined
Wait for
10 ms
Chip is ready from
this point on
Figure 36. POR Timing Diagram
Please note that any CLKOUT activity can also be used to detect that the chip is ready.
Rev 2 - Nov 2009
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
7.2.2. Manual Reset
A manual reset of the SX1231 is possible even for applications in which VDD cannot be physically disconnected. Pin 6
should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the
chip.
VDD
Pin 6
(input)
High-Z
> 100 us
Wait for
5 ms
’’1’’
High-Z
Chip is ready from
this point on
Figure 37. Manual Reset Timing Diagram
Note
whilst pin 6 is driven high, an over current consumption of up to ten milliamps can be seen on VDD.
7.3. RC Oscillator Calibration
The calibration of the internal oscillator is required when using the Listen mode of the SX1231. The calibration procedure
source code is the following:
/////// RC CALIBRATION (Once at POR) ///////
SetRFMode(RF_STANDBY);
WriteRegister(0x57, 0x80);
WriteRegister(REG_OSC1, ReadRegister(REG_OSC1) | 0x80);
while (ReadRegister(REG_OSC1) & 0x40 == 0x00);
WriteRegister(REG_OSC1, ReadRegister(REG_OSC1) | 0x80);
while (ReadRegister(REG_OSC1) & 0x40 == 0x00);
WriteRegister(0x57, 0x00);
////////////////////////////////////////////
7.4. Reference Design
Please contact your Semtech representative for evaluation tools, reference designs and design assistance.
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
8. Packaging Information
8.1. Package Outline Drawing
The SX1231 is available in a 24-lead QFN package as show in Figure 38.
A
DIMENSIONS
MILLIMETERS
MIN NOM MAX
B
D
DIM
E
PIN 1
INDICATOR
(LASER MARK)
A1
A2
A
SEATING
PLANE
aaa C
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
0.80 1.00
0.00
0.05
- (0.20) 0.25 0.30 0.35
4.90 5.00 5.10
3.20 3.25 3.30
4.90 5.00 5.10
3.20 3.25 3.30
0.65 BSC
0.35 0.40 0.45
24
0.08
0.10
C
LxN
D1
E/2
E1
2
1
N
bxN
e/2
bbb
C A B
e
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Figure 38. Package Outline Drawing
8.2. Recommended Land Pattern
K
DIMENSIONS
(C) H
G
Z
Y
X
DIM
C
G
H
K
P
X
Y
Z
MILLIMETERS
(4.90)
4.10
3.30
3.30
0.65
0.35
0.80
5.70
P
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
Figure 39. Recommended Land Pattern
Rev 2 - Nov 2009
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SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
8.3. Thermal Impedance
The thermal impedance of this package is: Theta ja = 29° C/W typ., calculated from a package in still air, on a 4-layer FR4
PCB, as per the Jedec standard.
8.4. Tape & Reel Specification
Figure 40. Tape & Reel Specification
Note
Single Sprocket holes
Rev 2 - Nov 2009
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
9. Revision History
Table 30 Revision History
Revision
1
Date
Oct 2009
2
Nov 2009
Rev 2 - Nov 2009
Comment
First FINAL datasheet version
Clarification and adjustment on the specification
Corrections throughout the document
Improve AGC setting description, Temp sensor description
Page 77
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ADVANCED COMMUNICATIONS & SENSING
DATASHEET
© Semtech 2009
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes
no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper
installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to
parameters beyond the specified maximum ratings or operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN
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SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S
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indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs damages and attorney fees which could arise.
Contact information
Semtech Corporation
Advanced Communication and Sensing Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
E-mail: [email protected]
[email protected]
Internet: http://www.semtech.com
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