ACS8947T JAM PLL Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path ADVANCED COMMUNICATIONS COMMS & SENSING FINAL EVALUATION BOARD ACS8947T JAM PLL Evaluation Board (EVB) Kit About this document This document is the user guide for the ACS8947T JAM PLL Evaluation Board (EVB) Kit, comprising PCB hardware and PC software. The guide describes how to set-up and operate this equipment to exercise and evaluate the functionality of the ACS8947T JAM PLL, and includes the PCB Schematic and Bill of Materials (BOM). This document should be read in conjunction with the ACS8947T JAM PLL Datasheet. The Graphical User Interface (GUI) of the ACS8947T JAM PLL Evaluation Board has a comprehensive embedded help system. Revision 1.0/September 2007 © Semtech Corp. Page 1 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Table of Contents FINAL EVALUATION BOARD Section Page About this document .................................................................................................................................................................................1 Description ................................................................................................................................................................................................ 3 Features .................................................................................................................................................................................................... 3 Minimum Requirements ........................................................................................................................................................................... 3 Hardware Description................................................................................................................................................................................ 4 PCB Description ................................................................................................................................................................................5 GUI Software Description ..........................................................................................................................................................................8 GUI Controls: General Operation ......................................................................................................................................................8 GUI Controls and Display Elements .................................................................................................................................................9 Autoconfigure ...........................................................................................................................................................................9 Input Frequency Selection ....................................................................................................................................................... 9 Input Reference Selector MUX ................................................................................................................................................ 9 External Feedback Selector MUX ............................................................................................................................................9 Status of Input References ......................................................................................................................................................9 Input and Feedback Dividers ...................................................................................................................................................9 Odd Divider ............................................................................................................................................................................ 10 Charge Pump Indicator ......................................................................................................................................................... 10 Lock Detector ........................................................................................................................................................................ 10 Output Type Selector ............................................................................................................................................................. 10 Reset/Off-line Button ............................................................................................................................................................ 11 PLL BW Comps Display ......................................................................................................................................................... 11 Resynchronization Block ....................................................................................................................................................... 11 Jumper Settings Tab ............................................................................................................................................................. 11 Pinout Tab .............................................................................................................................................................................. 12 Loop Filter Calculator Tab ..................................................................................................................................................... 12 PCB Layout Recommendations ............................................................................................................................................................. 13 Bill of Materials ....................................................................................................................................................................................... 14 PCB Schematic ....................................................................................................................................................................................... 16 Trademark Acknowledgements ............................................................................................................................................................. 17 Acronyms & Abbreviations ..................................................................................................................................................................... 17 Revision Status/History ......................................................................................................................................................................... 17 Notes ....................................................................................................................................................................................................... 17 Ordering Information .............................................................................................................................................................................. 18 Disclaimers ..................................................................................................................................................................................... 18 Contact Information ................................................................................................................................................................................ 18 Revision 1.0/September 2007 © Semtech Corp. Page 2 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Description FINAL Features The ACS8947T JAM PLL Evaluation Board (EVB) and software GUI package provides the means to quickly set up and evaluate the JAM PLL, with an intuitive screen for rapid configuration, control and monitoring of all parameters relating to the device and its operating environment. The ACS8947T device can be configured, controlled and monitored from a PC using the supplied software and the interface provided on board. The PC parallel port is used to connect to the board and the driver software runs on a Windows (95/98/NT4/ME/2000/XP) PC. If the PCB is not connected to the PC, the GUI can still be used independently to provide configuration information. The user enters the required I/O and divider selections, and the GUI responds by providing a graphical representation of the necessary jumper/switch settings needed to manually configure the PCB to achieve this configuration, as well showing what pin-to-pin connectivity is being applied on the ACS8947T device to configure it. The board provides differential line input and output connections via SMB connectors, with provision for the appropriate termination circuitry for different applications. The required RC components that define the loop filter bandwidth can be determined from the datasheet for the specific application. These must then be soldered to the underside of the board. Z EVALUATION BOARD PC driver software with: intuitive graphical controls graphical device status display Z 6-layer populated PCB Z Windows 95/98/NT4/ME/2000/XP compatible Z Surface-mounted ACS8947T JAM PLL Z SMB connectors for reference clock and sync inputs and outputs Z EPLD to provide logic to implement configuration of ACS8947T and drive on-board LED indicators and alarms Z Configuration jumpers and switches for an alternative means to configure the ACS8947T instead of via PC Z LED indicators for: Input reference selected/not selected Activity on input reference detected/not detected Activity on selected reference detected/not detected Selected reference input locked/near locked/not locked Auto-reference selection on/off PC Control enabled/disabled Z Jumpers to enable/disable each output port Z Pushbutton switches for auto reference selection or individual manual input reference selection of CLK1, CLK2 or external feedback, and board reset Z Switches to manually configure output frequency selection Z Footprint provision for termination circuitry appropriate for CML or LVPECL I/O Z Single 5 V supply connection with on-board 3.3 V regulator Figure 1 Typical JAM PLL Evaluation Board and GUI Minimum Requirements Revision 1.0/September 2007 © Semtech Corp. Z IBM-compatible PC Z P200 MHz CPU Z Parallel port for direct configuration from GUI Z Mouse Z VGA monitor Z Microsoft Windows 95 Page 3 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Hardware Description FINAL EVALUATION BOARD Figure 2 Annotated EVB - Top 7 L 12) G H I J 8947 Revision 1.0/September 2007 © Semtech Corp. Page 4 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING FINAL EVALUATION BOARD Figure 3 Annotated EVB - Bottom View PLL Loop filter components, with footprint options for different capacitor sizes Datasheet CP2 = C10 (requires a zero ohm link for R32, with C9 unpopulated) or Datasheet CP2 = C9 (C10 and R32 unpopulated) 3.3V Supply Decoupling Capacitors, C25 to C49 Datasheet CP1 = C5 (requires a zero ohm link for R29, with C6 unpopulated) or Datasheet CP1= C6 (C5 and R31 unpopulated) Datasheet RS2 = R31 Datasheet CS2 = C8 Datasheet RS1 = R30 Datasheet CS1 = C7 C10 CP2 R33 not part of loop C8 C9 R32 R31 C10 VSS3V CS2 VCN RS2 C5 Internal Gnd Do not use CP1 C6 R29 C7 R30 VSS3V CS1 VCP RS1 Internal Gnd Do not use F8946EVB_annotbotfig2_01 PCB Description Figures 2 to 5 indicate the location of the main PCB components referred to in this description. The Datasheet terms in red in Figure 3 refer to the loop filter components in the Charge Pumps and External Lowpass Filter section of the ACS8947T datasheet. The board requires a single 5 V DC supply. Banana jacks provide the connection for the supply via terminal SK4. A 5 V supply is used for the electrically programmable logic device (EPLD), parallel port lamp, alarm/reference selection lamps and configuration jumper circuitry. The 5 V supply is reduced by voltage regulator IC4 to provide 3.3 V supplies for the ACS8947T. Decoupling capacitors (100 uF) are provided for the supply near SK4, and each IC has adjacent supply decoupling capacitors. The ACS8947T can be controlled and monitored from a PC. A printer port cable with a 36-way Centronics plug to 25 pin D-type plug is required to connect the Evaluation Board to a PC. The Centronics printer port of the PC, which runs on a 0 V to 5 V interface to and from the PC, is used to communicate with the parallel port interface of the board in bidirectional/EPP protocol mode. Revision 1.0/September 2007 © Semtech Corp. The EPLD provides the logic and buffering to control the configuration of the ACS8947T according to the configuration defined in software by the user, or by the jumper configuration (JMP1 thru JMP12). Under PC control (indicated when LED D10 is illuminated), any hardware configuration control is disabled and overridden, except for the output enable jumpers JMP16, JMP17, JMP19 and JMP20, which, if removed, power down the outputs. The EPLD is used for PC configuration control of the ACS8947T and is not required in the end application. Manual reset switch SW7 should be pressed after a manual configuration change, so that the configurations can take effect. However, if the board is under PC control, the manual reset switch should not be used: instead, reset should be executed from the reset softswitch on the GUI. (The GUI will advise when to apply a softswitch reset). Page 5 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING FINAL EVALUATION BOARD Figure 4 PCB Component Layout - Top Plan View Revision 1.0/September 2007 © Semtech Corp. Page 6 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING FINAL EVALUATION BOARD Figure 5 PCB Component Layout - Underside View Note...Areas shaded blue are populated by components Revision 1.0/September 2007 © Semtech Corp. Page 7 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING GUI Software Description FINAL EVALUATION BOARD Figure 6 EVB Software GUI Note...The GUI screen examples in this document are generic; they may differ for specific variants/software releases. The PC-based GUI is shown in Figure 6. The GUI is an interactive tool which should be used to configure the device directly or, if the PC is not connected to the PCB, to determine the required physical configuration. For example, the user enters the desired input and output frequencies and, if the PC is connected to the PCB, the device is configured on reset from the GUI or, in some cases, instantaneously. If the PC is not connected to the PCB, then the software can still be used as it returns the correct jumper and switch configurations that the user must set manually to achieve the configuration selected in the GUI. The GUI indicates if a reset is required by changing the color of the reset softswitch to red. Elements that are flat (yellow/white) may contain information that is updated on configuration change or reset. MUX selector softswitch If a reset is required, the Reset switch changes from to GUI Controls: General Operation All GUI control elements shown with drop shadows provide actions when clicked. For example, the MUX selector softswitch shown opposite is an action element. Configuration changes made by using green action elements are configured instantly: those made by using blue action elements take place on power-up/reset. Revision 1.0/September 2007 © Semtech Corp. indicating that the user must click on the Reset switch for the configuration to take place. Clicking on Reset causes parameter updates to be made and these are reflected in the GUI. Page 8 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING GUI Controls and Display Elements FINAL EVALUATION BOARD External Feedback Selector MUX Autoconfigure Press Auto Configure to open a dialog that allows the internal dividers to be automatically configured to produce a desired output frequency. Click on MUX symbol to toggle between normal mode or external feedback mode. In external feedback mode, CLK2 provides the external feedback path to the phase and frequency detector (PFD). Status of Input References Activity monitors are provided for each input. Red indicates inactivity, green indicates activity. These correspond to the PCB alarm LEDs D2 and D3. ALARM C (not shown) is provided also, which indicates activity or inactivity on the currently selected reference. Input Frequency Selection > The desired input frequency. Input and Feedback Dividers Input Reference Selector MUX Click on MUX symbol to cycle through the three input reference selection options: CLK1 CLK2 AUTO Select. Revision 1.0/September 2007 © Semtech Corp. IP Divider (1 to 256) and FB Divider (1 to 512) ratios can be programmed by using the Auto Configure function, or set directly by entering the required divider ratios into the divider dialog. Page 9 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING FINAL Odd Divider EVALUATION BOARD Output Dividers Odd Divider (1 to 15) cab be programmed by using the Auto Configure function, or set directly as follows: Click on OP Div By pulldown menu to select required odd integer division, or select 1 to effectively bypass the odd divide function. The resulting divided-down frequencies are available for selection at each of the four outputs. Charge Pump Indicator The Output Dividers pulldown menus allow the user to define the set of four “available rates” which will be the chip’s outputs. Any of the six available rates can be selected as many times as required. Output Type Selector The Charge Pump indicator displays the resulting charge pump current for a given I/O frequency configuration. Lock Detector Click on the Lock Detector pulldown menu to enable/disable the lock detector. The configuration of LVPECL or CML output type for outputs OUT1 thru OUT4 is also made from the Outputs Selector. Output type is applied on power-up or reset to independent pairs of outputs (OUT1/OUT2 and OUT3/OUT4) via selection boxes immediately above each pair of output frequency indicators. If enabled, LOCKB indicator illuminates as follows: • Green: PLL is locked to the reference input (charge pump voltage on LOCKB below 0.4 V), • Amber: PLL Near lock (charge pump voltage on LOCKB between 0.4 V and 1.4 V), • Red: PLL Not locked (charge pump voltage on LOCKB above 1.4 V). Note: Some PC parallel port configurations may not correctly display the lock detector indicator on the GUI. If in doubt check the Lock Detector LED (D11) on the PCB. Revision 1.0/September 2007 © Semtech Corp. Page 10 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING FINAL Reset/Off-line Button EVALUATION BOARD Jumper Settings Tab When the GUI is connected to the Evaluation Board this button will appear as a reset button. The button is used to apply power-up configuration settings (shown in purple in the tab) to the ACS8947T. If the Evaluation Board is not connected to the GUI, then this button will appear as a black off-line box. PLL BW Comps Display This panel displays the PLL bandwidth components calculated in the Loop Filter Calculator. The components are only displayed if they are valid for the current configuration of the schematic diagram. If the components have not been calculated yet, or the configuration has been changed since the components were last calculated then "Not Calculated" will be displayed. If the Evaluation Board is not connected to the PC, then the required cross-connections for a given ACS8947T configuration must be made by manually adjusting jumpers on the board. The GUI provides the Jumper Positions tab to help position the jumpers to configure the board. The tab gives a visual representation of the required jumper settings for a given configuration. To configure the ACS8947T using jumpers: 1. Setup your desired chip configuration in the Circuit Schematic tab. Resynchronization Block 2. Select the Jumper Positions tab - the tab contains a diagram showing the configuration header pins on the Evaluation Board and the jumper positions (marked in red) required to achieve the chip configuration shown in the Circuit Schematic tab. 3. Disconnect power from PCB before moving Jumpers. If resynchronization is being used, then the rising edge of OUT1 will be used to resynchronize the sync signal. 4. Adjust the jumpers on the PCB to match those in the Jumper Settings. 5. Reconnect power to the PCB. The ACS8947T adopts the new configuration on power-up. Revision 1.0/September 2007 © Semtech Corp. Page 11 www.semtech.com ACS8947T JAM PLL Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for OC-12/STM-4 and GbE ADVANCED COMMUNICATIONS COMMS & SENSING FINAL Pinout Tab EVALUATION BOARD This page is a guide to the Loop Filter Calculator tab. The numbering of the explanations below refers to the labelled screenshot: 1. Closed Loop Bandwidth Enter the required closed loop bandwidth for the loop filter. The bandwidth must be greater than 2kHz and less than one tenth of the PFD input frequency (= the input frequency divided by the input divider value). 2. Phase Margin/Damping Factor The Pinout tab provides a cross-connect diagram, showing the required ACS8947T pin-to-pin connections that would need to be made to implement the configuration chosen in the Schematic Circuit tab. The diagram is automatically updated as the configuration settings in the Schematic Circuit tab are changed. This schematic may be used to define the hard wire connections required to configure the ACS8947T in the end application PCB design. The second parameter can be entered as either a phase margin or damping factor. The pull down menu is used to select which of these will be used - switching to the other parameter will convert the entered value. 3. Component Series Select the series to be used for each component (Cp, Cs and Rs). The chosen series determines the range of possible values for the components: E6 - 1, 1.5, 2.2, 3.3, 4.7, 6.8 E12 - 1, 1.2, 1.5, 1.8, 2.2, 2.7, 3.3, 3.9, 4.7, 5.6, 6.8, 8.2 Loop Filter Calculator Tab E24 - 1, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2.0, 2.2, 2.4, 2.7, 3.0, 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1 4. Component Tolerance If component tolerances are required for the calculation, the tolerances check box [5] must be ticked. The tolerances of each component (Cp, Cs and Rs) can then be selected from the option boxes. The following tolerances are available: Once the configuration of the device is complete, the loop filter components must be calculated. To help determine suitable values, the software provides the Loop Filter Calculator tab. Before using the calculator, set up the chosen configuration in the Circuit Schematic tab. If the configuration in the Circuit Schematic tab is changed so that the component values and output parameters are no longer valid for the current configuration, then the loop filter calculator results will be cleared. Revision 1.0/September 2007 © Semtech Corp. 1% 5% 10% 5. Use Tolerances Option If deselected, the calculator will only determine a nominal jitter transfer function. If selected, the calculator generates additional jitter transfer functions for minimum and maximum, bandwidth and peaking. The calculator uses the specified tolerances for the components, together with the charge pump current and Kvco tolerances. Page 12 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING 6. Calculate FINAL EVALUATION BOARD PCB Layout Recommendations Once the input parameters are entered click the Calculate button to start the calculations. The GUI will perform the calculations with nominal values and then if the tolerances check box is ticked it will use the tolerance values to produce the maximum and minimum values for bandwidth and peaking. 7. Status Bar 1. A generous ground plane should be provided around the IC to minimize noise and maximize the effectiveness of decoupling components. The status bar gives progress information whilst the calculations are being performed. 8. Output Values Minimum, nominal and maximum values for the closed loop bandwidth, phase margin, damping factor and peaking parameters will be displayed as the calculations are performed. Minimum and maximum values will only be displayed if tolerances were used in the calculation. 9. Closed-Loop Jitter Transfer The graph shows the closed-loop jitter transfer, with gain plotted against frequency. Nominal (brown), minimum bandwidth (orange), maximum peaking (green), minimum peaking (blue) and maximum bandwidth (navy blue) plots are added to the graph as they are calculated. Revision 1.0/September 2007 © Semtech Corp. The Evaluation Board PCB layout follows good practice for minimizing noise. Large area ground planes and supply decoupling are used. The analog and digital parts of the IC use separate ground and supply connections. The following guidelines should be considered when laying out a custom circuit board for the ACS8947T: 2. Power supply decoupling capacitors should be placed as close as possible to the pins of the IC to decouple all power connections to the device. 3. Ensure that for the differential inputs and outputs, both tracks in each pair of tracks are matched in length. 4. Ensure that for the differential inputs and outputs, both tracks in each pair of tracks are of 50 Ohm impedance. Page 13 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Bill of Materials Ref. FINAL Value EVALUATION BOARD Description PCB Qty. CAPACITORS C26, C27, C28, C32, C34, C36, C41, C43, C47, C49 100 pF 0603 Capacitor (SMD) 10 C11, C12, C13, C14, C15, C23, C25, C29, C33, C35, C37, C40, C42, C46, C48, C50, C51, C52, C53, C56, C57, C58, C59, C60 220 nF 0805 Capacitor (SMD) 24 C1, C2, C3, C4, C17, C18 220NF / 0R 0805 Capacitor / Zero Ohm Link (Link Selected) 6 C7, C8 Defined by Loop Filter Calculator 0805 ceramic capacitor 2 C5, C10 Defined by Loop Filter Calculator Footprint to accept all caps up to case C. 2 C16, C24 Defined by Loop Filter Calculator Case 'D' Polarized Capacitor (SMD) 2 C6, C9 Select on Test 0805 Capacitor (SMD) (Optional - Not Fitted) 0 PCON2 5mm Pitch Vertical Mount DC Connector 1 RF1, RF2, RF3, RF4, RF5, RF6, RF7, N/A RF11, RF12, RF13, RF14, RF17, RF18, RF19, RF20 5-Pin SMB - Straight (PTH) 15 SK2 CENTRONICS IEEE-488 connector 36 Way 90 degree PCB mount 1 SK3 SSMH_FPGA_MB_ CONN 10-Way Connector 0.1" Pitch 1 JMP1, JMP2, JMP3, JMP4, JMP5, JMP6, JMP7, JMP8, JMP9, JMP10, JMP11, JMP12 JUMPER3X3 3 x 3-Pin SIL Header (Qty x 3) 36 JMP16, JMP17, JMP19, JMP20 N/A 2-Pin SIL Header 0.1" Pitch 4 SW2, SW3, SW4, SW6, SW7 PUSH_BUT Push Button 5 R30, R31, R33 0R 0805 Resistor (SMD) 3 R29, R32 100R 0805 Resistor (SMD) 2 R4, R7, R10, R13, R15 68R 0805 Resistor (SMD) 5 R25, R26, R27, R28, R43, R44, R50, R51, R52, R53, R56, R57, R58, R59 82R 0805 Resistor (SMD) 14 RP1, RP2 100R Resistor Pack 16 Pin DIL 2 R61, R63, R65 120R 0805 Resistor (SMD) 3 CONNECTORS SK4 MISC. RESISTORS Revision 1.0/September 2007 © Semtech Corp. Page 14 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Ref. FINAL Value EVALUATION BOARD Description PCB Qty. R60, R62, R64, R68, R69, R70, R71, R74, R75, R76, R77 130R 0805 Resistor (SMD) 11 R3, R6, R9, R16, R17, R84, R85, R86 180R 0805 Resistor (SMD) 8 R1, R22, R23, R24, R42 1K 0805 Resistor (SMD) 5 R21 4K7 0805 Resistor (SMD) 1 R5, R8, R11, R14, R19, R20, R38, R39, R40, R41, R79, R80, R82, R83, R88 10K 0805 Resistor (SMD) 15 R18 39K 0805 Resistor (SMD) 1 R49 470K 0805 Resistor (SMD) 1 R55 560K 0805 Resistor (SMD) 1 R54, R89 1M 0805 Resistor (SMD) 1 D12 PHILIPS_BZV90C5 V6 PHILIPS_BZV90-C5V6 SOT223 1 IC2 LM258D Dual Op Amp 1 IC4 SC1566CM-3.3TR Semtech 3.3V 3A Regulator (TO-263-5) 1 U1 ACS8947TEVBPLD MAX 7000 E2PROM PLD,EPM7128STC100-15 1 SK1 ACS8947T ACS8947T QFN 7x7 48L 1 D1, D2, D3, D11 LED_TRICOL HP Tri-Color LED 4-pin surface mount HSMF-C655 4 D5, D6, D7, D9, D10 LED SMD 1206 LED 5 SEMICONDUCTORS Revision 1.0/September 2007 © Semtech Corp. Page 15 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING PCB Schematic FINAL EVALUATION BOARD Figure 7 EVB Software GUI 1 2 3 4 5 6 7 8 5V Supply Decoupling Caps 9 10 11 12 3.3V Supply Decoupling Caps VDD5V 100pF per 3.3V supply pin, plus 220nF per supply to be placed as close as possible to the supply pins. (100pF to be placed closest) TP23 VDD3V3 SC1566I5M-2.5TRT 4 5V (+-5%) C4 REF CLOCK 2 (POS) VDD5V VSS5V 1 220nF RF4 R18 39K 2 2 LK9 LINK 0603 1 1 1 1 1 1 A 2 1 TP18 TP19 GND5VGND5V 1 For LVPECL mode outputs, these resistors (R50-53, R56-59 & R68-71, R74-77) should only be fitted if it is necessary to terminate the clock output on this PCB. CML mode outputs may be terminated at both ends of the transmission line. 1 1 1 VSS3V 1 VSS5V 1 VDDP1 1 1 130R TP20 TP21 GND3VGND3V To terminate LVPECL mode outputs, populate R50-53 & R56-59 with 82R resistors and also populate R68-71 & R74-77 with 130R resistors. C For CML mode outputs, do not populate R50-53 & R56-59, and populate R68-71 & R74-77with 51R resistors. R63 VDDOP TP251 1 C40-49 are 100pF & 220nF supply decoulping to be placed as close as possible to the supply pins. (100pF to be placed closest) C OUT_VTERM 130R 1 LED PC CONTROL 2 1 DBP_VSS RATE1B RATE1A 47 48 RATE2A RATE2B 46 ACS8946_QFN_DUAL 2 TP16 VCN 1 TP13 1 VSSOSC 1 R33 0R VDDOSC 1 GND3V JMP19 1 OUTPUT 2 ENABLE 1 TP14 2 C47 100pF R82 1 VDDP2 RATE SELECTION VDD5V 1 JMP20 SW-DIP2 1 2 OUTPUT 1 ENABLE BSW-DIP2 1A 2 jumper_sigs[6] 4 3 1 C48 220nF SW11 VSS3V 2 1 R2 R1 10K R38 10K R39 10K R40 10K R41 7 RF7 220nF 2 1 C59 OUT1 (NEG) RF20 C 130R 220nF 3 1 1 SYNC_VTERM Normally fit optional resistors (R68-77) to local power, not TP. TP positions are for current measurement purposes. C 130R VSS3V C 130R VDDP2 1 B 2 10K VSS3V 1 2 3 4 5 8 7 7 D 3 R59 82R 5 8 7 7 8 8 9 RF19 OUT1 (POS) 220nF R77 Local Power D 6 6 4 5 5 R83 Normally fit optional resistors (R64-65) to local power, not TP. TP positions are for current measurement purposes. 9 6 5 6 6 C49 100pF Local Power 4 9 1 1 2 JMP2 JUMPER3X3 4 4 9 7 8 9 2 3 3 F 1 3 2 2 3 1 4 5 6 5 5 7 7 9 8 8 6 6 8 5 5 JMP4 JUMPER3X3 4 4 9 1 3 H 2 2 3 1 4 6 5 6 6 9 4 7 7 8 JMP6 JUMPER3X3 4 4 7 J 1 1 3 2 2 3 6 5 5 5 9 7 8 9 9 6 6 8 5 5 JMP8 JUMPER3X3 4 4 9 1 3 2 2 3 1 4 6 5 6 6 7 5 4 8 6 L 3 VSS5V JMP10 JUMPER3X3 C58 R58 82R R65 R2 R1 8 7 8 9 9 SYNC 1 (NEG) 4 130R C SYNC OUT RF5 R44 C18 82R VDD5V 4 R76 3 1 2 3 A 1 4 5 220nF R43 82R VDD VSS JMP12 JUMPER3X3 OUT2 (NEG) RF18 JMP1 JUMPER3X3 VSS3V D R64 RF6 SYNC 1 (POS) 5 7 7 8 9 9 1 VSS5V C17 6 JMP3 JUMPER3X3 2 TP17 4 6 4 5 6 5 5 2 C 3 1 1 2 6 6 7 9 8 9 4 4 JMP5 JUMPER3X3 8 5 5 2 3 3 E 1 3 2 2 3 1 4 6 5 6 6 7 9 8 9 4 4 JMP7 JUMPER3X3 8 5 5 7 1 2 3 G 1 4 6 5 6 6 7 7 9 9 4 4 JMP9 JUMPER3X3 8 5 5 7 4 6 5 6 6 2 3 I 1 1 2 3 4 4 7 9 8 7 8 9 2 3 5 JMP11 JUMPER3X3 8 4 6 5 6 5 8 1 2 3 K 1 2 3 4 6 C VSS3V C57 220nF 130R JUMPER-2 cfg_out[3] cfg_out[0] B 4 R57 82R C 3 4 3 2 SW10 1A 2 5 RF17 OUT2 (POS) 220nF VSS5V 68R R15 VSS5V 6 C56 R56 82R R75 Local Power 10K VSS3V Position test points TP13-TP16 on a 0.1" grid. R20 10K 130R C JUMPER-2 ACS8946EVBPLD TP5 RES75 R74 3 1 R32 33R 22uF C10 76 No Fit 2 2 RESERVED 77 3 74 79 78 VSS5V 4 R2 R1 2 3 2 5 3 C46 220nF 1 R2 R1 3 8 6 VDDO1 45 44 2 3 14 13 ALARM1_CO0 ALARM2_CO1 15 CFG_OUT2 17 18 19 20 21 22 23 16 ALARMC_CO3 LOCKB CFG_IN0 CFG_IN2 CFG_IN3 CFG_IN4 CFG_IN1 SYNCN SYNCP RESETB VSSOSC VDDP2 43 41 42 40 R31 0R IC1 2 VCN 39 3 36 OUT1N 38 3 R30 0R OUT1P VCP 2.2uF OUT3 (NEG) RF14 220nF 130R 4 1 80 3 VDDARF 37 81 35 1 2.2uF 2 82 TP15 VCP 1 1 1 83 R29 33R VSS3V C53 C 9 VDDO2 SYNC_OUT 34 3 No Fit 1 7 OUT2N AUTO_SEL R53 82R Local Power VSS3V 1 B 10 OUT2P ACS8946_QFN 49 33 22uF 2 84 VDDO3 VDDOSC C5 86 85 OUT3N CLK2N SEL_CLK2 87 VDDARF CFG_IN5 24 CFG_IN6 32 RESERVED 75 GND jumper_sigs[0] TDO 73 jumper_sigs[1] 71 72 jumper_sigs[2] 70 jumper_sigs[3] VCCIO jumper_sigs[5] jumper_sigs[6] jumper_sigs[4] 69 68 67 65 pp_scan_en 66 50 RF13 OUT3 (POS) 220nF 11 OUT3P VDDP1 CLK2P 88 C6 4 5 1 RESERVED 6 2 RESERVED 7 8 9 3 TDI cfg_inputs[5] cfg_inputs[4] 10 11 GND cfg_inputs[3] cfg_inputs[2] cfg_inputs[1] cfg_inputs[0] 15 13 14 16 12 RESERVED TMS cfg_outputs[3] cfg_outputs[2] cfg_outputs[1] cfg_outputs[0] 19 18 17 VCCIO RESERVED 24 cfg_inputs[9] C52 R52 82R R71 12 VDDO4 CLK1P 31 R80 10K VSS3V SK1 OUT4P OUT4N CLK1N 28 VDD5V C43 100pF 2 D10 R88 10K 20 cfg_inputs[8] VDD5V CENTRONICS RESERVED cfg_inputs[11] pp_scan_clk jumper_sigs[7] 49 64 48 jumper_sigs[8] 47 TCK 16 15 14 13 12 11 10 9 cfg_inputs[10] pp_scan_in 27 RES92 1 29 auto_sel pp_reset43b VDDADIV 30 GND jumper_sigs[12] 26 RES93 1 90 sel_clk2 VCCIO 1 CFG_IN7 VDDADIV 91 scan_mode VCCIO 1 RP2 2 100R 3 4 5 6 7 8 92 RES94 89 clk reset43b RES96 1 1 TP9 1 TP10 1 TP11 93 GND+ scan_clk_fb RES97 1 25 resetb RESERVED RES98 1 95 94 1 46 R1 1K 16 15 14 13 12 11 10 9 96 GND+ GND 44 45 1 RP1 2 100R 3 4 5 6 7 8 21 ref_sel_buts[3] 43 10K Push Button jumper_sigs[10] SW6 PUSH_BUT 1 2 1 2 Button & LED 1 TP6 1 TP7 1 TP8 97 1 R14 EXT FB SELECT 22 ref_sel_leds[3] jumper_sigs[9] VSS5V 23 alarm_leds[2] 41 42 98 VCCINT 130R C JUMPER-2 C42 220nF C7 40 68R R13 LED buffer_in[1] VCCINT 2 99 C8 39 D9 buffer_in[0] GND OUTPUT 3 ENABLE 100 C9 38 VDD RESERVED 51 C 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VCCIO ref_sel_buts[2] PUSH_BUT 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED GND 2 Push Button RESERVED 63 VSS ref_sel_leds[1] ref_sel_buts[1] 62 Button & LED GND ref_sel_leds[2] 37 10K RESERVED alarm_leds[1] 36 R11 2 RESERVED ACS8946EVBPLD 35 68R R10 LED RESERVED alarm_leds[0] (EPM7128STC100) 34 PUSH_BUT D7 SW4 1 1 1 JMP17 1 RESERVED 61 VSS 2 4 LED_TRICOL OUT4 (NEG) RF12 R70 1 ALARMC_CO3 ref_sel_buts[0] 60 2 2 Push Button R86 180R D3 G+ GR+ R- 33 VCCIO 1 180R 1 3 R8 10K TP26 1 U1 cfg_inputs[6] ref_sel_leds[0] jumper_sigs[11] R9 32 RESERVED SW3 1 1 LED_TRICOL VDD Tri-Colour LED 30 31 G+ GR+ R- Button & LED REF 2 SELECT TP1 1 RES30 R7 58 REF 1 SELECT REF 2 ALARM 29 1 59 Tri-Colour LED 28 R5 10K 68R LED 57 2 2 Push Button PUSH_BUT D6 RESERVED LED D5 SW2 1 1 VSS 2 4 56 2 4 R85 180R D2 data 180R 1 3 pc_ctrl_led R6 VSS3V C51 220nF 130R RES2 1 1 RES1 1 TP4 cfg_inputs[7] load VDD 1 TP3 VDD5V alarm_leds[3] mux_chain G+ GR+ R- LED_TRICOL Button & LED R51 82R C VSS3V 55 1 3 Tri-Colour LED REF 1 ALARM 68R R4 1 470K VDD5V RESERVED 25 27 D1 54 180R RF11 OUT4 (POS) 220nF VSS5V GND 52 R3 AUTO SELECT SK2 26 VSS C50 R50 82R R69 Local Power R49 53 SELECTED REF ALARM buffer_out[0] C60 220nF VSS5V R79 10K VSS3V 220nF buffer_out[1] 1M R84 180R C41 100pF R2 R1 C23 R21 4K7 R89 VDD C40 220nF R2 R1 GND 2IN+ R19 10K TP2 RES21 VDD5V 130R C JUMPER-2 Lock Filter 5 VSS5V B R68 R2 R1 2IN- LM258D R16 180R 2 6 R2 R1 1IN+ 4 OUTPUT 4 ENABLE 3 7 1IN- 2OUT 3 R2 R1 2 JMP16 1 R2 R1 R- R+ G- G+ 3 1 Lock Detect 4 2 LED_TRICOL D11 1 8 1OUT VCC These capacitors (C50-53, C56-59) should only be fitted if it is necessary to AC couple the clock output on this PCB. If they are not fitted, they should be replaced with zero ohm links. 130R IC2 LM258D 1 LK10 LINK 0603 TP24 GND 3 R17 180R R28 82R LK8 LINK 0603 2 R24 1K 2 VSS3V SSMH_FPGA_MB_CONN LK3 3 220nF R27 82R LK7 LINK 0603 LINK 0603 1 Anode LINK 0603 LK2 R62 R2 R1 REF CLOCK 2 (NEG) 9 7 3 5 1 GND TDI NC NC VIO TDO VCCTMS GNDTCK 1 R2 R1 10 8 6 4 2 C3 R23 1K LK5 LINK 0603 PCON2 GND RF3 R22 1K VDDOP 220nF C37 C24 100uF C 3 2 JTAG ISP SK3 MasterBlaster LK4 LINK 0603 R55 560K C16 100uF Local Power VDD5V VDDOSC 220nF C35 C36 100pF 2 Cathode Cathode Anode R61 1 1 1 220nF RF2 130R 1 R26 82R C2 VDDARF 220nF C33 C34 100pF C32 100pF R54 1M 4 ADJ 2 2 2 VSS3V REF CLOCK 1 (POS) R2 R1 A C 3 220nF R25 82R VDDADIV 220nF C29 D12 PHILIPS_BZV90C5V6 SK4 3 REF CLOCK 1 (NEG) EN Push Button VSS5V VDDP2 100pF C27 C28 100pF C26 100pF 2 2 GND REF_VTERM 3 1 C25 220nF 5 VO 1 2 1 R2 R1 C1 VIN RESET SW7 PUSH_BUT 1 2 1 2 TP12 1 R60 RF1 VDDP1 1 SC1566I5M_2.5TRT IC4 1 2 1 per side of MAX7000, plus 1 for LM258D. Placed as close to the ICs as possible. Normally fit optional resistors (R60-63) to local power, not TP. TP positions are for current measurement purposes. 2 LK1 2 C15 220nF 1 C14 220nF 2 C13 220nF 1 R42 1K C12 220nF LINK 0603 C11 220nF TITLE: ACS894x Evaluation Board DRAWING No. 1 SHEET:1 OF 1 FILE NAME: ACS894x_EVB_v02.SchDoc 1 2 3 4 5 6 7 8 9 10 11 DATE: 23/04/2007 14:21:47 12 Note: Evaluation Board schematic is generic for all JAM PLLs. Revision 1.0/September 2007 © Semtech Corp. Page 16 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Acronyms & Abbreviations BOM CML DC EPLD EVB FEC GbE GUI I/C I/O JAM PLL LED LVPECL MUX OP Osc PCB PFD PLL RC SMB FINAL EVALUATION BOARD Trademark Acknowledgements Bill of Materials Current Model Logic Direct Current Electrical Programmable Logic Device Evaluation Board Forward Error Correction Gigabit Ethernet Graphical User Interface Integrated Circuit Input/Output Jitter-Attenuating, Multiplying PLL Light Emitting Diode Low Voltage Positive Emitter Coupled Logic Multiplexer Output Oscillator Printed Circuit Board Phase and Frequency Detector Phase Locked Loop Resistor/Capacitor Sub-Miniature type B- a connector type for use in DC to 4 GHz range Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. Windows 95/98/NT4/ME/XP and 2000 are registered trademarks of Microsoft Corporation. Revision Status/History The Revision Status, as shown in the top center of the document, may be DRAFT, PRELIMINARY, or FINAL, and refers to the status of the Device (not the document), with the design cycle. DRAFT status is used when the design is being realized but is not yet physically available, and the document content reflects the intention of the design. The document is raised to PRELIMINARY status when initial prototype devices are physically available, and the document content more accurately represents the realization of the design. The document is only raised to FINAL status after the device has been fully characterized, and the datasheet content updated with measured, rather than simulated parameter values. This is a FINAL release (Revision 1.00) of the ACS8947T EVB document. Changes made for this document revision are given in Table 1, together with a brief summary of previous revisions. For specific changes between earlier revisions, refer (where available) to those earlier revisions. Always use the current version of the document. Table 1 Revision History Revision 1.00/September 2007 Reference All pages Description of changes FINAL draft. Notes Revision 1.0/September 2007 © Semtech Corp. Page 17 www.semtech.com ACS8947T JAM PLL ADVANCED COMMS & SENSING Ordering Information FINAL EVALUATION BOARD Table 2 Parts List Part Number ACS8947T EVB Description Evaluation Board (EVB) Kit including PCB and PC software Disclaimers Life support - This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications, and is not authorized or warranted for such use. Right to change - Changes may be made to this product without notice. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards - Operation of this device is subject to the user’s implementation and design practices. It is the responsibility of the user to ensure equipment using this device is compliant to any relevant standards. Contact Information Semtech Corporation Advanced Communications & Sensing Products E-mail: [email protected] [email protected] Internet: http://www.semtech.com USA 200 Flynn Road, Camarillo, CA 93012-8790. Tel: +1 805 498 2111 Fax: +1 805 498 3804 FAR EAST 12F, No. 89 Sec. 5, Nanking E. Road, Taipei, 105, TWN, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 EUROPE Semtech Ltd., Units 2 & 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN. Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601 ISO9001 CERTIFIED Revision 1.0/September 2007 © Semtech Corp. Page 18 www.semtech.com