SC1112EVB Evaluation Kit ECN# OKHD-4TCPSX; Rev.1a; 1/01 SC1112EVB TEL:805-498-2111 FAX:805-498-3804 DESCRIPTION FEATURES The SC1112 was designed for the latest high speed motherboards. It includes three low dropout regulator controllers. The controllers provide the power for the system AGTL bus Termination Voltage, Chipset, and clock circuitry. u Triple linear controllers u Selectable and Adjustable Output Voltages u LDOs track input voltage within 200mV(Function of the Mosfets used) until regulation u Integrated Charge Pump u Programmable Power Good delay Signal u Latched Over Current Protection (VTT) An adjustable controller with a 1.2V reference is available, while two selectable outputs are provided for the VTT (1.25V or 1.5V) and the AGP (1.5V or 3.3V). The SC1112 low dropout regulators are designed to track the 3.3V power supply as the VTTIN supply is cycled On and Off. ORDERING INFORMATION A latched short circuit protection is also available for the VTT output. Device SC1112EVB Other features include an integrated charge pump that provides adequate gate drives for the external Mosfets, and a capacitive programable delay for the power good signal. Board Type Temp. Range (TA) SMT-FR4 0° to 70°C Evaluation Kit Schematic +5VSTBY J1 +5VSTBY C1 10uF J2 GND +3.3V C3 0.1uF C4 0.1uF VTT POWER GOOD R1 1k J6 U1 1 2 C5 C6 + 330uF C7 0.1uF 22nF 3 R2 100k R3 4 100k 5 Q2 IRFR120N ADJ ADJ J11 6 ADJ 7 8 J13 ** RA ** ADJ = 1.2*(1+RA/RB) C12 + 330uF PWRGD VTTIN DELAY VTTGATE VTTSEL VTTSEN AGPSEL AGPGATE ADJGATE AGPSEN CAP- FC CAP+ 16 15 Q1 IRFR120N 14 VTT 13 12 C9 0.1uF 11 J17 + C19 330uF J8 VTT J9 VTT J10 GND J12 GND C10 9 1uF VTT SELECT Signal J14 C13 0.1uF AGP SELECT Signal C11 0.1uF C15 + C14 0.1uF 330uF Q3 IRFR120N RB GND + C8 330uF 10 ** J16 +3.3V J7 GND GND ADJSEN +3.3V J4 J5 GND SC1112CS 5VSTBY J15 GND + C2 + C18 330uF 330uF J3 * 1 1 JP1 2 2 * AGP JP2 * JP1 = OPEN, VTT = 1.5 V C17 0.1uF + C16 330uF J18 AGP J19 AGP * JP1 = SHORT, VTT = 1.25 V J20 GND * JP2 = OPEN, AGP = 3.3 V J21 GND * JP2 = SHORT, AGP = 1.5 V 1 © 2001 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 SC1112EVB Evaluation Kit ECN# OKHD-4TCPSX; Rev.1a; 1/01 SC1112EVB TEL:805-498-2111 FAX:805-498-3804 Start up +5VSTBY supply is used for powering the logic, Internal Reference, Internal Charge Pump, Oscillator, Linear Controllers, of the SC1112 Evaluation Board. Before appling the supply voltages, following steps can be performed by the user to analyse the SC1112 evaluation board: +5VSTBY input voltage ranging from 4.40V to 5.25V should be provided before applying the 3.3V (VTTIN). Voltage for +5VSTBY should be applied to J1(Positive), and J2(Negative). 1- Connect all supplies to above mentioned terminals. If possible minimize all stray inductance due to long wiring by using twisted wires or short wire connection from the power supply to the terminals. Voltage for the VTTIN ranging from 3.13V to 3.47V should be applied to J3/J4(Positive), and J5/J7(Negative). If the AGP output voltage will be set for a 3.3V operation, the VTTIN supply should be at least 500mV above the 3.3V input to achieve the 3.3V output at the AGP. 2- Connect all instruments (DVM, current meters, Loads, osciloscope probes, etc.). More accurate measurements can be achieved if all stray inductanes are minimized. 3- Configure the jumpers JP1, JP2: The output voltage(VTT) can be verified on J8/J9(Positive), and J10/J12(Negative). The AGP output voltage can verified on J18/J19(Positive), and J20/J21(Negative). The ADJ output voltage can be veified on J11/J13(Positive), and J16/J17(Negative). JP1=OPEN, VTT =1.50V JP1=SHORT, VTT =1.25V JP2=OPEN, AGP =3.30V JP2=SHORT, AGP =1.50V 4- Apply +5VSTBY supply voltage. An open collector Power Good flag for the VTT is provided on J6. 5- Apply the VTTIN (3.3V) supply Voltage. loads and analyse the board. Evaluation Kit Schematic +5VSTBY J1 +5VSTBY C1 10uF J2 GND +3.3V C3 0.1uF C4 0.1uF VTT POWER GOOD R1 1k J6 U1 1 2 C5 C6 + 330uF C7 0.1uF 22nF 3 R2 100k R3 4 100k 5 Q2 IRFR120N ADJ ADJ J11 6 ADJ 7 8 J13 ** RA C12 + ** ADJ = 1.2*(1+RA/RB) 330uF PWRGD VTTIN DELAY VTTGATE VTTSEL VTTSEN AGPSEL AGPGATE ADJGATE AGPSEN CAP- FC CAP+ 16 15 Q1 IRFR120N 14 VTT 13 12 C9 0.1uF 11 J17 + C19 330uF J8 VTT J9 VTT J10 GND J12 GND C10 9 1uF VTT SELECT Signal J14 C13 0.1uF AGP SELECT Signal C11 0.1uF C15 + C14 0.1uF 330uF Q3 IRFR120N RB GND + C8 330uF 10 ** J16 +3.3V J7 GND GND ADJSEN +3.3V J4 J5 GND SC1112CS 5VSTBY J15 GND + C2 + C18 330uF 330uF J3 * JP1 1 1 2 2 * AGP JP2 * JP1 = OPEN, VTT = 1.5 V C17 0.1uF + C16 330uF J18 AGP J19 AGP * JP1 = SHORT, VTT = 1.25 V J20 GND * JP2 = OPEN, AGP = 3.3 V J21 GND * JP2 = SHORT, AGP = 1.5 V 2 © 2001 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 SC1112EVB Evaluation Kit ECN# OKHD-4TCPSX; Rev.1a; 1/01 SC1112EVB TEL:805-498-2111 FAX:805-498-3804 Bill Of Materials SC1112 Evaluation board Revised: Thursday, January 04, 2001 SC1112EVB Revision: 1a Item Quantity Reference Part Foot print 1 1 C1 10uF SM/C_1206 2 8 C2,C6,C8,C12,C14,C16,C18, 330uF CPCYL/D.275/LS.100/.031 C19 3 8 C3,C4,C7,C9,C11,C13,C15, 0.1uF SM/C_0805 C17 4 1 C5 22nF SM/C_0805 5 1 C10 1uF SM/C_0805 6 2 JP1,JP2 TP2 VIA\2P 7 1 J1 +5VSTBY ED5052 8 9 J2,J5,J7,J10,J12,J16,J17, GND ED5052 J20,J21 9 2 J3,J4 +3.3V ED5052 10 1 J6 POWER GOOD ED5052 11 2 J8,J9 VTT ED5052 12 2 J11,J13 ADJ ED5052 13 1 J14 VTT SELECT Signal ED5052 14 1 J15 AGP SELECT Signal ED5052 15 2 J19,J18 AGP ED5052 16 3 Q1,Q2,Q3 IRFR120N DPAKFET 17 3 R1,RB,RA 1k SM/R_0805 18 2 R2,R3 100k SM/R_0805 19 1 U1 SC1112CS SO-16 Evaluation Kit Bill of Material 3 © 2001 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 SC1112EVB Evaluation Kit ECN# OKHD-4TCPSX; Rev.1a; 1/01 SC1112EVB TEL:805-498-2111 FAX:805-498-3804 Board Layout Assembly Top Board Layout Assembly Bottom Board Layout Top Board Layout Bottom 4 © 2001 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 SC1112EVB Evaluation Kit ECN# OKHD-4TCPSX; Rev.1a; 1/01 SC1112EVB TEL:805-498-2111 FAX:805-498-3804 SC1112EVB Evaluation Board Verification Test Sheet Date: Sales Order #: Component Date Code: Board Revision #: Board Serial #: Tested By: VTTIN(V) Iin_VTTIN(A) +5VSTBY(V) Iin_+5VSTBY(A) VTT(V) Io_VTT(A) AGP(V) Io_AGP(A) ADJ(V) Io_ADJ(A) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 5 5 5 0 1 2 2 2 2 2 2 2 0 0 0 1 2 0 0 1 2 0 0 0 0 0 1 2 1 2 5 © 2001 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320