SC1189 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C Parameter Conditions Min Typ Max Units 5 mA Linear Sections Quiescent Current LDOV = 12V Output Voltage LDO1 2.487 2.525 2.563 V Output Voltage LDO2 1.231 1.250 1.269 V Gain (AOL) Load Regulation LDOS (1,2) to GATE (1,2) 90 IO = 0 to 8A 0.3 % 0.3 % 1 1.5 kΩ 8.0 10 V 1.9 V 0.01 -200 1.0 -300 µA µA 20 40 60 % 1 5 60 ms 0.5 4 30 ms 80 300 750 kΩ Line Regulation Output Impedance VGATE = 6.5V LDOV Undervoltage Lockout 6.5 LDOEN Threshold 1.3 LDOEN Sink Current Overcurrent Trip Voltage LDOEN = 3.3V LDOEN = 0V % of Vo set point Power-up Output Short Circuit Immunity Output Short Circuit Glitch Immunity Gate Pulldown Impedance GATE (1,2) -AGND; VCC+BST=0V VOSENSE Impedance dB 10 kΩ Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) See Gate Resistor Selection recommendations. 2004 Semtech Corp. 3 www.semtech.com SC1189 POWER MANAGEMENT Pin Configuration Ordering Information TOP VIEW AGND 1 24 GATE2 GATE1 2 23 LDOV LDOS1 3 22 VID25MV LDOS2 4 21 VID0 VCC 5 20 VID1 PWRGD 6 19 VID2 LDOEN 7 18 VID3 CS- 8 17 VOSENSE CS+ 9 16 EN PGNDH 10 15 BSTH DH 11 14 BSTL PGNDL 12 13 DL Device (1) Package Linear Voltage Temp Range (T J) SC1189SWTR SO-24 1.25V/2.5V 0° to 125°C Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (24 Pin SOIC) Pin Descriptions Pin # Pin Name 1 AGND Small Signal Analog and Digital Ground Pin Function 2 GATE1 Gate Drive Output LDO1 3 LDOS1 Sense Input for LDO1 4 LDOS2 Sense Input for LDO2 5 VCC 6 PWRGD Power Good Output, pulls low if VCC_CORE is outside valid range 7 LDOEN LDO Supply Monitor. 8 CS- Input Voltage Current Sense Input (negative) 9 CS+ 10 PGNDH 11 DH 12 PGNDL 13 DL 14 BSTL Supply for Low Side Driver 15 BSTH Supply for High Side Driver 16 EN Logic low shuts down the converter, High or open for normal operation 17 Current Sense Input (positive) Power Ground for High Side Switch High Side Driver Output Power Ground for Low Side Switch Low Side Driver Output (1) VOSENSE Top end of internal feedback chain. Programming Input (MSB) 18 VID3 19 VID2 (1) Programming Input 20 VID1 (1) Programming Input 21 VID0 22 VID25MV 23 LDOV +12V for LDO section 24 GATE2 Gate Drive Output LDO2 (1) Programming Input (1) (1) Programming Input (LSB) Note: (1) All logic level inputs and outputs are open collector TTL compatible. 2004 Semtech Corp. 4 www.semtech.com SC1189 POWER MANAGEMENT Block Diagram VCC CS- CS+ EN CURRENT LIMIT REF VID3 VID2 VID1 VID0 - ERROR AMP D/A BSTH + 70mV LEVEL SHIFT AND HIGH SIDE DRIVE + - DH + VID25MV PGNDH VOSENSE R + Q OSCILLATOR - PWRGD SHOOT-THRU CONTROL S OPEN COLLECTORS BSTL + AGND SYNCHRONOUS MOSFET DRIVE LDOEN DL LDOS1 GATE1 2.5V FET CONTROLLER REF 1.25V FET CONTROLLER LDOV 2004 Semtech Corp. PGNDL GATE2 5 LDOS2 AGND www.semtech.com SC1189 POWER MANAGEMENT Applications Information - Output Voltage Table Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; = 0°C < Tj < 85°C VID Parameter Output Voltage Conditions (1) 25MV 3210 Min Typ Max Units 0 0100 1.034 1.050 1.066 V 1 0100 1.059 1.075 1.091 0 0011 1.084 1.100 1.117 IO = 2A in Application circuit 1 0011 1.108 1.125 1.142 0 0010 1.133 1.150 1.167 1 0010 1.157 1.175 1.193 0 0001 1.182 1.200 1.218 1 0001 1.207 1.225 1.243 0 0000 1.231 1.250 1.269 1 0000 1.256 1.275 1.294 0 1111 1.281 1.300 1.320 1 1111 1.305 1.325 1.345 0 1110 1.330 1.350 1.370 1 1110 1.354 1.375 1.396 0 1101 1.379 1.400 1.421 1 1101 1.404 1.425 1.446 0 1100 1.428 1.450 1.472 1 1100 1.453 1.475 1.497 0 1011 1.478 1.500 1.523 1 1011 1.502 1.525 1.548 0 1010 1.527 1.550 1.573 1 1010 1.551 1.575 1.599 0 1001 1.584 1.600 1.616 1 1001 1.609 1.625 1.641 0 1000 1.634 1.650 1.667 1 1000 1.658 1.675 1.692 0 0111 1.683 1.700 1.717 1 0111 1.708 1.725 1.742 0 0110 1.733 1.750 1.768 1 0110 1.757 1.775 1.793 0 0101 1.782 1.800 1.818 1 0101 1.798 1.825 1.852 Note 1: VID[3:0] correspond to legacy VRM8.4 voltage levels for 1.3V to 1.8V 2004 Semtech Corp. 6 www.semtech.com SC1189 POWER MANAGEMENT Layout Guidelines Careful attention to layout requirements are necessary for successful implementation of the SC1189 PWM controller. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency. 12V IN 5V 10 1 2 3 4 0.1uF 5 6 7 8 9 0.1uF 10 11 12 AGND GATE2 GATE1 LDOV LDOS1 VID0 LDOS2 VID1 VCC VID2 PWRGD LDOEN CS- VID3 VID25MV VOSENSE CS+ EN PGNDH BSTH DH BSTL PGNDL DL 24 23 2.32k 22 21 Q1 Cin + 1.00k 20 5mOhm Vout 19 L 18 + Q2 Cout 17 16 15 14 13 SC1189 3.3V Vo Lin1 Q3 Heavy lines indicate high current paths. + + Cout Lin1 Cin Lin Layout Diagram SC1189 Vo Lin2 Q4 + Cout Lin2 2004 Semtech Corp. 7 www.semtech.com SC1189 POWER MANAGEMENT Layout Guidelines (Cont.) 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1189 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. PGNDH and PGNDL should be returned to the ground plane close to the package. The AGND pin should be connected to the ground side of (one of) the output capacitor(s). If this is not possible, the AGND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 6) Vcc for the SC1189 should be supplied from the 5V supply through a 10Ω resistor, the Vcc pin should be decoupled directly to AGND by a 0.1µF ceramic capacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces running back to CS+ and CS- on the SC1189 should run parallel and close to each other. The 0.1µF capacitor should be mounted as close to the CS+ and CS- pins as possible. 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s). 5V Currents in Power Section + Vout + 2004 Semtech Corp. 8 www.semtech.com SC1189 POWER MANAGEMENT Component Selection S WIT CHING SECTION WITCHING OUTPUT CAP ACIT ORS - Selection begins with the most CAPA CITORS critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from: R ESR ≤ and 0% duty cycle capability, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from: Vt It Where Vt = Maximum transient voltage excursion It = Transient current step For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10mΩ. To meet this kind of ESR level, there are three available capacitor technologies. Each Cap. Technology C (µF) ESR (mΩ) Qty. Rqd. C (µF) Total ESR (mΩ) Low ESR Tantalum 330 60 6 2000 10 OS-CON 330 25 3 990 8.3 1500 44 5 7500 8.3 Low ESR Aluminum ILRIPPLE = Ripple current allowance will define the minimum permitted inductor value. PO WER FETS - The FETs are chosen based on several POWER criteria, with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as: PCOND = IO2 ⋅ RDS(on) ⋅ δ where The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. δ = duty cycle ≈ PSW = IO ⋅ VIN ⋅ 10 −2 or more generally, PSW = IO ⋅ VIN ⋅ ( t r + t f ) ⋅ fOSC 4 c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be: R ESR C ⋅ VA It where VA is the lesser of VO or (VIN − VO ) PRR = QRR ⋅ VIN ⋅ fOSC The calculated maximum inductor value assumes 100% 2004 Semtech Corp. VO VIN b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then: INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from: L≤ VIN 4 ⋅ L ⋅ fOSC To a first order approximation, it is convenient to only con- 9 www.semtech.com SC1189 POWER MANAGEMENT Component Selection (Cont.) sider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be: Using 1.5X Room temp RDS(ON) to allow for temperature rise. FET type RDS(on) (mΩ) PD (W) Package IRL34025 15 1.69 D2Pak IRL2203 10.5 1.19 D2Pak Si4410 20 2.26 S0-8 BO TT OM FET - Bottom FET losses are almost entirely due BOTT TTOM to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by: PCOND = IO2 ⋅ RDS( on) ⋅ (1 − δ) For the example above: FET type RDS(on) (mΩ) PD (W) Package IRL34025 15 1.33 D2Pak IRL2203 10.5 0.93 D2Pak Si4410 20 1.77 INPUT CAP ACIT ORS - since the RMS ripple current in the CAPA CITORS input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. GATE RESIS TOR SELECTION - The gate resistors for the RESIST top and bottom switching FETs limit the peak gate current and hence control the transition time. It is important to control the off time transition of the top FET, it should be fast to limit switching losses, but not so fast as to cause excessive phase node oscillation below ground as this can lead to current injection in the IC substrate and erratic behaviour or latchup. The actual value should be determined in the application, with the final layout and FETs. CURRENT SENSE, LIMIT OOP AND OFFSET LIMIT,, DR DROOP The converter is protected and it’s loadline shaped by the signals generated from the sense resistor and associated components. CURRENT LIMIT CIRCUIT V CS S0-8 Io RF RD Each of the package types has a characteristic thermal impedance. For the surface mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of 40oC/W for the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below: Temperature Rise (OC) FET type Top FET Bottom FET IRL34025 67.6 53.2 IRL2203 47.6 37.2 Si4410 180.8 141.6 It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. 2004 Semtech Corp. Vo RS INDUCTOR + Ra VOSENSE Rb Rc DROOP AND OFFSET CIRCUIT Rload Current Limit, Droop and Offset circuit Current Limit is given by IOLIM = VCS.(RD+RF)/(RS.RF) At no load the output voltage is given by: VO=VO(nom)*(1+(Ra.Rb)/(Rc*(Ra+Rb)) so the offset is: VOS=VO(nom)*1000*(Ra.Rb)/(Rc*(Ra+Rb)) and the droop is calculated as: VD=Io*RS*Rb/(Ra+Rb) where RS is in mΩ, VOS and VD in mV For a full design procedure for droop and offset, see Application Note AN97-9, “Using Droop and Vout Offset for improved transient response”. 10 www.semtech.com SC1189 POWER MANAGEMENT FOLDBACK CURRENT LIMITING The SC1189 implements a “Hard Current Limit” overcurrent protection for the switching supply output. In a short circuit condition, this will lead to higher than normal power dissipation in the bottom side FETs. If this is problematic, foldback current limiting can be easily and inexpensively implemented to drastically reduce dissipation during output short circuit RA RB = RC V + VCS + VF = B (R A + R C ) VIN where VF = Forward Voltage drop of diode (≈ 0.6V) VCS To CS- D1 1N4148 RD L1 RF RS VO Output Current Path Foldback current limit components 1 Breakpoint VB 0 0 IOS M ⋅ VB ⋅ R D ⋅ R F (M − 1)VCS (R D + R F ) 4) Calculate the ratio of the input divider To CS+ RC IOLIM IOS 3) Choose VB and calculate RB RB VIN VOUT M= IOLIM 1 Foldback current limit characteristics For a complete design procedure for foldback current limiting see Application Note AN01-2, “Foldback Current Limit”. An abbreviated procedure is given below. 1) Choose values for IOLIM and RS and calculate the ratio Choose RC<RB/10 and calculate RA SHOR T CIR CUIT PR OTECTION - LINEARS SHORT CIRCUIT PRO The Short circuit feature on the linear controllers is implemented by using the Rds(on) of the FETs. As output current increases, the regulation loop maintains the output voltage by turning the FET on more and more. Eventually, as the Rds(on) limit is reached, the FET will be unably to turn on more fully, and output voltage will start to fall. When the output voltage falls to approximately 50% of nominal, the LDO controller is latched off, setting output voltage to 0. Power must be cycled to reset the latch. To prevent false latching due to capacitor inrush currents or low supply rails, the current limit latch is initially disabled. It is enabled at a preset time (nominally 2mS) after both the LDOV and LDOEN rails rise above their lockout points. To be most effective, the linear FET Rds(on) should not be selected artificially low, the FET should be chosen so that, at maximum required current, it is almost fully turned on. If, for example, a linear supply of 1.5V at 4A is required from a 3.3V ± 5% rail, max allowable Rds(on) would be. Rds(on)max = (0.95*3.3-1.5)/4 » 400mΩ To allow for temperature effects 200mΩ would be a suitable room temperature maximum, allowing a peak short circuit current of approximately 15A for a short time before shutdown. RF VCS = RD + RF IOLIM ⋅ R S If this ratio > 1, the value of RS or IOLIM must be increased. Then let RF=1kW and calculate RD. 2) Choose a short circuit current (IOS) and calculate M, do not be too agressive with M, a value between 2 and 3 should be sufficient. Choosing too low a value for IOS will result in a high value for M and may cause startup problems due to insufficient current. 2004 Semtech Corp. 11 www.semtech.com SC1189 POWER MANAGEMENT Theory of Operation (Linear OCP) The Linear controllers in the SC1189 have built in Overcurrent Protection (OCP). An overcurrent is assumed to have occured when the external FET is turned fully on and the output currrent is RDS(ON) limited, this is detected by the gate voltage going very high while the output voltage is below approximately 40% of it’s setpoint. To allow for capacitor charging and very short overcurrent durations, the gate voltage is ramped very slowly upwards whenever the output voltage is below the OCP threshold. To guarantee that the LDO output voltage is capable of reaching it’s setpoint, the gate drive is disabled until both LDOV Undervoltage Lockout (UVLO) and LDOEN Threshold values are exceeded, ensuring that there is sufficient gate drive capability and sufficient LDO input voltage capability. A block diagram of one LDO controller is shown below. 12V 3.3V LDOV LDOEN Gate 1.4V/us Vout 1V/ms Vout/2 Time Startup with no short circuit If at some later time, a short circuit is applied to the output, the GATEx voltage will ramp up quickly as Vout falls to try and maintain regulation. Once Vout has fallen to the OCP threshold, switch S1 will open and the gate will continue ramping at the 1V/ms rate. If the short is not removed before the GATEx output reaches approximately LDOV - 0.7V, the GATEx pin will be latched low, disabling the LDO + - 10pF C RAMP Short applied LDOV - gm LDOV-0.7V 1V/ms GATEx + Gate + VREF 1.3V R2 LDOSx Vout 1.26V SWITCH CLOSED ON LOW R - S1 Vout + Vout/2 + 10nA R R1 Time 14uA AGND Short circuit after startup RESET BY LDOV LOW S Q + - R LDOV-0.7V If the LDO tries to start into a short, the gate ramps at the 1V/ms rate to LDOV - 0.7V, where the GATEx pin will be latched low. During a normal start-up, once LDOV and LDOEN have reached their thresholds, the GATEx pin is released and CRAMP is charged by 10nA causing the GATEx voltage to ramp at 10nA/10pF = 1V/ms. Once the GATEx output has ramped to the external FET threshold, Vout starts to ramp up, following GATEx. When Vout reaches the OCP threshold, approximately 40% of setpoint, switch S1 is closed and GATEx ramps up at a much faster rate, followed by Vout, until Vout reaches setpoint and the loop settles into steady state regulation. 2004 Semtech Corp. LDOV-0.7V Gate 1V/ms Time Startup into short circuit 12 www.semtech.com SC1189 POWER MANAGEMENT Typical Characteristics Typical Ripple, Vo=1.75V, Io=10A Typical Efficiency (Switching section) 100% PIN Descriptions Efficiency 90% 1.75V 80% 1.50V Vo=1.25V 70% 0 5 10 15 20 Output Current (A) 25 30 Transient Response Vo=1.75V, Io=0A to 28A 2004 Semtech Corp. 2.5V Linear Short circuit output response 13 www.semtech.com J2 2004 Semtech Corp. 14 + C14 330uF + + + + + C38 C41 330uF 0.1uF J30 C42 0.1uF IRFR120N Q9 C34 + 330uF R28 4.99k + CS- CS+ C5 PWRGD DELAY AGPSEL VTTSEL ADJSEN ADJGATE + FC CAP- CAP+ AGPSEN AGPGATE VTTSEN VTTGATE VTTIN R24 1k Q3 IRL2203 R9 2R2 8 C33 0.1uF 10 9 11 12 13 14 15 Q1 IRL3103S R6 2R2 VTT = 1.5 V VTT = 1.25 V AGP=3.3V AGP=1.5V SC1112CS GND C26 47uF 0.1uF 5VSTBY U2 3 2 6 12 10 13 14 11 15 17 8 9 VTTSEL = 1, VTTSEL = 0, AGPSEL = 1, AGPSEL = 0, 22nF C43 16 3 5 4 7 6 2 1 5VSTBY LDOS1 GATE1 PWRGD PGNDL PGNDH DL BSTL DH BSTH VOSENSE C19 1500uF R26 100k SC1189CS LDOS2 GATE2 LDOV AGND EN VID4 VID3 VID2 VID1 VID0 J32 J33 AGPSEL VTTSEL R29 10k + LDOEN VCC U1 C18 1500uF R25 100k 4 24 3.3V STBY 1.8V STBY R27 1.00k R23 442 IRLR024N J27 CHIPSET C15 + Q5 330uF 1.8V 330uF + C12 3.3V STBY J13 CHIPSET 330uF C35 C36 C37 C39 C40 330uF 330uF 330uF 0.1uF 0.1uF 10uF 0.1uF 1 5VSTBY 23 16 EN S2 18 VID3 C29 19 C28 20 7 5 VID2 C4 0.1uF VID1 EMPTY R3 10 21 ON/OFF + R1 1N4148 D2 22 C11 + C3 1500uF C2 1500uF 5V 12V VID25MV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VID0 ATX M/B MOLEX 39-29-9202 3.3V 3.3V COM 5V COM 5V COM PWR_OK 5VSB 12V 3.3V -12V COM PS_ON COM COM COM -5V 5V 5V 1uF C45 Q10 IRFR120N Q8 IRFR120N Q4 IRL2203 R10 2R2 C27 OPEN 2.5V 1.2uH 0.1uF C46 + C44 330uF AGP 330uF 0.1uF + C32 330uF 5V R12 1k R15 See Table 2 J31 J29 1.5V/3.3V AGP (2X/4X) J28 J26 1.25V/1.5V VTT J24 J14 Clock C9 + + C7 + DROOP mV/A 0 1 2 5 1 2 5 1 2 5 VID 3210 0100 0100 0011 0011 0010 0010 0001 0001 0000 0000 1111 1111 1110 1110 1101 1101 VOUT VID 25MV 1.050 0 1.075 1 1.100 0 1.125 1 1.150 0 1.175 1 1.200 0 1.225 1 1.250 0 1.275 1 1.300 0 1.325 1 1.350 0 1.375 1 1.400 0 1.425 1 VID 3210 1100 1100 1011 1011 1010 1010 1001 1001 1000 1000 0111 0111 0110 0110 0101 0101 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 VOUT J18 SCOPE TP CON4 1 2 3 4 J17 R15 (Ohm) EMPTY 5.0 2.5 2.0 12.5 6.3 5 25.0 12.5 10.0 1500uF 1500uF 1500uF 1500uF C23 + C21 + C10 0.1uF C20 + C22 + R11 (Ohm) 0 3.3 10 EMPTY 8.3 25 EMPTY 16.7 50 EMPTY VCC_CORE OFFSET mV/V 0 2 2 2 5 5 5 10 10 10 TABLE VALID FOR 2x5mOhm SENSE RESISTOR 1500uF 1500uF 1500uF 1500uF + C6 VID 25MV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C8 R11 See Table 2 R8 5mOhm J15 VCC_CORE PWRGD + C30 VTT R5 OPEN R19 5mOhm R4 1.00k R21 18k R2 10k C16 C17 330uF + 330uF + L1 1N4148 D1 C31 Q6 IRLR024N R22 390 Q2 IRL3103S R7 2R2 C1 0.1uF R20 1k SC1189 POWER MANAGEMENT Typical Application Circuit www.semtech.com SC1189 POWER MANAGEMENT Evaluation Board Bill of Materials Item Qty. Reference Value 1 12 C1, C4, C5, C10, C28, C31, C33, C39, C40, C41, C42, C46 0.1uF 2 12 C2, C3, C6, C7, C8, C9, C18, C19, C20, C21, C22, C23 1500uF 3 14 C11, C12, C14, C15, C16, C17, C30, C32, C34, C35, C36, C37, C38, C44 330uF 4 1 C26 47uF 6 1 C29 10uF 7 1 C43 22nF 8 1 C45 1uF 9 2 D1, D2 1N4148 10 1 J2 ATX M/B MOLEX 39-29-9202 6 1 L1 1.2uH Panasonic PCC-S1 7 2 Q1, Q2 IRLR3103S 8 2 Q3, Q4 IRL2203 9 2 Q5, Q6 IRLR024N 25 3 Q8,Q9,Q10 IRFR120N 10 1 R1 10 11 2 R2, R29 10k 29 2 R4, R27 1.00k 13 4 R6, R7, R9, R10 2R2 14 2 R8, R19 5mOhm 15 2 R11, R15 See Table 12 3 R12, R20, R24 1k 16 1 R21 18k 17 1 R22 390 36 1 R23 442 37 2 R26, R25 100k 38 1 R28 4.99k 18 1 U1 SC1189CS SEMTECH 41 1 U2 SC1112CS SEMTECH 2004 Semtech Corp. 15 Notes Low ESR Sanyo MV-GX or equivalent IRC OAR1 www.semtech.com SC1189 POWER MANAGEMENT Outline Drawing - SO-24 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012-8790 Phone: (805)498-2111 FAX (805)498-3804 2004 Semtech Corp. 16 www.semtech.com