74LV153 Dual 4-input multiplexer Rev. 5 — 12 December 2011 Product data sheet 1. General description The 74LV153 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC153 and 74HCT153. The 74LV153 provides a dual 4-input multiplexer which selects 2 bits of data from up to four sources selected by common data select inputs (S0, S1). The two 4-input multiplexer circuits have individual active LOW output enable inputs (1E, 2E) which can be used to strobe the outputs independently. The outputs (1Y, 2Y) are forced LOW when the corresponding output enable inputs are HIGH. The 74LV153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch, is determined by the logic levels applied to S0 and S1. The logic equations for the outputs are: 1Y = 1E (1I0 S1 S0 + 1I1 S1 S0 + 1I2 S1 S0 + 1I3 S1 S0) 2Y = 2E (2I0 S1 S0 + 2I1 S1 S0 + 2I2 S1 S0 + 2I3 S1 S0) The 74LV153 can be used to move data to a common output bus from a group of registers. The state of the select inputs would determine the particular register from which the data came. An alternative application is a function generator. The device can generate two functions or three variables. This is useful for implementing highly irregular random logic. 2. Features and benefits Wide operating voltage: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 C Non-inverting outputs Separate enable input for each output Common select inputs Permits multiplexing from n lines to 1 line Enable line provided for cascading (n lines to 1 line) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 74LV153 NXP Semiconductors Dual 4-input multiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV153N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74LV153D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV153DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LV153PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 4. Functional diagram 1 6 5 4 3 6 5 4 3 10 11 12 14 13 2 14 Fig 1. 1I0 1I1 1I2 1I3 2I0 2I1 2I2 2I3 S0 10 2 S1 11 1 1E 12 15 2E 13 Logic symbol 74LV153 Product data sheet 1Y 2Y 7 9 2E 1I0 1I1 1I2 1Y MUX 7 1I3 S0 S1 2I0 2I1 2I2 2Y MUX 9 2I3 2E 15 001aal843 Fig 2. 001aal844 Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 2 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 1E 1I3 1I2 1I1 1I0 S0 S1 2I3 2I2 1Y Fig 3. 2I1 2Y 2I0 2E 001aal845 Logic diagram 5. Pinning information 5.1 Pinning 74LV153 1E 1 16 VCC S1 2 15 2E 1I3 3 14 S0 1I2 4 13 2I3 74LV153 1E 1 16 VCC S1 2 15 2E 1l3 3 14 S0 1I1 5 12 2I2 1l2 4 13 2l3 1I0 6 11 2I1 1l1 5 12 2l2 1l0 6 11 2l1 1Y 7 10 2l0 GND 8 1Y 7 GND 8 10 2I0 9 2Y Pin configuration DIP16, SO16 74LV153 Product data sheet 2Y 001aal847 001aal846 Fig 4. 9 Fig 5. Pin configuration (T)SSOP16 All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 3 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 5.2 Pin description Table 2. Pin description Symbol Pin Description 1E, 2E 1, 15 output enable inputs (active LOW) S0, S1 14, 2 data select inputs 1I0, 1I1, 1I2, 1I3 6, 5, 4, 3 data inputs source 1 1Y 7 multiplexer output source 1 GND 8 ground (0 V) 2Y 9 multiplexer output source 2 2I0, 2I1, 2I2, 2I3 10, 11, 12, 13 data inputs source 2 VCC 16 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. select Inputs data inputs output enable output S0 S1 nI0 nI1 nI2 nI3 nE nY X X X X X X H L L L L X X X L L L L H X X X L H H L X L X X L L H L X H X X L H L H X X L X L L L H X X H X L H H H X X X L L L H H X X X H L H 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current VO = 0.5 V to (VCC + 0.5 V) ICC IIK Min Max Unit 0.5 +4.6 V - 20 mA - 50 mA - 25 mA supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 4 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Ptot total power dissipation Tamb = 40 C to +125 C Min Max Unit DIP16 package [2] - 750 mW SO16 package [3] - 500 mW (T)SSOP16 package [4] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 C. [3] Ptot derates linearly with 8 mW/K above 70 C. [4] Ptot derates linearly with 5.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI VO Conditions Min Typ Max Unit 1.0 3.3 3.6 V input voltage 0 - VCC V output voltage 0 - VCC V [1] Tamb ambient temperature t/V input transition rise and fall rate [1] 40 +25 +125 C VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 5 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V lO = 100 A; VCC = 1.2 V - 1.2 - - - V lO = 100 A; VCC = 2.0 V 1.8 2.0 - 1.8 - V lO = 100 A; VCC = 2.7 V 2.5 2.7 - 2.5 - V lO = 100 A; VCC = 3.0 V 2.8 3.0 - 2.8 - V lO = 6 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V IO = 100 A; VCC = 1.2 V - 0 - - - V IO = 100 A; VCC = 2.0 V - 0 0.2 - 0.2 V IO = 100 A; VCC = 2.7 V - 0 0.2 - 0.2 V VI = VIH or VIL VI = VIH or VIL IO = 100 A; VCC = 3.0 V - 0 0.2 - 0.2 V IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V II input leakage current VI = VCC or GND; VCC = 3.6 V - - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - - 20.0 - 160 A ICC additional supply current per input; VI = VCC 0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 A CI input capacitance - 3.5 - - - pF [1] Typical values are measured at Tamb = 25 C. 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 6 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 8. Symbol Parameter propagation delay tpd 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V - 85 - - - ns VCC = 2.0 V - 29 56 - 66 ns VCC = 2.7 V - 21 41 - 49 ns VCC = 3.3 V; CL = 15 pF - 14 - - - ns - 16 33 - 39 ns VCC = 1.2 V - 90 - - - ns VCC = 2.0 V - 31 58 - 70 ns VCC = 2.7 V - 23 43 - 51 ns - 14 - - - ns - 17 34 - 41 ns VCC = 1.2 V - 60 - - - ns VCC = 2.0 V - 20 39 - 46 ns VCC = 2.7 V - 15 29 - 34 ns VCC = 3.3 V; CL = 15 pF - 10 - - - ns VCC = 3.0 V to 3.6 V [3] - 11 23 - 27 ns CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] - 30 - - - pF 1In to 1Y and 2In to 2Y; see Figure 6 VCC = 3.0 V to 3.6 V [2] [3] Sn to nY; see Figure 6 VCC = 3.3 V; CL = 15 pF VCC = 3.0 V to 3.6 V [3] nE to nY; see Figure 6 power dissipation capacitance CPD [1] All typical values are measured at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL. [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V) unless otherwise stated. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching (CL VCC2 fo) = sum of the outputs. 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 7 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 11. Waveforms VI VM 1In, 2In input GND tPHL tPLH VOH VM nY output VOL 001aal848 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The input (1In, 2In) to output (1Y, 2Y) propagation delays VI VM Sn, nE input GND tPHL tPLH VOH VM nY output VOL 001aal849 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. The input (Sn, nE) to output (nY) propagation delays Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 8 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer VCC PULSE GENERATOR VI VO DUT RT CL 50 pF RL 1 kΩ 001aaa663 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 8. Table 9. Test circuit for measuring switching times Test data Supply voltage Input VCC VI tr, tf < 2.7 V VCC 2.5 ns 2.7 V to 3.6 V 2.7 V 2.5 ns 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 9 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 9. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 10 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 11 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT338-1 (SSOP16) 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 12 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 12. Package outline SOT403-1 (TSSOP16) 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 13 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV153 v.5 20111212 Product data sheet - 74LV153 v.4 Modifications: • Legal pages updated. 74LV153 v.4 20100429 Product data sheet - 74LV153 v.3 74LV153 v.3 19980428 Product specification - 74LV153 v.2 74LV153 v.2 19970515 Product specification - - 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 14 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 15 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LV153 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 12 December 2011 © NXP B.V. 2011. All rights reserved. 16 of 17 74LV153 NXP Semiconductors Dual 4-input multiplexer 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 December 2011 Document identifier: 74LV153