74HC00; 74HCT00 Quad 2-input NAND gate Rev. 6 — 14 December 2011 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC00; 74HCT00 provides a quad 2-input NAND function. 2. Features and benefits Input levels: For 74HC00: CMOS level For 74HCT00: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number 74HC00N Package Temperature range Name Description Version 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm 74HCT00N 74HC00D 74HCT00D 74HC00DB 74HCT00DB 74HC00PW 74HCT00PW 74HC00BQ 74HCT00BQ 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 4. Functional diagram 1 1 1A 2 1B 1Y 3 4 2A 5 2B 2Y 6 9 3A 10 3B 3Y 8 12 4A 13 4B 4Y 11 2 4 5 9 10 12 13 & 3 & 6 & 8 A Y 11 & B mna212 Fig 1. mna211 mna246 Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74HC00 74HCT00 1 1A terminal 1 index area 2 13 4B 2 13 4B 1Y 3 12 4A 4 11 4Y 1Y 3 12 4A 2A 2A 4 11 4Y 2B 5 2B 5 10 3B 2Y 6 2Y 6 9 3A 8 1B 1B GND 7 8 3Y 3Y 14 VCC 7 1 GND 1A 14 VCC 74HC00 74HCT00 GND(1) 10 3B 9 3A 001aal324 Transparent top view 001aal323 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 2 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate Table 2. Pin description …continued Symbol Pin Description 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nY L X H X L H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C DIP14 package - 750 mW SO14, (T)SSOP14 and DHVQFN14 packages - 500 mW [2] Min Max Unit 0.5 +7 V [1] - 20 mA [1] - 20 mA [2] total power dissipation Ptot [1] Conditions The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 3 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC00 Min 74HCT00 Typ Max Min Unit Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max 74HC00 VIH VIL VOH VOL HIGH-level input voltage VCC = 2.0 V - 1.2 - 1.5 - 1.5 - V VCC = 4.5 V - 2.4 - 3.15 - 3.15 - V VCC = 6.0 V - 3.2 - 4.2 - 4.2 - V LOW-level input voltage VCC = 2.0 V - 0.8 - - 0.5 - 0.5 V VCC = 4.5 V - 2.1 - - 1.35 - 1.35 V VCC = 6.0 V - 2.8 - - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V - 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V - 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V - 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V - 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V - 5.81 - 5.34 - 5.2 - V HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 0 - - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 - - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 - - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 - - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 - - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - - - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - - - 20 - 40 A 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 4 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min CI input capacitance 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT00 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V - 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 - - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 4.5 - 4.4 - 4.4 - V IO = 4.0 mA - 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 - - 0.1 - 0.1 V IO = 5.2 mA; VCC = 6.0 V - 0.15 - - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 6.0 V - - - - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - - - 20 - 40 A ICC additional supply current per input pin; VI = VCC 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V 150 - - 675 - 735 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 25 - 115 135 74HC00 tpd propagation delay nA, nB to nY; see Figure 6 [1] VCC = 2.0 V VCC = 4.5 V - 9 - 23 27 ns VCC = 5.0 V; CL = 15 pF - 7 - - - ns - 7 - 20 23 ns VCC = 6.0 V tt transition time 74HC_HCT00 Product data sheet ns see Figure 6 [2] VCC = 2.0 V - 19 - 95 110 ns VCC = 4.5 V - 7 - 19 22 ns VCC = 6.0 V - 6 - 16 19 ns All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 5 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate Table 7. Dynamic characteristics …continued GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter CPD 25 C Conditions power dissipation capacitance [3] per package; VI = GND to VCC 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 22 - - - pF 74HCT00 [1] propagation delay nA, nB to nY; see Figure 6 tpd transition time tt power dissipation capacitance CPD VCC = 4.5 V - 12 - 24 29 ns VCC = 5.0 V; CL = 15 pF - 10 - - - ns VCC = 4.5 V; see Figure 6 [2] - - - 29 22 ns per package; VI = GND to VCC 1.5 V [3] - 22 - - - pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 11. Waveforms VI nA, nB input VM GND tPHL VOH tPLH VY VM VX nY output VOL tTHL tTLH 001aai814 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. Input to output propagation delays Measurement points Type Input Output VM VM VX VY 74HC00 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT00 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 6 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Table 9. Load circuitry for measuring switching times Test data Type Input Load Test VI tr, tf CL 74HC00 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT00 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 7 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 8 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 9 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT337-1 (SSOP14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 10 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 11. Package outline SOT402-1 (TSSOP14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 11 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 12 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT00 v.6 20111214 Product data sheet - 74HC_HCT00 v.5 - 74HC_HCT00 v.4 Modifications: 74HC_HCT00 v.5 • Legal pages updated. 20101125 Product data sheet 74HC_HCT00 v.4 20100111 Product data sheet - 74HC_HCT00 v.3 74HC_HCT00 v.3 20030630 Product data sheet - 74HC_HCT00_CNV v.2 Product specification - - 74HC_HCT00_CNV v.2 19970826 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 13 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from competent authorities. 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 14 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 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Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 15 of 16 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 December 2011 Document identifier: 74HC_HCT00