74CBTLV3125 4-bit bus switch Rev. 3 — 15 December 2011 Product data sheet 1. General description The 74CBTLV3125 provides a 4-bit high-speed bus switch with separate output enable inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable (nOE) input is HIGH. To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V Standard ’125’-type pinout High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 74CBTLV3125 NXP Semiconductors 4-bit bus switch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV3125DS 40 C to +125 C SSOP16[1] plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm SOT519-1 74CBTLV3125PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74CBTLV3125BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm [1] SOT762-1 Also known as QSOP16. 4. Functional diagram 1OE 1A 1B 2OE 2A 2B 3OE 3A 3B nA nB 4OE 4A 4B nOE 001aak856 Fig 1. Logic symbol 74CBTLV3125 Product data sheet Fig 2. 001aak863 Logic diagram (one switch) All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 2 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 5. Pinning information 5.1 Pinning terminal 1 index area 1 74CBTLV3125 2 15 4OE 1A 3 1B 1OE 1 14 4A 1A 2 14 VCC 13 4OE 4 13 4B 1B 3 12 4A 2OE 5 12 3OE 2OE 4 11 4B 2A 6 11 3A 2A 5 10 3OE 2B 7 10 3B 2B 6 9 3A GND 8 GND 7 8 3B 9 n.c. 001aak857 1A 2 13 4OE 1B 3 12 4A 2OE 4 2A 5 2B 6 11 4B GND(1) 10 3OE 9 8 1OE 3B 16 VCC 7 1 GND 74CBTLV3125 n.c. 14 VCC 1OE 74CBTLV3125 3A 001aak859 Transparent top view 001aak858 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration SOT519-1 (SSOP16) Fig 4. Pin configuration SOT402-1 (TSSOP14) Fig 5. Pin configuration SOT762-1 (DHVQFN14) 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE, 3OE, 4OE Description SOT519-1 SOT402-1 and SOT762-1 2, 5, 12, 15 1, 4, 10, 13 output enable input 1A, 2A, 3A, 4A, 3, 6, 11, 14 2, 5, 9, 12 A input/output 1B, 2B, 3B, 4B 4, 7, 10, 13 3, 6, 8, 11 B output/input GND 8 7 ground (0 V) VCC 16 14 positive supply voltage n.c. 1, 9 - not connected 6. Functional description Table 3. Function table[1] Output enable input OE Function switch L ON-state H OFF-state [1] H = HIGH voltage level; L = LOW voltage level. 74CBTLV3125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 3 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage Min Max Unit 0.5 +4.6 V 0.5 +4.6 V 0.5 VCC + 0.5 V VI input voltage control inputs [1] VSW switch voltage enable and disable mode [2] IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current VI < 0.5 V 50 - mA ISW switch current VSW = 0 V to VCC - 128 mA ICC supply current - +100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot Tamb = 40 C to +125 C [3] [1] The minimum input voltage rating may be exceeded if the input clamping current ratings are observed. [2] The switch voltage ratings may be exceeded if switch clamping current ratings are observed [3] For SSOP16 and TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions VI input voltage VSW switch voltage Tamb ambient temperature t/V input transition rise and fall rate Min Max Unit 2.3 3.6 V control inputs 0 3.6 V enable and disable mode 0 VCC V 40 +125 C 0 200 ns/V pin nOE; VCC = 2.3 V to 3.6 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 3.0 V to 3.6 V 2.0 - - 2.0 - V LOW-level input VCC = 2.3 V to 2.7 V voltage VCC = 3.0 V to 3.6 V - - 0.7 - 0.7 V - - 0.9 - 0.9 V II input leakage current - - 1.0 - 20 A IS(OFF) OFF-state VCC = 3.6 V; see Figure 6 leakage current - - 1 - 20 A VIH VIL HIGH-level input voltage 74CBTLV3125 Product data sheet pin nOE; VI = GND to VCC; VCC = 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 4 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch Table 6. Static characteristics …continued At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max IS(ON) ON-state VCC = 3.6 V; see Figure 7 leakage current - - 1 - 20 A IOFF power-off VI or VO = 0 V to 3.6 V; leakage current VCC = 0 V - - 10 - 50 A ICC supply current VI = GND or VCC; IO = 0 A; VSW = GND or VCC; VCC = 3.6 V - - 10 - 50 A ICC additional supply current pin nOE; VI = VCC 0.6 V; VSW = GND or VCC; VCC = 3.6 V - - 300 - 2000 A CI input capacitance pin nOE; VCC = 3.3 V; VI = 0 V to 3.3 V - 0.9 - - - pF CS(OFF) OFF-state capacitance VCC = 3.3 V; VI = 0 V to 3.3 V - 5.2 - - - pF CS(ON) ON-state capacitance VCC = 3.3 V; VI = 0 V to 3.3 V - 14.3 - - - pF [1] All typical values are measured at Tamb = 25 C. [2] One input at 3 V, other inputs at VCC or GND. [2] 9.1 Test circuits VCC VCC nOE VIH A VI IS nB nA nOE VIL IS A A GND VO VI IS 001aak864 Product data sheet GND VO VI = VCC or GND and VO = open circuit. Test circuit for measuring OFF-state leakage current (one switch) 74CBTLV3125 nB 001aak865 VI = VCC or GND and VO = GND or VCC. Fig 6. nA Fig 7. Test circuit for measuring ON-state leakage current (one switch) All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 5 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 9.2 ON resistance Table 7. Resistance RON At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter RON Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 64 mA; VI = 0 V - 4.2 8.0 - 15.0 ISW = 24 mA; VI = 0 V - 4.2 8.0 - 15.0 ISW = 15 mA; VI = 1.7 V - 8.4 40.0 - 60.0 ISW = 64 mA; VI = 0 V - 4.0 7.0 - 11.0 ISW = 24 mA; VI = 0 V - 4.0 7.0 - 11.0 ISW = 15 mA; VI = 2.4 V - 6.2 15.0 - 25.5 ON resistance VCC = 2.3 V to 2.7 V; see Figure 9 to Figure 11 [2] VCC = 3.0 V to 3.6 V; see Figure 12 to Figure 14 [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 9.3 ON resistance test circuit and graphs 001aai109 11 RON (Ω) 9 VSW V 7 VCC (1) nOE VIL (2) 5 nA nB (3) VI GND ISW (4) 3 0 0.5 1.0 1.5 2.0 2.5 VI (V) 001aak866 (1) Tamb = 125 C. RON = VSW / ISW. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 8. Test circuit for measuring ON resistance (one switch) 74CBTLV3125 Product data sheet Fig 9. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 15 mA All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 6 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 001aai110 11 RON (Ω) 001aai111 11 RON (Ω) 9 9 7 7 (1) (1) (2) 5 (2) 5 (3) (3) (4) (4) 3 3 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 VI (V) (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 10. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 24 mA Fig 11. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 64 mA 001aai105 8 2.5 VI (V) RON (Ω) 001aai106 8 RON (Ω) 6 6 (1) (1) (2) (2) (3) 4 (3) 4 (4) (4) 2 2 0 1 2 3 4 0 1 VI (V) (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 12. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 15 mA Product data sheet 3 4 VI (V) (1) Tamb = 125 C. 74CBTLV3125 2 Fig 13. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 24 mA All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 7 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 001aai107 7.5 RON (Ω) 6.5 5.5 (1) (2) 4.5 (3) 3.5 (4) 2.5 0 1 2 3 4 VI (V) (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 17 Symbol Parameter Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - - 0.13 - 0.20 ns - - 0.20 - 0.31 ns 1.0 2.7 4.6 1.0 6.0 ns 1.0 2.4 4.4 1.0 6.0 ns VCC = 2.3 V to 2.7 V 1.0 2.2 3.9 1.0 5.5 ns VCC = 3.0 V to 3.6 V 1.0 2.9 4.2 1.0 5.5 ns propagation delay nA to nB or nB to nA; see Figure 15 tpd [2][3] VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V enable time ten [4] nOE to nA or nB; see Figure 16 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V disable time tdis [5] nOE to nA or nB; see Figure 16 [1] All typical values are measured at Tamb = 25 C and at nominal VCC. [2] The propagation delay is the calculated RC time constant of the on-state resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance). [3] tpd is the same as tPLH and tPHL. [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPHZ and tPLZ. 74CBTLV3125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 8 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 11. Waveforms VI input VM VM 0V tPHL tPLH VOH VM output VM VOL 001aai367 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 15. The data input (nA or nB) to output (nB or nA) propagation delays Table 9. Measurement points Supply voltage Input VCC VM VI tr = tf Output VM VX VY 2.3 V to 2.7 V 0.5VCC VCC 2.0 ns 0.5VCC VOL + 0.15 V VOH 0.15 V 3.0 V to 3.6 V 0.5VCC VCC 2.0 ns 0.5VCC VOL + 0.3 V VOH 0.3 V VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND switch enabled switch enabled switch disabled 001aak860 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 16. Enable and disable times 74CBTLV3125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 9 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 17. Test circuit for measuring switching times Table 10. Test data Supply voltage Load VCC CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 2.3 V to 2.7 V 30 pF 500 open GND 2VCC 3.0 V to 3.6 V 50 pF 500 open GND 2VCC 74CBTLV3125 Product data sheet VEXT All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 10 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 12. Package outline SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm D E SOT519-1 A X c y HE v M A Z 9 16 A2 A (A 3) A1 θ Lp L 8 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp v w y Z (1) θ mm 1.73 0.25 0.10 1.55 1.40 0.25 0.31 0.20 0.25 0.18 5.0 4.8 4.0 3.8 0.635 6.2 5.8 1 0.89 0.41 0.2 0.18 0.09 0.18 0.05 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-05-04 03-02-18 SOT519-1 Fig 18. Package outline SOT519-1 (SSOP16) 74CBTLV3125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 11 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 19. Package outline SOT402-1 (TSSOP14) 74CBTLV3125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 12 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 20. Package outline SOT762-1 (DHVQFN14) 74CBTLV3125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 13 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74CBTLV3125 v.3 20111215 Product data sheet - 74CBTLV3125 v.2 Modifications: • Legal pages updated. 74CBTLV3125 v.2 20110104 Product data sheet - 74CBTLV3125 v.1 74CBTLV3125 v.1 20100108 Product data sheet - - 74CBTLV3125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 14 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. 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All rights reserved. 15 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74CBTLV3125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 16 of 17 74CBTLV3125 NXP Semiconductors 4-bit bus switch 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 9.1 9.2 9.3 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 December 2011 Document identifier: 74CBTLV3125