UM6401 6 Line ESD/EMI Protection for Color LCD Interfaces UM6401 DFN12 3.0×1.6 General Description The UM6401 is a low pass filter array with integrated TVS diodes. It is designed to suppress unwanted EMI/RFI signals and provide electrostatic discharge (ESD) protection in portable electronic equipment. This state-of-the-art device utilizes solid-state silicon-avalanche technology for superior clamping performance and DC electrical characteristics. They have been optimized for protection of color LCD panels in cellular phones and other portable electronics. The device consists of six identical circuits comprised of TVS diodes for ESD protection, and a resistor -capacitor network for EMI/RFI filtering. A series resistor value of 100Ω and a capacitance value of 10pF are used to achieve 30dB minimum attenuation from 800MHz to 2.5GHz. The TVS diodes provide effective suppression of ESD voltages in excess of ±15kV (air discharge) and ±8kV (contact discharge) per IEC 61000-4-2, level 4. The UM6401 is in a 12-pin, RoHS compliant, DFN12 3.0×1.6 package. The leads are spaced at a pitch of 0.5mm and are finished with lead-free Ni Pd. The small package makes it ideal for use in portable electronics such as cell phones, digital still cameras, and PDAs. Applications Features Color LCD Protection Cell Phone CCD Camera Lines Bottom Connector Cell Phones Pin Configurations Bidirectional EMI/RFI Filter with Integrated TVS ESD Protection to IEC 61000-4-2 (ESD) Level 4, ±15kV (Air), ±8kV (Contact) 30dB Minimum Attenuation: 800MHz to 2.5GHz TVS Working Voltage: 5V Resistor: 100Ω±15% Typical Capacitance: 10pF (VR=2.5V) Protection and Filtering for Six Lines Solid-State Technology Top View XX: Week Code UM6401 DFN12 3.0×1.6 ___________________________________________________________________________ http://www.union-ic.com Rev.06 Dec.2014 1/7 UM6401 Ordering Information Part Number Working Voltage Packaging Type Channel Marking Code Shipping Qty UM6401 5.0V DFN12 3.0×1.6 6 6401 3000pcs/7 Inch Tape & Reel Absolute Maximum Ratings PARAMETER SYMBOL VALUE UNITS Junction Temperature TJ 125 °C Steady-State Power per Resistor @ 25 PR 328 mW Operating Temperature Range TOP -40 to 85 °C Storage Temperature Range TSTG -55 to 150 °C TL 260 °C Maximum Lead Temperature for Soldering Electrical Characteristics PARAMETER Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current SYMBOL CONDITIONS MIN TYP VRWM VBR It = 1mA VRWM = 3.0V IR=20mA Total Series Resistance RA Each Line Input to GND, Total Capacitance Cd Each Line VR = 0V, f = 1MHz Input to GND, Total Capacitance Cd Each Line VR = 2.5V, f = 1MHz Above this frequency, Cut-Off Frequency f3dB appreciable attenuation (Note 1) occurs Note 1: 50Ω source and 50Ω load termination. 6 7 IR MAX UNITS 5 V 8 V 0.5 μA 85 100 115 Ω 16 20 24 pF 9 10 12 pF 150 MHz ___________________________________________________________________________ http://www.union-ic.com Rev.06 Dec.2014 2/7 UM6401 Typical Operating Characteristics Typical Insertion Loss S21 Analog Crosstalk Curve (S41) -5 -30 -10 -35 -15 -40 S41(dB) S21 (dB) -20 -25 -30 -45 -50 -35 -55 -40 -45 -60 1E7 1E7 1E8 1E8 1E9 1E9 Frequency(Hz) FREQUENCY (Hz) Typical Resistance vs. Temperature Capacitance vs. Reverse Voltage 104 1.0 103 0.9 101 Cj(Vr)/Cj(Vr=0) Resistance(ohm) 102 100 99 98 0.8 0.7 0.6 f=1M 97 0.5 96 0.4 -40 -20 0 20 40 60 Temperature(Celsiur scale) ESD Clamping (+8kV Contact) 80 0 1 2 3 4 5 Reverse Voltage - Vr(V) ESD Clamping (-8kV Contact) ___________________________________________________________________________ http://www.union-ic.com Rev.06 Dec.2014 3/7 UM6401 Applications Information Device Connection The UM6401 is comprised of six identical circuits each consisting of a low pass filter for EMI/RFI suppression and dual TVS diodes for ESD protection. The device is in a 12-pin DFN package. Electrical connection is made to the 12 pins located at the bottom of the device. A center tab serves as the ground connection. The device has a flow through design for easy layout. Pin connections are noted in Figure 1. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Recommendations for the ground connection are given below. Ground Connection Recommendation Parasitic inductance present in the board layout will affect the filtering performance of the device. As frequency increases, the effect of the inductance becomes more dominant. This effect is given by Equation 1. Pin 1-6 Identification Input Lines 7 - 12 Output Lines Center Tab Ground Equation 1: The Impedance of an Inductor at Frequency XLF XLF(L,f ) = 2×л×f ×L Where: L= Inductance (H) f = Frequency (Hz) Via connections to the ground plane form rectangular wire loops or ground loop inductance as shown in Figure 2. Ground loop inductance can be reduced by using multiple vias to make the connection to the ground plane. Bringing the ground plane closer to the signal layer (preferably the next layer) also reduces ground loop inductance. Multiple vias in the device ground pad will result in a lower inductive ground loop over two exterior vias. Vias with a diameter d are separated by a distance y run between layers separated by a distance x. The inductance of the loop path is given by Equation 2. Thus, decreasing distance x and y will reduce the loop inductance and result in better high frequency filter characteristics. Where: d = Diameter of the wire (in) x = Length of wire loop (in) y = Breath of wire loop (in) ___________________________________________________________________________ http://www.union-ic.com Rev.06 Dec.2014 4/7 UM6401 Figure 3 shows the recommended device layout. The ground pad vias have a diameter of 0.008 inches (0.20 mm) while the two external vias have a diameter of 0.010 inches (0.250mm). The internal vias are spaced approximately evenly from the center of the pad. The designer may choose to use more vias with a smaller diameter (such as 0.005 inches or 0.125mm) since changing the diameter of the via will result in little change in inductance (i.e. the log function in Equation 2 in highly insensitive to parameter d) . ___________________________________________________________________________ http://www.union-ic.com Rev.06 Dec.2014 5/7 UM6401 Package Information UM6401: DFN12 3.0×1.6 Outline Drawing Symbol A A1 A2 b c D D1 E e L DIMENSIONS MILLIMETERS INCHES Min Max Min Max 0.700 0.800 0.028 0.031 0.000 0.050 0.000 0.002 0.153 0.253 0.006 0.010 0.180 0.300 0.007 0.012 0.300 0.500 0.012 0.020 2.900 3.100 0.114 0.122 2.400 2.600 0.094 0.102 1.550 1.675 0.061 0.066 0.450 0.550 0.018 0.022 0.150 0.350 0.006 0.014 Land Pattern NOTES: 1. Compound dimension: 3.0×1.6; 2. Unit: mm; 3. General tolerance ±0.05mm unless otherwise specified; 4. The layout is just for reference. Tape and Reel Orientation ___________________________________________________________________________ http://www.union-ic.com Rev.06 Dec.2014 6/7 UM6401 IMPORTANT NOTICE The information in this document has been carefully reviewed and is believed to be accurate. Nonetheless, this document is subject to change without notice. Union assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the contained information, or to notify a person or organization of any update. Union reserves the right to make changes, at any time, in order to improve reliability, function or design and to attempt to supply the best product possible. Union Semiconductor, Inc Add: Unit 606, No.570 Shengxia Road, Shanghai 201210 Tel: 021-51093966 Fax: 021-51026018 Website: www.union-ic.com ___________________________________________________________________________ http://www.union-ic.com Rev.06 Dec.2014 7/7