UM5204EECD - Union Semiconductor

UM5204EECD
Quad Channel Low Capacitance ESD Protection Array
UM5204EECD TSOP-6/SOT23-6
General Description
UM5204EECD is surge rated diode arrays designed to protect high speed data interfaces. This
series has been specifically designed to protect sensitive components which are connected to data
and transmission lines from over-voltage caused by ESD (electrostatic discharge).
The unique design incorporates surge rated, low capacitance steering diodes and a TVS diode in a
single package. During transient conditions, the steering diodes direct the transient to either the
positive side of the power supply line or to ground. The internal TVS diode prevents over-voltage
on the power line, protecting any downstream components.
The low capacitance array configuration allows the user to protect four high-speed data or
transmission lines. The low inductance construction minimizes voltage overshoot during high
current surges. This device is optimized for ESD protection of portable electronics. They may be
used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (± 15kV air, ± 8kV
contact discharge).
Applications
Features








USB 2.0
USB OTG
Monitors and Flat Panel Displays
Digital Visual Interface (DVI)
High-Definition Multimedia Interface
(HDMI)
SIM Ports
IEEE 1394 Firewire Ports







Pin Configurations
Transient Protection for High-Speed Data
Lines to IEC 61000-4-2 (ESD) ± 15kV (Air),
±8kV (Contact)
Array of Surge Rated Diodes with Internal
TVS Diode
Protects up to Four I/O Lines & Power Line
Low Capacitance (<2pF) for High-Speed
Interfaces
No Insertion Loss to 2.0GHz
Low Leakage Current and Clamping Voltage
Low Operating Voltage: 5.0V
Solid-State Silicon-Avalanche Technology
Top View
XX: Week Code
UM5204EECD
TSOP-6/SOT23-6
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UM5204EECD
Ordering Information
Part Number
Working
Voltage
Packaging Type
Channel
Marking
Code
Shipping Qty
UM5204EECD
5.0V
TSOP-6/SOT23-6
4
UCF
3000pcs /7Inch
Tape & Reel
Absolute Maximum Ratings
RATING
Peak Pulse Power (tp = 8/20µs)
SYMBOL
VALUE
UNITS
Ppk
150
Watts
IPP
A
kV
°C
Peak Pulse Current (tp = 8/20µs )
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Operating Temperature
VESD
TJ
6
±15
±8
-55 to +125
Storage Temperature
TSTG
-55 to +150
°C
Electrical Characteristics (Note 1)
PARAMETER
Reverse Stand-Off
Voltage
Reverse Breakdown
Voltage
Reverse Leakage
Current
SYMBOL
VBR
IR
VC
Clamping Voltage
VC
Reverse Recovery
Time
MIN
TYP
VRWM
Clamping Voltage
Junction
Capacitance
TEST CONDITIONS
Cj
Trr
It = 1mA, Pin 5 to Pin2
VRWM = 5V, T=25°C,
Pin5 to Pin2
IPP = 1A, 8/20µs,
Any pin to pin2
IPP = 6A, 8/20µs,
Any pin to pin2
VR = 0V, f = 1MHz,
Any I/O pin to pin2
VR = 0V, f = 1MHz ,
Between I/O pins
VR = 0V, f = 1MHz,
Pin5 to pin2
VR = 2.5V, f = 1MHz,
Pin5 to pin2
Pin2 to Pin5
MAX
UNIT
5.0
V
6.0
V
2
µA
15
V
25
V
2
pF
1
pF
60
pF
40
pF
40
ns
Pin2 to I/O Pin
160
ns
Pin5 to I/O Pin
45
ns
Note 1: I/O pins are pin 1, 3, 4, and 6
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UM5204EECD
Typical Operating Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
110
10
90
% of Rated Power or Ipp
Peak Pulse Power – PPK (kW)
100
1
0.1
80
70
60
50
40
30
20
10
0
0.01
0.1
10
1
100
0
1000
25
Pulse Duration – tp (µs)
Pulse Waveform
75
100
125
150
Clamping Voltage vs. Peak Pulse Current
110
28
90
80
Clamping Voltage – Vc (V)
Waveform
Parameters:
tr=8μs
td=20μs
100
e-t
70
60
50
td=IPP/2
40
30
20
24
Pin 1, 3, 4, 6 to
Pin 2
20
16
Pin 5 to Pin 2
Waveform
Parameters:
tr=8μs
td=20μs
12
10
8
0
0
5
10
15
20
25
0
30
1
2
3
4
5
6
Peak Pulse Current – Ipp (A)
Time (µs)
Forward Voltage vs. Forward Current
Junction Capacitance vs. Reverse Voltage
8
3
f=1MHz
2.5
6
Capacitance – Cj (pF)
Forward Voltage – VF (V)
Percent of Ipp
50
Ambient Temperature - TA(℃)
4
Waveform
Parameters:
tr=8μs
td=20μs
2
0
0
1
2
3
4
Forward Current – IF (A)
5
6
2
Any I/O Pin
to Pin2
1.5
1
0.5
0
0
1
2
3
4
Reverse Voltage – VR (V)
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UM5204EECD
Applications Information
Device Connection Options for Protection of Four High-Speed Data Lines
This device is designed to protect data lines by clamping them to a fixed reference. When the
voltage on the protected line exceeds the reference voltage the steering diodes are forward biased,
conducting the transient current away from the sensitive circuitry. Data lines are connected at pins
1, 3, 4 and 6. Pin 2 should be connected directly to a ground plane. The path length is kept as short
as possible to minimize parasitic inductance. The positive reference is connected at pin 5. The
options for connecting the positive reference are as follows:
1. To protect data lines and the power line, connect pin 5 directly to the positive supply rail (VCC).
In this configuration the data lines are referenced to the supply voltage. The internal TVS diode
prevents over-voltage on the supply rail.
2. In applications where the supply rail does not exit the system, the internal TVS may be used as
the reference. In this case, pin 5 is not connected. The steering diodes will begin to conduct when
the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop).
3. In applications where complete supply isolation is desired, the internal TVS is again used as the
reference and VCC is connected to one of the I/O inputs. An example of this configuration is the
protection of a SIM port. The Clock, Reset, I/O, and VCC lines are connected at pins 1, 3, 4, and 6.
Pin 2 is connected to ground and pin 5 is not connected.
Protection of Four Data Lines and Power Supply Line
Protection of Four Data Lines
using Internal TVS Diode as Reference
To
Protected
IC
I/O 1
I/O 2
1
6
2
5
3
4
I/O 3
I/O 4
I/O 2
VCC
To
Protected
IC
To
Protected
IC
I/O 1
I/O 3
I/O 4
1
6
2
5
3
4
NC
To
Protected
IC
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte
tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads
is small compared to the solder paste volume that is placed on the land pattern of the PCB, the
reflow profile will be determined by the requirements of the solder paste. Therefore, these devices
are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other
lead-free compositions, matte tin does not have any added alloys that can cause degradation of the
solder joint.
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UM5204EECD
Package Information
UM5204EECD TSOP-6/SOT23-6
Outline Drawing
D
θ
b
5
4
1
2
3
L
L1
E
E1
6
e
c
20
e1
Top View
A
A2
A1
End View
Side View
DIMENSIONS
MILLIMETERS
Symbol
Min
Max
A
1.050
1.250
A1
0.000
0.100
A2
1.050
1.150
b
0.300
0.500
c
0.100
0.200
D
2.820
3.020
E
1.500
1.700
E1
2.650
2.950
e
0.950REF
e1
1.800
2.000
L
0.600REF
L1
0.300
0.600
θ
0°
8°
INCHES
Min
Max
0.041 0.049
0.000 0.004
0.041 0.045
0.012 0.020
0.004 0.008
0.111 0.119
0.059 0.067
0.104 0.116
0.037REF
0.071 0.079
0.023REF
0.012 0.024
0°
8°
Land Pattern
2.4
0.9
0.7
0.95
0.95
NOTES:
1. Compound dimension: 2.92×1.60;
2. Unit: mm;
3. General tolerance ±0.05mm unless otherwise
specified;
4. The layout is just for reference.
UCF
XX
Tape and Reel Orientation
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UM5204EECD
IMPORTANT NOTICE
The information in this document has been carefully reviewed and is believed to be
accurate. Nonetheless, this document is subject to change without notice. Union assumes
no responsibility for any inaccuracies that may be contained in this document, and makes
no commitment to update or to keep current the contained information, or to notify a
person or organization of any update. Union reserves the right to make changes, at any
time, in order to improve reliability, function or design and to attempt to supply the best
product possible.
Union Semiconductor, Inc
Add: Unit 606, No.570 Shengxia Road, Shanghai 201210
Tel: 021-51093966
Fax: 021-51026018
Website: www.union-ic.com
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