BL8589

BL8589
16-Channel Constant-Current LED Driver
DESCRIPTION
FEATURES
The BL8589 is designed for LED display
applications. The device has an input shift
register with corresponding data latches and
16 constant current sink drivers.

16 constant-current output channels, with
maximum current capability up to 50 mA
each
3.0 to 5.5 V logic supply range
Schmitt trigger inputs for improved noise
Immunity
Power-On Reset , all register bits=0
Low-power CMOS logic and latches
High data input rate: 30MHz
Output current accuracy: between channels
< ±3% and between ICs ±6%, over the full
operating temperature range
Internal UVLO and thermal shutdown (TSD)
circuitry


The device support digital input with internal
shift registers and latches, hence can be
controlled directly by microprocessor-based
systems. With a standard 3.3V or 5V logic
supply, serial data input rates can reach up to
30 MHz. The BL8589 allows user defined
maximum LED drive current level which is set
by a single external resistor. Chip build-in
serial data output permits cascading of multiple
devices in applications requiring additional
drive lines.





APPLICATIONS
The BL8589 is available in a variety of 24terminal packages: QFN44-24, which has an
exposed thermal pad, SSOP-24 and TSSOP24. All packages are lead (Pb) free and RoHS
compliable.

Single-color, multicolor, or full-color LED
display
Single-color, multicolor, or full-color LED
signboard
Display backlighting
Multicolor LED lighting



TYPICAL APPLICATION
VLED
10uF
OUT0
Controller
OUT0
SDO
CLK
VDD
OE
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OUT15
SDI
LE
BL8589
LC9300
10uF
VDD
100nF
SDI
SDO
CLK
VDD
GND
LE
REXT
OE
1
OUT15
BL8589
LC9300
GND
REXT
VDD
100nF
BL8589
FUNCTIONAL BLOCK DIAGRAM
OUT0
REXT
VDD
OUT1
OUT14
OUT15
VDD
Current
Regulator
OE
UVLO
Output Control Drivers
TSD
16 bits
LE
Latches
GND
16 bits
SDI
16 bits Shift Registors
SDO
CLK
PIN DESCRIPTION
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
QFN44-24
6
4
7
24
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Number
TSSOP-24 & SSOP-24
3
3
1
1
4
4
21
21
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
PAD
-
-
-
REXT
2
23
23
SDI
SDO
VDD
5
1
3
2
22
24
2
22
24
Name
CLK
GND
LE
OE
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Description
Clock, data shift clock input terminal
Ground
Latch Enable input terminal, active high
Output Enable input terminal, active low
Constant current outputs
Exposed pad for enhanced thermal dissipation,
not connected internally, connect to GND.
Reference current terminal, sets output current
for all channels
Serial Data in terminal
Serial Data out terminal
Logic supply terminal
2
BL8589
OE
OUT15
OUT14
OUT13
OUT12
OUT11
PIN CONFIGURATION
24
23
22
21
20
19
24
VDD
GND
1
24
VDD
2
23
REXT
SDI
2
23
REXT
CLK
3
22
SDO
CLK
3
22
SDO
LE
4
21
OE
LE
4
21
OE
OUT0
5
20
OUT15
OUT0
5
20
OUT15
16 OUT8
OUT1
6
19
OUT14
OUT1
6
19
OUT14
15 OUT7
OUT2
7
18
OUT13
OUT2
7
18
OUT13
SDI 5
14 OUT6
OUT3
8
17
OUT12
OUT3
8
17
OUT12
CLK 6
13 OUT5
OUT4
9
16
OUT11
OUT4
9
16
OUT11
OUT5 10
15
OUT10
OUT5 10
15
OUT10
OUT6
11
14
OUT9
OUT6
11
14
OUT9
OUT7
12
13
OUT8
OUT7
12
13
OUT8
REXT 2
17 OUT9
LLLL
18 OUT10
VDD 3
7
8
9
10
11
12
LE
OUT0
OUT1
OUT2
OUT3
OUT4
GND 4
BL8589
LC9300
SDO 1
QFN44
Top View
BL8589
LC9300
LLLL
1
SDI
BL8589
LC9300
LLLL
GND
Thermal Pad
TSSOP-24
SSOP-24
Marking: LLLL: LOT No.
ORDERING INFORMATION
Product NO
BL8589
BL8589
BL8589
Ordering Number
BL8589CJLTR
BL8589CPOTR
BL8589CQOTR
Pin Package
QFN44-24
SSOP-24
TSSOP-24
Devices per reel
3000
2000
2000
Temperature range & Rohs
-40~150C & Pb free
-40~150C & Pb free
-40~150C & Pb free
ABSOLUTE MAXIMUM RATINGS
Characteristic
Supply Voltage
Input Voltage Range
OUT(X) Output Current
OUT(X) Voltage Range
Clock Frequency
ESD Rating
Junction Temperature
Storage Temperature
Symbol
VDD
VSDI, VCLK, VLE, V OE
I OUT(X)
VOUT(X)
fCLK
HBM
CDM
TJ
TSTG
Rating
0~8.0
-0.3~VDD+0.3
+65
-0.3~12
30
2.0
1.0
150
-55~165
Units
V
V
mA
V
MHz
KV
KV
C
C
ELECTRICAL CHARACTERISTICS
(Test Conditions: TA1=25C, VDD=3.0 to 5.5V, unless otherwise specified.)
Symbol
Parameter
Conditions
Min.
VDD
Input Voltage
Operating
3.0
VDD 0→5V
2.5
Under voltage
VDD(UV)
Lockout
VDD 5→0V
2.3
VDD=4.5 to 5.5V,
47.4
VOUT(X)=1V, RREXT =374Ω
VDD=3.0 to 3.6V,
46.5
VOUT(X)=1V, RREXT =374Ω
IOUT(X)
Output Current
VDD=4.5 to 5.5V,
19.8
VOUT(X)=1V, RREXT =910Ω
VDD=3.0 to 3.6V,
19.5
VOUT(X)=1V, RREXT =910Ω
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3
Typ2
5.0
2.7
2.5
Max.
5.5
2.9
2.7
Units
V
V
V
51.1
54.5
mA
50.1
53.5
mA
21.4
22.8
mA
21.0
22.4
mA
BL8589
ELECTRICAL CHARACTERISTICS (Continued)
(Test Conditions: TA1=25C, VDD=3.0 to 5.5V, unless otherwise specified.)
％Δ IOUT(X)
Output Current
Shift
Err
Out to Out
Matching3
％Δ
IOUT(X)(REG)
IOUT(X)LK
VIH
VIL
VIHYS
IL
VOL
VOH
IVDD(OFF)
IVDD(ON)
VREXT
TJTSD
TJTSDhys
Output Current
Regulation
VDD=5.5V, VOUT(X)=1V, RREXT
=910Ω , TA=25C; between
one output on and all outputs
on
VOUT(X)=1V, RREXT =374Ω , all
outputs on
VOUT(X)=1V, RREXT =910Ω , all
outputs on
VDD=5.5V, VOUT(X)=1 to 3V,
RREXT =374Ω , all outputs on
VDD=5.5V, VOUT(X)=1 to 3V,
RREXT=910Ω , all outputs on
VDD=3.6V, VOUT(X)=1 to 3V,
RREXT =374Ω , all outputs on
VDD=3.6V, VOUT(X)=1 to 3V,
RREXT =910Ω , all outputs on
Output Leakage
VOUT(X)=12V, V OE =Logic “1”
Current
Logic Input
Voltage
Logic Input
Voltage
All digital inputs
Hysteresis
Logic Input
All digital inputs
Current
IOL=1mA
SDO Voltage
IOH=-1mA
RREXT =3.8kΩ, V OE =Logic “1”
RREXT =910Ω, V OE = Logic “1”
RREXT =374Ω, V OE = Logic “1”
All outputs on, RREXT =910Ω,
Supply Current4
VOUT(X)=1V, Data transfer
30MHz
All outputs on, RREXT =374Ω,
VOUT(X)=1V, Data transfer
30MHz
Reference
RREXT =374Ω
Voltage
Thermal
Temperature Increasing
Shutdown
Thermal
Shutdown
Temperature Decreasing
Hysterisis
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4
-
-
±1
%
-
±1
±3
%
-
±1
±3
%
-
1.7
3
%
-
2.4
4
%
-
1.2
2
%
-
1.8
3
%
-
-
0.5
uA
0.8*VDD GND
-
VDD
V
0.2*GND V
250
-
900
mV
-1
-
1
uA
VDD-0.5
-
-
0.5
6
16
40
V
V
mA
mA
mA
-
-
20
mA
-
-
45
mA
-
1.21
-
V
-
150
-
C
-
30
-
C
BL8589
SWITCHING CHARACTERISTICS
(Test Conditions: TA1=25C, VIH=VDD=5.0V, VOUT(X)=1V, VIL=0V, RREXT=910Ω , VL=2V, RL=51Ω ,
CL=15pF(see also Timing section).
Symbol
Parameter
Conditions
Min
Typ2 Max Units
fCLK
Clock Frequency
30
MHz
Clock Frequency
fCLKC
25
MHz
(cascade devices)
twh0
Clock pulse duration CLK= Logic “1”
16
ns
twh1
LE pulse duration
LE= Logic “1”
20
ns
SDI to CLK↑
tsu0
10
ns
Setup Time
CLK↑ to LE↑
tsu1
10
ns
CLK↑ to SDI
th0
10
ns
Hold Time
LE↓ to CLK↑
th1
10
ns
SDO, 10/90% points
tr0
16
ns
(measurement circuit A)
Rise Time
OUTx, VDD=5V, 10/90% points
tr1
10
30
ns
(measurement circuit B)
SDO, 10/90% points
tf0
16
ns
(measurement circuit A)
Fall Time
OUTx, VDD=5V, 10/90% points
tf1
10
30
ns
(measurement circuit B)
CLK↑ to SDO
tpd0
30
ns
(measurement circuit A)
Propagation Delay
OE ↓to OUTx
tpd1
60
ns
Time
(measurement circuit B)
LE↑to OUTx
tpd2
60
ns
(measurement circuit B)
Output Enable Pulse
tw( OE )
(see Timing Diagrams section)
60
ns
Duration
1
Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may
vary for individual units, within the specified maximum and minimum limits.
3
Err = (IO(min or max) – IO(av)) / IO(av). IO(av) is the average current of all outputs. IO(min or max) is the output current with the greatest
Difference from IO(av).
4
Recommended operating range: VO = 1.0 to 3.0 V.
2
INPUT-OUTPUT TRUTH TABLE
SDI
H
L
X
CLK
Shift Register Contents
I0 I1 I2 … I15
H R0 R1 … R14
L R0 R1 … R14
R0 R1 R2 … R15
X X X … X
P0 P1 P2 … P15
SDO
LE
Latch Contents
I0 I1 I2 … I15
OE
Output Contents
I0 I1 I2 … I15
L
H
P0 P1 P2 … P15
Hiz Hiz Hiz… Hiz
R15
R15
X
L
H
R0 R1 R2 … R15
P0 P1 P2 … P15
X X X … X
L = Low logic (voltage) input, H = High logic (voltage) input, X = Don’t care, P = Present state, R = Previous state，Hiz=High impedance
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5
BL8589
TIMING DIAGRAMS
CLK
0
1
D0
D1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D14
D15
16
SDI
OE
LE
OUT0
D15
OUT1
D14
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
D1
OUT15
D0
SDO
D0
Do not care
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On status
High impedance
6
BL8589
TIMING DIAGRAMS (Continued)
Disabling Outputs
tW(OE)
OE
50%
50%
tpd1
tpd1
90%
OUT(x)
(Current)
50%
50%
10%
tr1
tf1
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7
BL8589
PARAMETER MEASUREMENT CIRCUITS
VL
SDO
RL
OUT(X)
15pF
CL
LC9300
BL8589
LC9300
BL8589
(A) Circuit for tf0, tpd0, tr0
(B) Circuit for tf1, tpd1, tpd2 and tr1
OPERATING CHARACTERISTICS
Channel Output Current vs External Resistance
Channel Output Current vs OUT(X) Voltage
50
45
VDD=3V
Iout(x) (mA)
VDD=5V
30
(mA)
Iout(x) (mA)
40
20
35
Rext=470Ω
Rext=910Ω
25
10
15
0
0
2
0
4
1
2
3
Vout(x) (V)
Rext (KΩ )
APPLICATION INFORMATION
Normal Operation
pins are high during serial data entry the
latches are bypassed.
A CLK (Clock) input pulse or more specifically
the rising edge of the CLK starts the transfer of
serial data from the SDI (Serial Data In) input
to the shift register. For proper and accurate
transfer, the serial data must appear at the
input prior to the rising edge of the CLK
waveform. The register stores the SDI data
and forward to the SDO (Serial Data Out)
output upon succeeding CLK pulses.
Setting Maximum Channel Current
The maximum individual channel output
current is determined by the external resistor,
RREXT, which is placed between the REXT pin
and GND. The voltage on RREXT, VREXT, is set
by build-in bandgap reference, of which the
typical value is 1.21V.
Access to the data stored in the register from
corresponding latches can be enabled by
holding LE high (serial-to-parallel conversion).
Holding OE (Output Enable) high disables the
output sink drivers. While with OE active (low),
the outputs are controlled by the state of their
respective latches. When both LE and OE
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Following equations can be used to calculate
the maximum channel output current:
IOUT(X) (max) = (1.24/ RREXT) *15
where RREXT is the value of the external resistor,
which should larger than 374 Ω. The maximum
per channel (OUT0 to OUT15) constant output
current IOUT(X) (max) as a function of values of
8
BL8589
RREXT is shown in the Operating Characteristics
section.
VOUT(X) will result in increased package power
dissipation. To minimize package power
dissipation, it is recommended that either
lowest possible load supply voltage (VLED) is
used or to set a series voltage drop, VDROP,
according to the following equation:
Under voltage Lockout
The BL8589 has an internal under voltage
lockout (UVLO) function to ensure proper
device operation. The outputs are disabled
once the supply voltage drops below a
minimum acceptable level. This feature is of
significant importance for some critical
applications. Upon recovery of the supply
voltage after a UVLO event, all internal shift
registers and latches are set to 0. The BL8589
is then operated in normal mode.
VDROP = VLED – VF –VOUT(X),
in which VF is the LED forward voltage. VDROP =
IO× RDROP for a single driver, for a Zener diode
(VZ), or for a series string of silicon diodes
(approximately 0.7 V per diode) for a group of
drivers (these configurations are shown in the
figure). If the available voltage source will
cause unacceptable power dissipation and
series resistors or diodes are undesirable, a
voltage regulator can be used to provide VLED.
Thermal Shutdown Protection
The typical value of thermal shutdown
threshold temperature TJTSD is 150°C. If the
junction temperature exceeds this value, the
outputs will be turned off. There exists a
thermal shutdown hysteresis, which is typically
30°C. Hence outputs are resumed once the
device is cooled down and junction
temperature falls below 135°C. However, the
shift register and output latches register remain
active during a thermal shutdown event.
Therefore, stored data is preserved and there
is no need to reset.
VLED
VDROP
VF
VDS
Load Supply Voltage (VLED)
The optimum driver voltage drops (VOUT(X)) for
the device is in the range of 1.0 to 3.0V. Higher
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VLED
VLED
VDROP
VDROP
VF
VF
VDS
VDS
Typical Application Voltage Drops
9
BL8589
PACKAGE LINE
Package
Symbol
QFN44-24
Devices per reel
Dimension (mm)
3000Pcs
Symbol
Unit
mm
Dimension (mm)
MIN
NOM
MAX
A
0.77
0.82
0.87
Ne
2.50BSC
A1
-
0.01
0.05
Nd
2.50BSC
b
0.18
0.25
0.32
E
c
0.18
0.20
0.22
E2
D
3.90
4.00
4.10
L
0.35
0.40
0.45
h
0.30
0.35
0.40
D2
2.50REF
e
0.50BSC
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10
MIN
3.90
NOM
4.00
MAX
4.10
2.50REF
4.00
BL8589
PACKAGE LINE (Continued)
Package
Symbol
TSSOP-24
Devices per reel
Dimension (mm)
MIN
NOM
MAX
A
-
-
1.77
A1
0.08
0.18
A2
1.20
A3
2000Pcs
Symbol
Unit
mm
Dimension (mm)
MIN
NOM
MAX
D
8.45
8.65
8.85
0.28
E
5.8
6.0
6.2
1.40
1.60
E1
3.7
3.9
4.1
0.55
0.65
0.75
e
b
0.23
-
0.33
L
b1
0.22
0.25
0.28
L1
c
0.21
-
0.26

c1
0.19
0.20
0.21

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11
0.635BSC
0.5
0.65
0.8
1.05BSC
0
-
8°
BL8589
PACKAGE LINE (Continued)
Package
Symbol
SSOP-24
Devices per reel
Dimension (mm)
MIN
NOM
MAX
A
-
-
1.90
A1
0.05
A2
1.40
A3
2000Pcs
Symbol
Unit
mm
Dimension (mm)
MIN
NOM
MAX
D
12.80
13.00
13.20
0.15
E
7.70
7.90
8.10
1.50
1.60
E1
5.80
6.00
6.20
0.47
0.67
0.87
e
b
0.39
-
0.47
L
b1
0.38
0.40
0.43
L1
c
0.15
-
0.20

c1
0.14
0.15
0.16

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12
1.00BSC
0.25
0.45
0.65
0.95BSC
0
-
8°