FIN1049 LVDS Dual-Line Driver with Dual-Line Receiver Features Description Greater than 400 Mbps Data Rate 3.3 V Power Supply Operation Low Power Dissipation Fail-Safe Protection for Open-Circuit Conditions Meets or Exceeds TIA/EIA-644-A LVDS Standard 16-pin TSSOP Package Saves Space Flow-Through Pinout Simplifies PCB Layout Enable/Disable for all Outputs Industrial Operating Temperature Range: -40°C to +85°C This dual driver-receiver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver accepts LVTTL inputs and translates them to LVDS outputs. The receiver accepts LVDS inputs and translates them to LVTTL outputs. The LVDS levels have a typical differential output swing of 350 mV, which provides for low EMI at ultra-low power dissipation even at high frequencies. The FIN1049 can accept LVPECL inputs for translating from LVPECL to LVDS. The En and Enb inputs are AND-ed together to enable / disable the outputs. The enables are common to all four outputs. A single-line driver and single-line receiver function is also available in the FIN1019. Ordering Information Part Number Operating Temperature Range FIN1049MTCX -40 to +85°C © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 Package 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Packing Method Tape and Reel www.fairchildsemi.com FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver April 2013 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver Pin Configuration Functional Diagram Figure 1. Pin Configuration Figure 2. Functional Diagram Pin Definitions Pin # Name Description 2, 3 RIN1+, RIN2+ Non-Inverting LVDS Inputs 1, 4 RIN1-, RIN2- Inverting LVDS Inputs 7, 6 DOUT1+, DOUT2+ Non-Inverting Driver Outputs 8, 5 DOUT1-, DOUT2- Inverting Driver Outputs 16, 9 EN, ENb 15, 14 ROUT1, ROUT2 10, 11 DIN1, DIN2 12 VCC Power Supply (3.3 V) 13 GND Ground Driver Enable Pins for All Outputs LVTTL Output Pins for ROUT1 and ROUT2 LVTTL Input Pins for DIN1 and DIN2 Function Table Inputs Inputs (LVDS)(1) Outputs (LVTTL) EN ENb ROUT1 ROUT2 H L ON H H L H L H RINn+ RINn- Outputs (LVDS) DOUTn+ DOUTn- ON ON ON Z Z Z Z Z Z Z Z L Z Z Z Z L H H Open Current Fail-Safe Condition Legend: H=HIGH Logic Level L=LOW Logic Level or OPEN X=Don't Care Z=High Impedance Note: 1. Any unused receiver Inputs should be left open. © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 +4.6 V VIN LVDS DC Input Voltage -0.5 +4.6 V VOUT LVDS DC Output Voltage -0.5 +4.6 V IOSD Driver Short-Circuit Current (Continuous) TSTG Storage Temperature Range 10 -65 mA +150 °C TJ Max Junction Temperature +150 °C TL Lead Temperature (Soldering, 10 Seconds) +260 °C ESD Human Body Model, JESD22-A114 7000 Machine Model, JESD22-A115 250 V Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VCC Supply Voltage 3.0 3.6 V |VID| Magnitude of Differential Voltage 100 VCC mV Operating Temperature -40 +85 °C TA © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 3 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver Absolute Maximum Ratings Over-supply voltage and operating temperature ranges, unless otherwise specified. All typical values are at TA=25°C and with VCC=3.3 V. Symbol Parameter Conditions Min. Typ. Max. Units 0 35 mV LVDS Input DC Specifications (RIN1+, RIN1-, RIN2+, RIN2-) See Figure 3 and Table 1 VCM=1.2 V, 0.05 V, 2.35 V VTH Differential Input Threshold HIGH VTL Differential Input Threshold LOW VIC Common Mode Voltage Range VID=100 mV, VCC=3.3 V IIN Input Current VCC=0 V or 3.6 V, VIN=0 V or 2.8 V -100 0 VID/2 mV VCC (VID/2) V ±20 mA CMOS/ LVTTL Input DC Specifications (EN, ENb, DIN1, DIN2) VIH Input High Voltage (LVTTL) 2.0 VCC V VIL Input Low Voltage (LVTTL) GND 0.8 V IIN Input Current (EN, ENb, DIN1, DIN2, RINx+, RINx-) VIN=0 V or VCC ±20 µA VIK Input Clamp Voltage VIK=-18 mA -1.5 -0.7 250 350 V LVDS Output DC Specifications (DOUT1+, DOUT1-, DOUT2+, DOUT2-) VOD VOD VOS VOS IOS Output Differential Voltage See Figure 4 VOD Magnitude Change from RL=100 450 mV 35 mV Differential LOW-to-HIGH Driver Enabled Offset Voltage See Figure 4 1.375 V 25 mV DOUT+=0V & DOUT-=0 V, Driver Enabled -9 mA VOD=0 V, Driver Enabled -9 mA 1.125 1.250 Offset Magnitude Change from Differential LOW-to-HIGH Short-Circuit Output Current IOSD IOFF Power-Off Input or Output Current VCC=0 V, VOUT=0 V or VCC ±20 mA IOZD Disabled Output Leakage Current Driver Disabled, DOUT+=0 V or VCC or DOUT-=0V or VCC ±10 mA CMOS/LVTTL Output DC Specifications (ROUT1, ROUT2) VOH Output High Voltage IOH=-2 mA, VID=200 mV VOL Output Low Voltage IOL=2 mA, VID=200 mV 2.7 0.25 V V IOZ Disabled Output Leakage Current Driver Disabled, ROUTn=0 V or VCC ±10 mA ICC Power Supply Current(2) Drivers Enabled, Any Valid Input Condition 25 mA ICCZ Power Supply Current Drivers Disabled 10 mA CIND Input Capacitance LVDS Input 3.0 pF COUT Output Capacitance LVDS Output 4.0 pF CINT Input Capacitance LVTTL Input 3.5 pF Note: 2. Both driver and receiver inputs are static. All LVDS outputs have 100 load. None of the outputs have any lumped capacitive load. © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 4 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver DC Electrical Characteristics Over-supply voltage and operating temperature ranges, unless otherwise specified. All typical values are at T A=25°C and with VCC=3.3 V. Symbol Parameter Conditions Min. Typ. Max. Units Switching Characteristics - LVDS Outputs tPLHD Differential Propagation Delay LOW-to-HIGH See Figure 5, Figure 6 2 ns tPHLD Differential Propagation Delay HIGH-to-LOW 2 ns tTLHD Differential Output Rise Time (20% to 80%) 0.2 1.0 ns tTHLD Differential Output Fall Time (80% to 20%) 0.2 1.0 ns tSK(P) Pulse Skew |tPLH - tPHL| 0.35 ns tSK(LH), tSK(HL) Channel-to-Channel Skew(3) 0.35 ns tSK(PP) Part-to-Part Skew(4) 1 ns tPZHD Differential Output Enable Time, Z-to-HIGH 6 ns tPZLD Differential Output Enable Time, A-to-LOW 6 ns tPHZD Differential Output Disable Time, HIGH-to-Z 3 ns tPLZD Differential Output Disable Time, LOW-to-Z 3 ns fMAXD (5) Maximum Frequency See Figure 7, Figure 8 See Figure 5 200 MHz Switching Characteristics - LVTTL Outputs tPHL Propagation Delay HIGH-to-LOW Measured from 20% to 80% Signal 0.5 1.0 tPLH Propagation Delay LOW-to-HIGH VID=200 mV 0.5 tSK1 Pulse Skew Distributed Load 0 tSK2 Channel-to-Channel Skew CL=15 pF and 50 0 tSK3 Part-to-Part Skew RL=1 k 0 tLHR Transition Time LOW-to-HIGH VOS=1.2 V 0.10 tHLR Transition Time HIGH-to-LOW See Figure 9, Figure 10 tPHZ Disable Time HIGH-to-Z See Figure 11, Figure 12 tPLZ 3.5 ns 1.0 3.5 ns 35 400 ps 50 500 ps 1 ns 0.25 1.40 ns 0.10 0.18 1.40 ns 2.2 4.5 8.0 ns Disable Time LOW-to-Z 1.3 3.5 8.0 ns tPZH Enable Time Z-to-HIGH 1.8 3.0 7.0 ns tPZL Enable Time Z-to-LOW 0.9 1.4 7.0 ns fMAXT (6) Maximum Frequency See Figure 9 200 MHz Notes: 3. tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. 4. tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. 5. fMAXD generator input conditions: tr=tf < 1 ns (10% to 90%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle=45% / 55%, VOD > 250 mV, all channels switch. 6. fMAXT generator input conditions: tr=tf < 1 ns (10% to 90%), 50% duty cycle, VID=200 mV, VCM=1.2 V. Output criteria: duty cycle=45% / 55%, VOH > 2.7 V. VOL < 0.25 V, all channels switching. © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 5 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver AC Electrical Characteristics Notes: 7. Electrostatic Discharge Capability: Human Body Model and Machine Model ESD should be measured using MILSTD-883C method 3015.7 standard. 8. Latch-up immunity should be tested to the EIA/JEDEC Standard Number 78 (EIA/JESD78). Figure 3. Differential Receiver Voltage Definitions Test Circuit Note: 9. CL=15 pF, includes all probe and jig capacitances. Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages Resulting Differential Input Voltage (mV) Applied Voltages (V) Resulting Common Mode Input Voltage (V) VIA VIB VID VIC 1.25 1.15 100 1.2 1.15 1.25 -100 1.2 VCC VCC - 0.1 100 VCC - 0.05 VCC - 0.1 VCC -100 VCC - 0.05 0.1 0.0 100 0.05 0.0 0.1 -100 0.05 1.75 0.65 1100 1.2 0.65 1.75 -1100 1.2 VCC VCC - 1.1 1100 VCC - 0.55 VCC - 1.1 VCC -1100 VCC - 0.55 1.1 0.0 1100 0.55 0.0 1.1 -1100 0.55 Figure 4. LVDS Output Circuit for DC Test Note: 10. RL=100 © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 6 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver Required Specifications and Test Diagrams FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver Required Specifications and Test Diagrams (Continued) Figure 5. LVDS Output Propagation Delay and Transition Time Test Circuit Notes: 11. A: RL=100 12. B: ZO=50 and CT=15 pF distributed. Figure 6. LVTTL Input to LVDS Output AC Waveform © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 7 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver Required Specifications and Test Diagrams (Continued) Figure 7. LVDS Output Enable / Disable Delay Test Circuit Notes: 13. A: RL=100 14. B: ZO=50 and CT=15 pF distributed. 15. R1=1000 , RS=950 16. VTST=2.4 V. Figure 8. LVDS Output Enable / Disable Timing Waveforms © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 8 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver Required Specifications and Test Diagrams (Continued) Figure 9. LVTTL Output Propagation Delay and Transition Time Test Circuit Notes: 17. A: ZO=50 and CT=15 pF distributed. 18. RL=100 and RS=950 Figure 10. LVDS Input to LVTTL Output Propagation Delay and Transition Time Waveforms © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 9 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver Required Specifications and Test Diagrams (Continued) Figure 11. LVTTL Output Enable / Disable Test Circuit Notes: 19. A: ZO=50 and CT=15 pF distributed. 20. RL=100 , R1=1000 , and RS=950 Figure 12. LVTTL Output Enable / Disable Timing Waveforms © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 10 5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 13. 16-Lead, Thin-Shrink Small-Outline Package (TSSOP), JEDEC MO-153, 4.4 mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 11 FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver Physical Dimensions FIN1049 — LVDS Dual-Line Driver with Dual-Line Receiver © 2003 Fairchild Semiconductor Corporation FIN1049 • Rev. 1.0.3 www.fairchildsemi.com 12