Preliminary Revised September 2001 FIN1101 LVDS Single Port High Speed Repeater (Preliminary) General Description Features This single port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. It accepts and outputs LVDS levels with a typical differential output swing of 350 mV which provides low EMI at ultra low power dissipation even at high frequencies. It can directly accept LVPECL, HSTL, and SSTL-2 for translating directly to LVDS. ■ Greater than 800 Mbps full differential path ■ 3.5 ps max random jitter and 135 ps max deterministic jitter ■ 3.3V power supply operation ■ Wide rail-to-rail common mode range ■ Ultra low power consumption ■ LVDS receiver inputs accept LVPECL, HSTL, and SSTL-2 directly ■ Power off protection ■ 6 kV HBM ESD protection ■ Meets or exceed the TA/EIA-644-A LVDS standard ■ Packaged in 8-pin SOIC and US8 (Preliminary) ■ Open circuit, shorted, and terminated fail safe protection Ordering Code: Order Number Package Number FIN1101M M08A FIN1101K8 MAB08A Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 8-Lead US8, 0.7mm x 3.1mm x 2.0mm Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Functional Diagram Pin Descriptions Function Table Pin Name Description Inputs Outputs EN RIN+ RIN− DOUT+ Inverting LVDS Inputs H H L H L Non-Inverting Driver Outputs H L H L H RIN+ Non-Inverting LVDS Inputs RIN− DOUT+ DOUT− Inverting Driver Outputs EN Driver Enable Pin VCC Power Supply GND Ground © 2001 Fairchild Semiconductor Corporation H L or OPEN Fail Safe Case X X DOUT− H L Z Z H = HIGH Logic Level L = LOW Logic Level X = Don't Care Z = High Impedance DS500654 www.fairchildsemi.com FIN1101 LVDS Single Port High Speed Repeater (Preliminary) September 2001 FIN1101 Preliminary Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) −0.5V to +4.6V Recommended Operating Conditions LVDS DC Input Voltage (VIN) −0.5V to +4.6V −0.5V to +4.6V Supply Voltage (VCC) LVDS DC Output Voltage (VOUT) Driver Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Continuous 10 mA (|VID|) −65°C to +150°C 100 mV to VCC −40°C to +85°C Operating Temperature (TA) 150°C Max Junction Temperature (TJ) 3.0V to 3.6V Magnitude of Differential Voltage Lead Temperature (TL) (Soldering, 10 seconds) 260°C ESD (Human Body Model) 6000V ESD (Machine Model) Note 1: The “Absolute Maximum Ratings”: are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. 600V DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Test Conditions Min Typ Max (Note 2) Differential Input Threshold HIGH See Figure 1 VTL Differential Input Threshold LOW See Figure 1 VIH Input High Voltage (EN) 2.0 VCC V VIL Input Low Voltage (EN) GND 0.8 V VOD Output Differential Voltage 450 mV ∆VOD VOD Magnitude Change from RL = 100 Ω, Driver Enabled, Differential LOW-to-HIGH See Figure 2 25 mV VOS Offset Voltage ∆VOS Offset Magnitude Change from 100 Units VTH −100 250 1.125 mV mV 350 1.25 1.375 V 25 mV DOUT + = 0V & DOUT− = 0V, Driver Enabled −8 mA VOD = 0V, Driver Enabled ±6 mA ±20 µA Differential LOW-to-HIGH IOS IIN Short Circuit Output Current Input Current (EN, DINX+, DINX−) VIN = 0V to VCC, Other Input = VCC or 0V (for Differential Inputs) IOFF Power-Off Input or Output Current VCC = 0V, VIN or VOUT = 0V to 4.6V ICCZ Disabled Power Supply Current Drivers Disabled ICC Power Supply Current IPU/PD Output Power-Up/ Power Leakage Current IOZ Disabled Output Leakage Current ±20 µA 5 mA Drivers Enabled, Any Valid Input Condition 15 mA VCC = 0V to 1.5V ±20 µA ±20 µA Driver Disabled, DOUT+ = 0V to 4.6V or DOUT − = 0V to 4.6V VCC− (VID/2) VIC Common Mode Voltage Range CIN Input Capacitance VID/2 3 pF COUT Output Capacitance 4 pF Note 2: All typical values are at TA = 25°C and with VCC = 3.3V. www.fairchildsemi.com 2 V Preliminary FIN1101 AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol tPLHD Parameter Test Conditions Differential Propagation Delay LOW-to-HIGH tPHLD Differential Propagation Delay RL = 100 Ω, CL = 5 pF, HIGH-to-LOW VID = 100 mV to 1100 mV, Min Typ Max (Note 3) Units 0.8 1.8 ns 0.8 1.8 ns tTLHD Differential Output Rise Time (20% to 80%) VIC = V ID/2 to VCC− (VID/2), 0.29 0.58 ps tTHLD Differential Output Fall Time (80% to 20%) Duty Cycle = 50%, 0.29 0.58 ps tSK(P) Pulse Skew |tPLH - tPHL| See Figure 3 and Figure 4 0.2 ns tSK(PP) Part-to-Part Skew (Note 4) fMAX Maximum Frequency (Note 5) tPZHD Differential Output Enable Time from Z to HIGH 10 tPZLD Differential Output Enable Time from Z to LOW RL = 100 Ω, CL = 5 pF, 10 ns tPHZD Differential Output Disable Time from HIGH to Z See Figure 5 and Figure 6 10 ns tPLZD Differential Output Disable Time from LOW to Z 10 ns tDJ LVDS Data Jitter, 100 135 ps 2.2 3.5 ps tRJ 0.5 800 VID = 300 mV, PRBS = 223 − 1, Deterministic VIC = 1.2V at 800 Mbps LVDS Clock Jitter, Random VID = 300 mV (RMS) VIC = 1.2 V at 400 MHz ns Mbps ns Note 3: All typical values are at TA = 25°C and with VCC = 3.3V. Note 4: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 5: Passing criteria for maximum frequency is the output VOD > 250 mV and the duty cycle is better than 45% / 55% with all channels switching. 3 www.fairchildsemi.com FIN1101 Preliminary Required Specifications: 5. Latch-up immunity should be tested to the EIA/JEDEC standard number 78 (EIA/JESD78). 1. When the true and complement LVDS outputs (having a 100Ω connected between outputs) are connected to 3.75kΩ resistors and the common point of those 3.75kΩ resistors are connected to a voltage source that sweeps from 0V to 2.4V, the DC VOD and ∆VOD are still maintained (see Figure 1). 6. When the true and complement LVDS outputs are connected with 49.9Ω resistors each to common point, then the common point does not vary by more than 150mV under all process, temperature, and voltage conditions when the outputs switch either from LOW-to-HIGH or from HIGH-to-LOW (see Figure 3, CL = board + pin stray capacitance) 2. When the true and complement LVDS inputs are connected together to a voltage source that sweeps from 0V to 2.4V with respect to the common ground, then the absolute value of the difference in input leakage current is less than 6µA (see Figure 2) 7. When the LVDS inputs are not driven either in High Impedance, shorted together, or terminated with a resistor, the outputs go the HIGH state (DOUT+ = H, DOUT− = L) and the LVDS inputs do not sink or source more than 20µA. 3. Pull-down resistor is required on the enable (EN) input. 4. Human Body Model ESD and Machine Model ESD should be measured using MIL-STD-883C method 3015.7 standard. FIGURE 1. Common Mode Supply Test Circuit FIGURE 2. Receiver Input Balance Measurements FIGURE 3. Dynamic VOS Test Circuit and Waveforms FIGURE 4. Differential Receiver Voltage Definitions and Propagation I and Transition Time Test Circuit www.fairchildsemi.com 4 Preliminary FIN1101 Required Specifications: (Continued) Note A: All input pulses have frequency = 10MHz, tR or tF < = 1ns Note B: CL includes all probe and jig capacitances FIGURE 5. Differential Driver DC Test Circuit FIGURE 6. Differential Driver Propagation Delay and Transition Time Test Circuit Note A: All input pulses have frequency = MHz, tR or tF < = 2 ns Note B: CL includes all probe and jig capacitances FIGURE 8. Differential Driver Enable and Disable Test Circuit FIGURE 7. AC Waveforms FIGURE 9. Enable and Disable AC Waveforms 5 www.fairchildsemi.com FIN1101 Preliminary Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A www.fairchildsemi.com 6 Preliminary FIN1101 LVDS Single Port High Speed Repeater (Preliminary) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead US8, 0.7mm x 3.1mm x 2.0mm Package Number MAB08A (Preliminary) Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com