FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Receiver Features Description Greater than 400Mbs Data Rate This dual receiver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra-low power dissipation, even at high frequencies. This device is ideal for high-speed transfer of clock and data signals. Meets or Exceeds the TIA/EIA-644 LVDS Standard Power Supply Operation: 3.3V Maximum Differential Pulse Skew: 0.4ns Maximum Propagation Delay: 2.5ns Low-Power Dissipation Power-Off Protection Fail-Safe Protection for Open-Circuit, Shorted, and Terminated Conditions The FIN1028 can be paired with its companion driver, the FIN1027, or any other LVDS driver. Flow-through Pinout Simplifies PCB Layout Ordering Information Part Number Operating Temperature Range FIN1028M -40 to +85°C FIN1028MX -40 to +85°C Package Packing Method RoHS 8-Lead Small Outline Package (SOIC) JEDEC MS-012, 0.150 inch Narrow Trays RoHS 8-Lead Small Outline Package (SOIC) JEDEC MS-012, 0.150 inch Narrow Tape and Reel Eco Status For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2001 Fairchild Semiconductor Corporation FI1028 • Rev. 1.0.2 www.fairchildsemi.com FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Receiver August 2008 FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Reciever Pin Configuration Figure 1. SOIC Pin Assignments (Top View) Pin Definitions Pin # Name Description 1 RIN1- Inverting LVDS Input 2 RIN1+ Non-Inverting LVDS Input 3 RIN2+ Non-Inverting LVDS Input 4 RIN2- Inverting LVDS Input 5 GND Ground 6 ROUT2 LVTTL Data Output 7 ROUT1 LVTTL Data Output 8 VCC Power Supply Function Table Inputs Outputs RIN+ RIN- ROUT LOW HIGH LOW LOW HIGH HIGH Fail-Safe Conditions (1) HIGH Note: 1. Fail-safe=open, shorted, terminated. © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC RINx+, RINx- Parameter Min. Max. Unit Supply Voltage -0.5 4.6 V DC Input Voltage -0.5 4.7 V ROUTx DC Output Voltage -0.5 6.0 V IO DC Output Current 16 mA TSTG +150 °C TJ Maximum Junction Temperature +150 °C TL Lead Temperature, Soldering 10 Seconds +260 °C Human Body Model, JESD22-A114 ≥6500 Machine Model, JESD22-A115 ≥300 ESD Storage Temperature Range -65 V Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Max. Unit 3.0 3.6 V 0 VCC V Magnitude of Differential Voltage 100 VCC mV VIC Common-Mode Input Voltage 0.05 2.35 V TA Operating Temperature -40 +85 °C VCC Supply Voltage VIN Input Voltage ⏐VID⏐ © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 Min. FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Reciever Absolute Maximum Ratings www.fairchildsemi.com 3 Typical values are at TA=25°C and with VCC=3.3V. Over-supply voltage and operating temperature ranges, unless otherwise noted. Symbol VTH Parameter Conditions Differential Input Threshold HIGH Min. Typ. Figure 2, Table 1 Max. Units 100 mV VTL Differential Input Threshold LOW Figure 2, Table 1 IIN Input Current VIN=0V or VCC ±20 µA Power-off Input Current VCC=0V, VIN=0V or 3.6V ±20 µA II(OFF) IOH=-100µA -100 mV VCC-0.2 VOH Output HIGH Voltage VOL Output LOW Voltage VIK Input Clamp Voltage IIK=-18mA ICC Power Supply Current RIN+=1V and RIN-=1.4V or RIN+=1.4V and RIN-=1V CIN Input Capacitance 4 pF Output Capacitance 6 pF COUT IOH=-8mA V 2.4 IOL=100µA 0.2 IOL=8mA 0.5 -1.5 V V 9 mA DC Electrical Characteristics Typical values are at TA=25°C and with VCC=3.3V. Over-supply voltage and operating temperature ranges, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units tPLH Differential Propagation Delay, LOW-to-HIGH 0.9 2.5 ns tPHL Differential Propagation Delay, HIGH-to-LOW 0.9 2.5 ns tTLH Output Rise Time (20% to 80%) tTHL Output Fall Time (80% to 20%) tSK(P) Pulse Skew ⏐tPLH - tPHL⏐ tSK(LH), tSK(HL) tSK(PP) ⏐VID⏐=400mV, CL=10pF Figure 2, Figure 3 (2) Channel-to-Channel Skew (3) Part-to-Part Skew 0.5 FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Reciever DC Electrical Characteristics ns 0.5 ns 0.4 ns 0.3 ns 1.0 ns Notes: 2. tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. 3. tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 www.fairchildsemi.com 4 Notes: 4. CL includes all probe and fixture capacitances. 5. All input pulses have frequency = 10MHz, tR or tF=1ns. Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) Resulting Differential Input Voltage (mV) Resulting Common Mode Input Voltage (V) VIA VIB VID VIC 1.25 1.15 100 1.2 1.15 1.25 -100 1.2 2.4 2.3 100 2.35 2.3 2.4 -100 2.35 0.1 0 100 0.05 0 0.1 -100 0.05 1.5 0.9 600 1.2 0.9 1.5 -600 1.2 2.4 1.8 600 2.1 1.8 2.4 -600 2.1 0.6 0 600 0.3 0 0.6 -600 0.3 FIN1028 —3.3V LVDS 2-Bit High-Speed Differential Receiver Figure 2. Differential Driver Propagation Delay and Transition Time Test Circuit Figure 3. AC Waveforms © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 www.fairchildsemi.com 5 Figure 4. Output High Voltage vs. Power Supply Voltage Figure 5. Output Low Voltage vs. Power Supply Voltage Figure 6. Output Short Circuit Current vs. Power Supply Voltage Figure 7. Power Supply Current vs. Frequency Figure 8. Power Supply Current vs. Ambient Temperature © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 FIN1028 —3.3V LVDS 2-Bit High-Speed Differential Receiver Typical Performance Characteristics Figure 9. Differential Propagation Delay vs. Power Supply Voltage www.fairchildsemi.com 6 Figure 10. Differential Propagation Delay vs. Ambient Temperature Figure 11. Differential Skew (tPLH-tPHL) vs. Power Supply Voltage Figure 12. Differential Skew (tPHL-tPHL) vs. Ambient Temperature Figure 13. Differential Propagation Delay vs. Differential Input Voltage Figure 14. Differential Propagation Delay vs. Common-Mode Voltage Figure 15. Transition Time vs. Power Supply Voltage © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 FIN1028 —3.3V LVDS 2-Bit High-Speed Differential Receiver Typical Performance Characteristics (Continued) www.fairchildsemi.com 7 Figure 16. Transition Time vs. Ambient Temperature Figure 17. Differential Propagation Delay vs. Load Figure 18. Differential Propagation Delay vs. Load Figure 19. Transition Time vs. Load Figure 20. Transition Time vs. Load © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 FIN1028 —3.3V LVDS 2-Bit High-Speed Differential Receiver Typical Performance Characteristics (Continued) Figure 21. Power Supply Current vs. Power Supply Voltage www.fairchildsemi.com 8 5.00 4.80 A 0.65 3.81 5 8 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.25 0.10 1.75 MAX R0.10 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 FIN1028 —3.3V LVDS 2-Bit High-Speed Differential Receiver Physical Dimensions C OPTION A - BEVEL EDGE GAGE PLANE R0.10 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 Figure 22. 8-Lead, Small Outline Package (SOIC), JEDEC MS-012, 0.150-inch, Narrow Body Click here for tape and reel specifications, available at: http://www.fairchildsemi.com/products/discrete/pdf/soic8_tr.pdf Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 www.fairchildsemi.com 9 FIN1028 —3.3V LVDS 2-Bit High-Speed Differential Receiver © 2001 Fairchild Semiconductor Corporation FIN1028 • Rev. 1.0.2 www.fairchildsemi.com 10