NC7ST08M5X

NC7ST08
TinyLogic HST 2-Input AND Gate
General Description
Features
The NC7ST08 is a single 2-Input high performance CMOS
AND Gate, with TTL-compatible inputs. Advanced Silicon
Gate CMOS fabrication assures high speed and low power
circuit operation. ESD protection diodes inherently guard
both inputs and output with respect to the VCC and GND
rails. High gain circuitry offers high noise immunity and
reduced sensitivity to input edge rate. The TTL-compatible
inputs facilitate TTL to NM OS/CMOS interfacing. Device
performance is similar to MM74HCT but with 1/2 the output
current drive of HC/HCT.
■ Space saving SOT23 or SC70 5-lead package
■ Ultra small MicroPak leadless package
■ High Speed:
tPD 6 ns (typ), VCC = 5V, CL = 15 pF, TA = 25°C
■ Low Quiescent Power, ICC < 1 µA, VCC = 5.5V
■ Balanced Output Drive; 2 mA IOL, −2 mA IOH
■ TTL-compatible inputs
Ordering Code:
Order
Package
Product Code
Number
Number
Top Mark
NC7ST08M5X
MA05B
8S08
NC7ST08P5X
MAA05A
T08
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide
3k Units on Tape and Reel
NC7ST08L6X
MAC06A
NN
6-Lead MicroPak, 1.0mm Wide
5k Units on Tape and Reel
Package Description
Supplied As
5-Lead SOT23, JEDEC MO-178, 1.6mm
3k Units on Tape and Reel
Connection Diagrams
Logic Symbol
IEEE/IEC
Pin Assignments for SC70 and SOT23
Pin Descriptions
Pin Names
Description
A, B
Inputs
Y
Output
NC
No Connect
(Top View)
Pad Assignment for MicroPak
Function Table
Y = AB
Inputs
Output
A
B
L
L
Y
L
L
H
L
H
L
L
H
H
H
H = HIGH Logic Level
(Top Thru View)
L = LOW Logic Level
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2004 Fairchild Semiconductor Corporation
DS012182
www.fairchildsemi.com
NC7ST08 TinyLogic HST 2-Input AND Gate
January 1997
Revised August 2004
NC7ST08
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
Supply Voltage
4.5V to 5.5V
@VIN < −0.5V
−20 mA
Input Voltage (VIN)
0.0V to VCC
@VIN ≥ VCC + 0.5V
+20 mA
Output Voltage (VOUT)
DC Input Voltage (VIN)
−0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
Input Rise and Fall Time (tr, tf)
VOUT < −0.5V
−20 mA
VOUT > VCC + 0.5V
+20 mA
Output Voltage (VOUT)
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
VCC = 5.0V
0 ns to 500 ns
Thermal Resistance (θJA)
−0.5V to VCC + 0.5V
DC Output Source or Sink Current
SOT23-5
300°C/W
SC70-5
425°C/W
±12.5 mA
(IOUT)
DC VCC or Ground Current per
±25 mA
Supply Pin (ICC or IGND)
−65°C to +150°C
Storage Temperature (TSTG)
150°C
Junction Temperature (TJ)
Lead Temperature (TL);
SOT23-5
200 mW
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of circuits outside the databook specifications.
SC70-5
150 mW
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
260°C
(Soldering, 10 seconds)
Power Dissipation (PD) @+85°C
DC Electrical Characteristics
Symbol
Parameter
TA = +25°C
VCC
(V)
Min
2.0
VIH
HIGH Level Input Voltage
4.5–5.5
VIL
LOW Level Input Voltage
4.5–5.5
VOH
HIGH Level Output Voltage
Typ
TA = 40°C to +85°C
Max
Min
Max
2.0
0.8
4.4
4.5
4.4
4.5
4.18
4.35
4.13
Conditions
V
0.8
4.5
Units
V
IOH = −20 µA
V
IOH = −2 mA
VIN = VIH
VOL
LOW Level Output Voltage
4.5
0
0.1
0.1
4.5
0.10
0.26
0.33
IOL = 20 µA
V
IOL = 2 mA
VIN = VIL
IIN
Input Leakage Current
5.5
±0.1
±1.0
ICC
Quiescent Supply Current
5.5
1.0
10.0
µA
VIN = VCC or GND
ICCT
ICC per Input
5.5
2.0
2.9
mA
One Input VIN = 0.5V or 2.4V,
µA
0 ≤ VIN ≤ 5.5V
Other Input VCC or GND
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2
Symbol
tPLH,
Parameter
Propagation Delay
TA = +25°C
VCC
(V)
Min
5.0
tPHL
4.5
5.5
tTLH,
Output Transition Time
tTHL
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
TA = 40°C to +85°C
Typ
Max
Min
Max
4
12
6
17
6
16
20
12
27
31
5
14
18
11
26
30
5.0
4
10
4.5
11
25
31
5.5
10
21
26
Open
5.0
10
6
Units
Conditions
Figure
Number
ns
CL = 15 pF
ns
CL = 50 pF
ns
CL = 15 pF
ns
CL = 50 pF
Figures
1, 3
(Note 3)
Figure 2
Figures
1, 3
pF
pF
Note 3: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (C PD)(VCC)(fIN) + (ICCstatic).
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tw = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 3. AC Waveforms
Input = AC Waveform; PRR = variable; Duty Cycle = 50%
FIGURE 2. ICCD Test Circuit
3
www.fairchildsemi.com
NC7ST08
AC Electrical Characteristics
NC7ST08
Tape and Reel Specification
TAPE FORMAT for SC70 and SOT23
Package
Tape
Designator
M5X, P5X
Number
Cavity
Section
Cavities
Status
Cover Tape
Status
Leader (Start End)
125 (typ)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
Package
SC70-5
SOT23-5
Tape Size
8 mm
8 mm
www.fairchildsemi.com
DIM A
DIM B
0.093
0.096
(2.35)
(2.45)
0.130
0.130
(3.3)
(3.3)
DIM F
DIM Ko
0.138 ± 0.004 0.053 ± 0.004
(3.5 ± 0.10)
(1.35 ± 0.10)
0.138 ± 0.002 0.055 ± 0.004
(3.5 ± 0.05)
4
(1.4 ± 0.11)
DIM P1
DIM W
0.157
0.315 ± 0.004
(4)
(8 ± 0.1)
0.157
0.315 ± 0.012
(4)
(8 ± 0.3)
TAPE FORMAT for MircoPak
Package
(Continued)
Tape
Number
Cavity
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
Designator
L6X
Cover Tape
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
REEL DIMENSIONS inches (millimeters)
Tape
Size
8 mm
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165
0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40 + 1.50/−0.00)
(14.40)
(W1 + 2.00/−1.00)
5
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NC7ST08
Tape and Reel Specification
LTR
BY/APP'D
11208
12/07/95
TL
REDRAW PER CURRENT STANDARD
11531
07/31/96
LUA
4
5
5
DATE
E.C.N.
RELEASE TO DOCUMENT CONTROL
B
C
3.00
2.80
DESCRIPTION
A
REDRAW AS PER JEDEC NEW ISSUE FROM A TO
B. CHANGE DRAWING TEMPLATE FROM
LANDSCAPE TO PORTRAIT. CHANGE DIMENSION
UNIT FROM INCHES TO MILLIMETERS.
CHANGED BOTTOM VIEW TO TOP VIEW,
REMOVED DATE FROM NOTES, ADDED NOTE C,
CHANGED FONT STYLE
BODY THICKNESS, TERMINAL THICKNESS, PACKAGE HEIGHT ADJUSTED TO MEET JEDEC STD
27 JUNE 07
L.HUEBENER
17 JULY 07
L.HUEBENER
SYMM
CL
0.95
0.95
A
4
B
3.00
2.60
1.70
1.50
1
2
2.60
3
(0.30)
1.00
0.50
0.30
0.95
1.90
0.20
C A B
0.70
TOP VIEW
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.30
0.90
1.45 MAX
0.15
0.05
0.22
0.08
C
0.10 C
NOTES: UNLESS OTHEWISE SPECIFIED
GAGE PLANE
A) THIS PACKAGE CONFORMS TO JEDEC
MO-178, ISSUE B, VARIATION AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) MA05Brev5
0.25
8°
0°
17 JULY 07
L.HUEBENER
0.55
0.35
0.60 REF
19 JULY 07
H.ALLEN
5LD,SOT23,JEDEC
MO-178,1.6MM
SEATING PLANE
NA
MM
FORMERLY:
NA
N/A
5
MKT-MA05B
SHEET :
1
OF 1
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Definition of Terms
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Product Status
Advance Information
Formative / In Design
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
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The datasheet is for reference information only.
Rev. I62
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