FAN6747WALMY Highly Integrated Green-Mode PWM Controller Description Features The highly integrated FAN6747WA PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary Green-Mode function provides off-time modulation to decrease the switching frequency with load condition. High-Voltage Startup Built-in 8ms Soft-Start Function Peak-Current Mode Operation with Cycle-by-Cycle Current Limiting Low Startup Current: 30 µA PWM Frequency Decreasing at Green-Mode AC-Line Brownout Protection by HV Pin Constant Output Power Limit by HV Pin (Full AC-Line Range) Under zero-load condition, the power supply enters Burst Mode. Burst frequency can be low to reduce power. Green Mode enables the power supply to meet international power conservation requirements. Leading-Edge Blanking (LEB) Short-Circuit Protection (SCP) with 15 ms Debounce Time as Output Short Low Operating Current: 1.7 mA Over-Temperature Protection (OTP) with External Negative-Temperature-Coefficient (NTC) Thermistor VDD Over-Voltage Protection (OVP) Internal Latch Circuit for OVP, OTP, SCP, and OCP Applications General-purpose switched-mode power supplies (SMPS) and flyback power converters, including: Power Adapters AC/DC NB Adapters SMPS with Peak-Current Output, such as for Printers, Scanners, and Motor Drivers Open-Frame SMPS The FAN6747WA is specially designed for SMPS with peak-current output. It incorporates a cycle-by-cycle current limiting and Over-Current-Protection (OCP) that can handle peak load with a debounce time. Once the current is over the threshold level, it triggers the first counter for 15ms and checks if VDD is below 11.5V. If it is, the PWM latches off for SCP. If VDD is higher than 11.5 V; it keeps counting for 860 ms, then the PWM latches off for OCP. FAN6747WA also integrates a frequency-hopping function that helps reduce EMI emission of a power supply with minimum line filters. The built-in synchronized slope compensation helps achieve stable peak-current control. To keep constant output power limit over the universal AC input range, the current limit is adjusted according to AC line voltage detected by the HV pin. The gate output is clamped at 14 V to protect the external MOSFET from over-voltage damage. Other protection functions include AC-line brownout protection with hysteresis and VDD Over-Voltage Protection (OVP). For Over-Temperature Protection (OTP), an external NTC thermistor can be applied to sense the ambient temperature. When OCP, OVP, SCP, or OTP is activated, an internal latch circuit latches off the controller. The latch is reset when the VDD supply is removed. Ordering Information Part Number Operating Temperature Range FAN6747WALMY -40 to +105°C © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 Package 8-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, .15-Inch Narrow Body Packing Method Tape & Reel www.fairchildsemi.com FAN6747WALMY — Highly Integrated Green-Mode PWM Controller January 2014 Figure 1. Typical Application Internal Block Diagram FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Application Diagram Figure 2. Functional Block Diagram © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 www.fairchildsemi.com 2 : Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Die Run Code F: L = OCP Latch T: Package Type (N =DIP, M = SOP) P: Y = Green Compound M: Manufacturing Flow Code Figure 3. Top Mark Pin Configuration Figure 4. Pin Assignments Pin Definitions Pin # Name 1 GND 2 FB 3 NC No Connection. HV High-Voltage Startup. This pin is connected to the line input via diodes and resistors to meet brownout and high/low line compensation. Once the voltage of the HV pin is lower than the brownout voltage, PWM output is turned off. High/low line compensation dominates the OverCurrent Protection (OCP) level and cycle-by-cycle current limit to solve the unequal OCP level and power-limit problem under universal input. 5 RT Over-Temperature Protection. For Over-Temperature Protection (OTP), an external NTC thermistor is connected from this pin to GND. The impedance of the NTC decreases at high temperatures. Once the voltage of the RT pin drops below the threshold voltage, the controller latches off the PWM. If the RT pin is not connected to the NTC resistor for over-temperature protection, it is recommended to place one 100 KΩ resistor to ground to prevent noise interference. This pin is limited by an internal clamping circuit. 6 SENSE Current Sense. This pin is used to sense the MOSFET current for the Current-Mode PWM and OCP. If the switching current is higher than the OCP threshold and lasts for 860 ms, the controller latches off the PWM. 7 VDD Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external bulk capacitor of typically 10 µF. The threshold voltages for startup and turn-off are 17 V and 10 V, respectively. The operating current is lower than 2 mA. 8 GATE 4 Description Ground. This pin is used for the ground potential of all the pins. A 0.1 µF decoupling capacitor placed between VDD and GND is recommended. FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Marking Information Feedback. The output voltage feedback information from the external compensation circuit is fed into this pin. The PWM duty cycle is determined from this pin and the current-sense signal from Pin 6 (SENSE). Gate Driver Output. The totem-pole output driver for the power MOSFET. It is internally clamped below 14 V. © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 30 V VHV Suddenly Input Voltage to HV Pin within 1 Second (Series connect with RHV) 640 V VL Input Voltage to FB, SENSE, and RT Pins 7.0 V PD Power Dissipation (TA<50°C) 400 mW Thermal Resistance (Junction-to-Ambient) 150 °C/W ΘJA TJ TSTG TL ESD -0.3 Operating Junction Temperature -40 +125 °C Storage Temperature Range -55 +150 °C +260 °C Lead Temperature (Soldering, 10 Seconds) Electrostatic Discharge Capability, All Pins Except HV Pin Human Body Model, JESD22-A114 5 Charge Device Model, JESD22-C101 2 kV Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to the network ground terminal. 3. ESD with HV pin: CDM=1250 V and HBM=1000 V. 4. ESD without HV pin: CDM and HBM sign actual level (no derating). Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter TA Operating Ambient Temperature VHV Input Voltage to HV Pin RHV HV Startup Resistor © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 Min. Typ. -40 150 200 Max. Unit +105 °C 500 V 250 kΩ FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings www.fairchildsemi.com 4 VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit VDD Section 24 V VDD-ON VOP Turn-On Threshold Voltage Continuously Operating Voltage 16 17 18 V VDD-OFF PWM Turn-Off Threshold Voltage 9 10 11 V VDD-OLP Threshold Voltage on VDD for HV JFET Turn-On in Protection Condition 5.5 6.5 7.5 V VDD-LH Threshold Voltage on VDD Pin for Latch-Off Release Voltage 3.5 4.0 4.5 V VDD-AC Threshold Voltage on VDD Pin for Disable AC Recovery to Avoid Startup Failed VDD-OFF +3 VDD-OFF +3.5 VDD-OFF +4 V VDD-SCP Threshold Voltage on VDD Pin for VFB > VFBO Short-Circuit Protection (SCP) VDD-OFF +1 VDD-OFF +1.5 VDD-OFF +2 V After Trigger OCP/ SCP/ OVP/ OTP Holding Current Under Latch-Off Conduction VDD=5 V IDD-ST Startup Current VDD-ON – 0.16 V IDD-OLP Holding Current at PWM-Off Phase VDD-OLP+0.1 V IDD-OP1 Operating Supply Current when PWM Operating IDD-OP2 Operating Supply Current when PWM Stop VDD-OVP Threshold Voltage on VDD Pin for VDD Over-Voltage Protection (Latch-Off) ILH tD-OVP VDD OVP Debounce Time 80 120 μA 30 μA 240 300 μA VDD=20 V, VFB=3 V Gate Open 1.7 2.0 mA VDD=20 V, VFB=3 V Gate Open 1.2 1.5 mA 24 25 26 V 75 160 245 μs 180 VFB > VFB-N 100 FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Electrical Characteristics Continued on the following page… Figure 5. UVLO Specification © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 www.fairchildsemi.com 5 VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit Supply Current Drawn from HV Pin VHV=120 V, VDD=0 V 1.50 2.75 5.00 mA VIN-OFF PWM Turn-Off Threshold DC Source Series R=200 kΩ to HV Pin 92 102 112 V VIN-ON PWM Turn-On Threshold DC Source Series R=200 kΩ to HV Pin 104 114 124 V Change in VIN, VIN-ON - VIN-OFF DC Source Series R=200 kΩ to HV Pin 6 12 18 V VFB > VFB-N 170 205 240 VFB < VFB-G 450 615 780 HV Section IHV ∆VIN tS-CYCLE Line Voltage Sample Cycle tS-TIME Line Voltage Sample Period tD_VIN-OFF PWM Turn-Off Debounce Time 20 VFB > VFB-N 65 VFB < VFB-G 180 μs μs 75 85 ms 235 290 ms Continued on following page… FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) Figure 6. Normal UVLO and Two-Step UVLO Behavior Figure 7. © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 Brownout Circuit www.fairchildsemi.com 6 Figure 8. Brownout Behavior FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) Figure 9. VDD-AC and AC Recovery © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 www.fairchildsemi.com 7 VDD=15V and TA=25°C, unless otherwise specified. Symbol Parameter Condition Min. Center Frequency (VFB>VFB-N) 61 Typ. Max. Unit 65 69 kHz Oscillator Section fOSC Normal PWM Frequency tJTR Hopping Period 4.8 ms fOSC-G Green-Mode Minimum Frequency VFB-N FB Threshold Voltage for Frequency Reduction Beginning VFB-G FB Threshold Voltage for Turn-Off Hopping and Frequency Reduction Destination VOZ-ON FB Threshold Voltage for Zero-Duty Recovery 1.6 1.8 2.0 V VFB-ZDC (VOZ-OFF) FB Threshold Voltage for Zero-Duty 1.5 1.7 1.9 V VOZ-ON - VOZ-OFF FB Voltage Hysteresis for VOZ-ON to VOZ-OFF 50 100 150 mV 20 23 26 kHz Pin, FB Voltage (VFB=VFB-N), fOSC – 5 KHz 2.6 2.8 3.0 V Hopping Range ±3.7 ±4.2 ±4.7 kHz FB Voltage (VFB=VFB-G) 2.1 2.3 2.5 V Hopping Range kHz ±1.45 fDV Frequency Variation vs. VDD VDD=12 V to 22 V Deviation 5 % fDT Frequency Variation vs. Temperature Deviation 5 % TA=-40 to 105°C Continued on following page… FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) Figure 10. PWM Frequency Figure 11. Burst-Mode Diagram © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 www.fairchildsemi.com 8 VDD=15 V and TA=25°C, unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit 1/4.5 1/4.0 1/3.5 V/V Feedback Input Section AV Input-Voltage to Current-Sense Attenuation ZFB Input Impedance 14 16 18 kΩ FB Pin Open Voltage 4.8 5.0 5.2 V FB Open-Loop Protection Threshold Voltage 4.3 4.6 4.9 V 760 860 960 ms 65 200 ns 230 270 310 ns VFBO VFB-OLP tD-OLP Open-Loop Protection Debounce time VFB < VFB-G VFB > VFB-OLP Current Sense Section tPD Delay to Output tLEB Leading-Edge Blanking Time Vlimit-L(Vocp-L) Current Limit at Low Line (VAC-RMS=86 V) VDC=122 V, Series R=200 kΩ to HV 0.790 0.825 0.860 V Vlimit-H(Vocp-H) Current Limit at High Line (VAC-RMS=259 V) VDC=366 V, Series R=200 kΩ to HV 0.690 0.725 0.760 V Period During Startup Startup Time 7 8 9 ms tD-OCP Debounce Time for Output OCP VCS>Vlimit 760 860 960 ms tD-SCP Debounce Time for Output SCP VCS>VOCP and VDD< VDD-SCP 10.5 13.5 16.5 ms 82 87 92 % 1.5 V tSOFT-START PWM Output Section DCYMAX Maximum Duty Cycle VOL Output Voltage Low VDD=15 V, IO=50 mA VOH Output Voltage High VDD=12 V, IO=50 mA tR Rising Time GATE=1 nF 95 ns tF Falling Time GATE=1 nF 30 ns Gate Output Clamping Voltage VDD=22 V VCLAMP 8 FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) V 11.0 13.5 16.0 V 92 100 108 μA 1.00 1.05 1.10 V VFB > VFB-N 14 16 18 ms VFB < VFB-G 40 51 62 ms 0.65 0.70 0.75 V Over-Temperature Protection Section IRT VOTP-LATCHOFF tD_OTP-LATCH VOTP2-LATCHOFF tD_OTP2-LATCH Output Current of RT Pin Threshold Voltage for OverTemperature Protection Over-Temperature Latch-Off Debounce Time Second Threshold Voltage for Over-Temperature Protection Second Over-Temperature Latch-Off Debounce Time © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 VFB > VFB-N 110 185 260 VFB < VFB-G 320 605 890 µs www.fairchildsemi.com 9 Figure 12. Startup Current (IDD-ST) vs. Temperature Figure 13. Operation Supply Current (IDD-OP1) vs. Temperature Figure 14. Start Threshold Voltage (VDD-ON) vs. Temperature Figure 15. Minimum Operating Voltage (VDD-OFF) vs. Temperature Figure 16. Supply Current Drawn from HV Pin (IHV) vs. Temperature Figure 17. HV Pin Leakage Current After Startup (IHV-LC) vs. Temperature Figure 18. Frequency in Normal Mode (fOSC) vs. Temperature Figure 19. Maximum Duty Cycle (DCYMAX) vs. Temperature © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics www.fairchildsemi.com 10 Figure 20. FB Open-Loop Trigger Level (VFB-OLP) vs. Temperature Figure 21. Debounce Time of FB Pin Open-Loop Protection (tD-OLP) vs. Temperature Figure 22. VDD Over-Voltage Protection (VDD-OVP) vs. Temperature Figure 23. Output Current from RT Pin (IRT) vs. Temperature Figure 24. Over-Temperature Protection Threshold Voltage (VOTP) vs. Temperature Figure 25. Over-Temperature Protection Threshold Voltage (VOTP2) vs. Temperature Figure 26. Brown-In (VIN-ON) vs. Temperature Figure 27. Brownout (VIN-OFF) vs. Temperature © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics www.fairchildsemi.com 11 The HV pin can perform current limit to shrink the tolerance of Over-Current Protection (OCP) under the full range of AC voltage to linearly current limit curve, as shown in Figure 28. Startup Current For startup, the HV pin is connected to the line input through an external diode and resistor, RHV, (1N4007 / 200 KΩ recommended). Peak startup current drawn from the HV pin is (VAC × 2 )/RHV and charges the holdup capacitor through the diode and resistor. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the FAN6747WA to maintain the VDD before the auxiliary winding of the main transformer provides the operating current. Operating Current Operating current is around 1.7 mA. The low operating current enables better efficiency, power consumption, and reduces the required VDD hold-up capacitance. Figure 28. Linearly Current Limit Curve Green-Mode Operation Short-Circuit Protection (SCP) The proprietary Green-Mode function provides off-time modulation to reduce the switching frequency in lightload and no-load conditions. VFB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum Green-Mode frequency of around 23 kHz. This protection is used to handle the huge output demand if the power supply output is suddenly shorted to ground. If VDD drops under 11.5 V and the sensed voltage is higher than the limited threshold voltage, SCP is triggered and PWM output is latched off. This latch condition is reset only if VDD is discharged under 4 V. Under-Voltage Lockout (UVLO) Current Sensing / PWM Current Limiting The turn-on and turn-off thresholds are fixed internally at 17 V and 10 V, respectively. During startup, the hold-up capacitor must be charged to 17 V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10 V during startup. This UVLO hysteresis window ensures that the hold-up capacitor is adequate to supply VDD during startup. The cycle-by-cycle current limiting shuts down the PWM immediately when the sense voltage is over the limited threshold voltage (0.825 V at low line). Additionally, when the sense voltage is higher than the OCP threshold (0.825 V at low line), the internal counter counts for 860 ms latches off PWM. When OCP occurs, PWM output is turned off and VDD begins decreasing. When VDD goes below the turn-off threshold (~10V), the controller is totally shut down. VDD continues to discharge below VDD-OLP by IDD-OLP. Then VDD is charged up to the turn-on threshold voltage of 17 V through the startup resistor. When VDD is charged to 17 V, it cycles again. This phenomenon is called two-level UVLO. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Brownout and Constant Power Limited HV Pin The HV pin can detect the peak value of AC line voltage for brownout function and adjust the current-limit level for constant output power limit. Through two fast diodes and startup resistor to sample the AC line voltage, the peak value is refreshed and stored in a register at each sampling cycle. Gate Output / Soft Driving The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 13.5 V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A softdriving waveform is implemented to minimize EMI. 2 / ( × 2 / V 1 8 . 0 S M R F F O C ) (= + ) ) 6 . 1 6 . V1 RH V 9 . 0 S M R VA N O C VA ( ( × )(= 6 . 1 6 . V1 RH Equations 1 and 2 calculate the level of brown-in and brownout in RMS value: ( + ) ) FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Operation Description (1) (2) where RHV is in kΩ. © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 www.fairchildsemi.com 12 Over-Temperature Protection (OTP) VDD over-voltage protection prevents damage due to abnormal conditions. If the VDD voltage is over the overvoltage protection voltage (VDD-OVP) and lasts for tD-OVP, the PWM pulses are disabled until the VDD voltage drops below 4 V, then restarts. Over-voltage conditions are usually caused by open feedback loops. A NTC thermistor, RNTC, in series with a resistor, RA, is connected from the RT pin to GND pin. A constant current IRT is output from this pin. The voltage of the RT pin can be expressed as VRT = IRT • (RNTC + RA), where IRT is 100 µA. The headroom of VRT is limited at around 5 V by internal circuitry. As high ambient temperatures occur, RNTC is smaller, such that the VRT decreases. When VRT is less than 1.05 V (VOTP) but over 0.7 V, the PWM turns off after tD_OTP-LATCH. The other threshold, VDD under 0.7 V, is used for fast shutdown after a short time. If RT pin is not connected to an NTC resistor for Over-Temperature Protection, it is recommended to place one 100 KΩ resistor to ground to prevent noise interference. The RT pin is limited by an internal clamping circuit. Soft-Start For many applications, it is necessary to minimize the inrush current at startup. The built-in 8 ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. Built-In Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6747WA inserts a synchronized, positive-going ramp at every switching cycle. Noise Immunity Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in ContinuousConduction Mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN6747WA, and increasing the power MOS gate resistance improve performance. Constant Output Power Limit When the SENSE voltage across sense resistor Rs reaches the threshold voltage, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current proportional to tPD • VIN / Lp. Since the delay is nearly constant regardless of the input voltage VIN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a power-limiter is controlled by the HV pin to solve the unequal power-limit problem. The power limiter is fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line input than at low-line input. © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 FAN6747WALMY — Highly Integrated Green-Mode PWM Controller VDD Over-Voltage Protection (OVP) www.fairchildsemi.com 13 0.65 A 4.90±0.10 (0.635) 8 5 B 1.75 6.00±0.20 1 PIN ONE INDICATOR 5.60 3.90±0.10 4 1.27 1.27 0.25 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.175±0.75 1.75 MAX 0.22±0.30 C 0.10 0.42±0.09 OPTION A - BEVEL EDGE (0.86) x 45° R0.10 GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 FAN6747WALMY — Highly Integrated Green-Mode PWM Controller Physical Dimensions NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08Arev15 F) FAIRCHILD SEMICONDUCTOR. SEATING PLANE 0.65±0.25 (1.04) DETAIL A SCALE: 2:1 Figure 29. 8-Lead, Small Outline Integrated Circuit (SOIC) Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 www.fairchildsemi.com 14 FAN6747WALMY — Highly Integrated Green-Mode PWM Controller © 2011 Fairchild Semiconductor Corporation FAN6747WALMY • Rev. 1.0.3 www.fairchildsemi.com 15