FAN6754 Highly Integrated Green- Mode PWM Controller Brownout and VLimit Adjustment by HV Pin Features Description The highly integrated FAN6754 PWM controller provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency under light-load conditions. High-Voltage Startup AC Input Brownout Protection with Hysteresis Monitor HV to Adjust VLimit Low Operating Current: 1.7mA Linearly Decreasing PWM Frequency to 22KHz Frequency Hopping to Reduce EMI Emission Fixed PWM Frequency: 65KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Internal Open-Loop Protection GATE Output Maximum Voltage Clamp: 13V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Latch Circuit (OVP, OTP) Open-Loop Protection (OLP); Restart for MR, Latch for ML Built-in 8ms Soft-Start Function Under zero-load and very light-load conditions, FAN6754 saves PWM pulses by entering deep burst mode. This burst mode function enables the power supply to meet international power conservation requirements. FAN6754 integrates a frequency-hopping function internally to reduce EMI emission of a power supply with minimum line filters. Built-in synchronized slope compensation is accomplished by proprietary HV monitor to adjust VLimit for constant output power limit over universal AC input range. Also, the gate output is clamped at 13V to protect the external MOSFET from over-voltage damage. FAN6754 — Highly Integrated Green-Mode PWM Controller March 2010 Other protection functions include AC input brownout protection with hysteresis and VDD over-voltage protection. For over-temperature protection, an external NTC thermistor can be applied to sense the external switcher’ s temperature. When VDD OVP are activated, an internal latch circuit is used to latch-off the controller. The latch mode is reset when the VDD supply is removed. FAN6754 is available in an 8-pin SOP package. Applications General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Ordering Information Part Number FAN6754MRMY FAN6754MLMY Operating Temperature Range Eco Status Package Packing Method -40 to +105°C Green 8-Pin, Small Outline Package (SOP) Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 www.fairchildsemi.com Figure 1. Typical Application Internal Block Diagram FAN6754 — Highly Integrated Green-Mode PWM Controller Application Diagram Figure 2. Functional Block Diagram © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 www.fairchildsemi.com 2 F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die Run Code T - Package Type (M=SOP) P - Y: Package (Green) M - Manufacture Flow Code ZXYTT 6754ML TPM ZXYTT 6754MR TPM Figure 3. Top Mark Pin Configuration SOP-8 GND 1 8 GATE FB 2 7 VDD NC 3 6 SENSE HV 4 5 RT Figure 4. Pin Configuration (Top View) FAN6754 — Highly Integrated Green-Mode PWM Controller Marking Information Pin Definitions Pin # Name 1 GND Description Ground. This pin is used for the ground potential of all the pins. A 0.1µF decoupling capacitor placed between VDD and GND is recommended. 2 FB Feedback. The output voltage feedback information from the external compensation circuit is fed into this pin. The PWM duty cycle is determined by this pin and the current-sense signal from Pin 6. FAN6754 performs an open-loop protection (OLP); if the FB voltage is higher than a threshold voltage (around 4.6V) for more than 55ms, the controller latches off the PWM. 3 NC No Connection. 4 HV High Voltage Startup. This pin is connected to the line input via a 1N4007 and 200k0 resistors to achieve brownout and high/low line compensation. Once the voltage on the HV pin is lower than the brownout voltage, PWM output turns off. High/low line compensation dominates the cycle-by-cycle current limiting to achieve constant output power limiting with universal input. 5 RT Over-Temperature Protection. An external NTC thermistor is connected from this pin to GND. The impedance of the NTC decreases at high temperatures. Once the voltage on the RT pin drops below the threshold voltage, the controller latches off the PWM. 6 SENSE Current Sense. This pin is used to sense the MOSFET current for the current-mode PWM and current limiting. 7 VDD Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external bulk capacitor of typically 47µF. The threshold voltage for turn-on and turn-off is 16.5V and 9V, respectively. The operating current is lower than 2mA. 8 GATE Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped below 13V. © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. (1, 2) Max. Unit 30 V VVDD DC Supply Voltage VFB FB Pin Input Voltage -0.3 7.0 V SENSE Pin Input Voltage -0.3 7.0 V VRT RT Pin Input Voltage -0.3 7.0 V VHV HV Pin Input Voltage 500 V PD Power Dissipation (TA＜50°C) 400 mW ΘJA Thermal Resistance (Junction-to-Air) 150 °C/W TJ Operating Junction Temperature -40 +125 °C Storage Temperature Range -55 +150 °C +260 °C 4.5 kV 1500 V VSENSE TSTG TL ESD Lead Temperature (Wave Soldering or IR, 10 Seconds) Human Body Model, Electrostatic Discharge Capability, JESD22-A114 All pins except HV pin Charged Device Model, JESD22-C101 Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. FAN6754 — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA RHV Parameter Conditions Min. Operating Ambient Temperature -40 HV Startup Resistor 150 © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 Typ. 200 Max. Unit +105 °C 250 kΩ www.fairchildsemi.com 4 VDD=15V and TA=25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units 24 V VDD Section VOP Continuously Operating Voltage VDD-ON Start Threshold Voltage VDD-OFF Minimum Operating Voltage 15.5 16.5 17.5 V 8 9 10 V VDD-OLP IDD-OLP Off Voltage 5.5 6.5 7.5 V VDD-LH Threshold Voltage on VDD Pin for Latch-Off Release Voltage 3.5 4.0 4.5 V VDD-AC Threshold Voltage on VDD Pin for Disable AC recovery to avoid Startup Failed VDD-OFF +2.5 VDD-OFF +3.0 VDD-OFF +3.5 V 30 µA IDD-ST Startup Current VDD-ON – 0.16V IDD-OP1 Operating Supply Current when PWM operation VDD=20V, FB=3V Gate Open 1.7 2.0 mA IDD-OP2 Operating Supply Current when Gate Stop VDD=20V, FB=3V 1.2 1.5 mA ILH Operating Current at PWM-Off Phase Under Latch-Off Conduction VDD=5V 30 60 90 µA IDD-OLP Internal Sink Current Under LatchVDD-OLP+0.1V Off Conduction 170 200 230 µA VDD-OVP VDD Over-Voltage Protection 24 25 26 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 75 165 255 µs 1.50 2.75 4.00 mA FAN6754 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics HV Section Supply Current from HV Pin VAC=90V(VDC=120V), VDD=0V VAC-OFF Brownout Threshold DC Source Series R=200kΩ to HV Pin See Equation 1 92 102 112 V VAC-ON Brownin Threshold DC Source Series R=200kΩ to HV Pin See Equation 2 104 114 124 V △VAC VAC-ON - VAC-OFF DC Source Series R=200kΩ to HV Pin 6 12 18 V tS-CYCLE Line Voltage Sample Cycle tH-TIME Line Voltage Hold Period IHV tD-AC-OFF PWM Turn-off Debounce Time FB > VFB-N 220 FB < VFB-G 650 μs 20 μs FB > VFB-N 65 75 85 ms FB < VFB-G 180 235 290 ms Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 www.fairchildsemi.com 5 VDD=15V and TA=25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Oscillator Section fOSC Frequency in Normal Mode tHOP Hopping Period fOSC-G 61 65 69 Hopping Range ±3.7 ±4.2 ±4.7 FB > VFB-N 3.9 4.4 4.9 FB=VFB-G 10.2 11.5 12.8 ms 19 22 25 KHz Center Frequency Green-Mode Frequency KHz ms fDV Frequency Variation vs. VDD Deviation VDD=11V to 22V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-40 to +105°C 5 % 1/3.5 V/V Feedback Input Section AV Input Voltage to Current-Sense Attenuation ZFB Input Impedance VFB-OPEN Output High Voltage VFB-OLP 1/4.5 FB Pin Open 1/4.0 14 16 18 kΩ 4.8 5.0 5.2 V FB Open-Loop Trigger Level 4.3 4.6 4.9 V tD-OLP Delay Time of FB Pin Open-Loop Protection 50 55 60 ms VFB-N Green-Mode Entry FB Voltage Pin, FB Voltage (FB =VFB-N) 2.6 2.8 3.0 V Hopping Range ±3.7 ±4.2 ±4.7 kHz Pin, FB Voltage (FB =VFB-G) 2.1 2.3 2.5 V Hopping Range ±1.27 ±1.45 ±1.62 kHz VFB-G Green-Mode Ending FB Voltage VFB-ZDCR FB Threshold Voltage for Zero-Duty Recovery 1.9 2.1 2.3 V VFB-ZDC FB Threshold Voltage for Zero-Duty 1.8 2.0 2.2 V FAN6754 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) Continued on the following page… PWM Frequency fOSC fOSC-G VFB-ZDC VFB-ZDCR VFB-G VFB-N VFB Figure 5. VFB vs. PWM Frequency © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 www.fairchildsemi.com 6 VDD=15V and TA=25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units 100 250 ns 230 280 330 ns Current-Sense Section tPD Delay to Output tLEB Leading Edge Blanking Time VLimit-L Current Limit at Low Line (VAC=86V) VDC=122V, Series R=200kΩ to HV 0.43 0.46 0.49 V VLimit-H Current Limit at High Line (VAC=259V) VDC=366V, Series R=200kΩ to HV 0.36 0.39 0.42 V Period During Soft-Start Time Startup Time 7 8 9 ms 86 89 92 % 1.5 V tSS GATE Section DCYMAX Maximum Duty Cycle VGATE-L Gate Low Voltage VDD=15V, IO=50mA VGATE-H Gate High Voltage VDD=12V, IO=50mA 8 V tr Gate Rising Time VDD=15V, CL=1nF 100 ns tf Gate Falling Time VDD=15V, CL=1nF 50 ns Gate Output Clamping Voltage VDD=22V VGATECLAMP 9 13 17 V RT Section RRT VRTTH1 VRTTH2 Internal Resistor from RT Pin Over-Temperature Protection Threshold Voltage tD-OTP1 Over-Temperature Latch-Off Debounce tD-OTP2 © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 9.50 10.55 11.60 KΩ 0.7V ＜ VRT ＜ 1.05V, after 12ms Latch Off 1.000 1.035 1.070 V VRT ＜ 0.7V, After 100µs Latch Off 0.65 0.70 0.75 V VRTTH2 ＜ VRT ＜ VRTTH1 FB > VFB-N 14 16 18 VRTTH2 ＜ VRT ＜ VRTTH1 FB < VFB-G 40 51 62 VRT< VRTTH2, FB > VFB-N 110 185 260 VRT< VRTTH2, FB < VFB-G 320 605 890 FAN6754 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) ms µs www.fairchildsemi.com 7 VDD=15V and TA=25°C unless otherwise noted. Figure 6. Brownout Circuit FAN6754 — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) Figure 7. Brownout Behavior Figure 8. VDD-AC and AC Recovery © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 www.fairchildsemi.com 8 45 4 40 3.5 3 IDD-OP1 (mA) IDD-ST (μA) 35 30 25 20 2.5 2 1.5 15 1 10 0.5 5 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃ ) 18 11 17.5 10.5 50 65 80 95 110 125 10 17 V DD-OFF (V) VDD-ON (V) 35 Figure 10. Operation Supply Current (IDD-OP1) vs. Temperature Figure 9. Startup Current (IDD-ST) vs. Temperature 16.5 16 9.5 9 8.5 15.5 8 15 7.5 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 Temperature (℃ ) 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 11. Start Threshold Voltage (VDD-ON) vs. Temperature Figure 12. Minimum Operating Voltage (VDD-OFF) vs. Temperature 7 3.5 6 3 IHV-LC (uA) 5 IHV (mA) 20 Temperature (℃ ) 4 3 2 FAN6754 — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics 2.5 2 1.5 1 1 0 0.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃ ) 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 13. Supply Current Drawn from HV Pin (IHV) vs. Temperature Figure 14. HV Pin Leakage Current After Startup (IHV-LC) vs. Temperature 70 100 69 68 95 DCYMAX (%) fOSC (KHz) 67 66 65 64 63 90 85 62 61 60 80 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 Temperature (℃ ) -10 5 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 15. Frequency in Normal Mode (fOSC) vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 -25 Figure 16. Maximum Duty Cycle (DCYMAX) vs. Temperature www.fairchildsemi.com 9 70 5.5 65 5 60 tD-OLP (ms) V FB-OLP (V) 6 4.5 4 3.5 55 50 45 3 40 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃ ) 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 17. FB Open-Loop Trigger Level (VFB-OLP) vs. Temperature Figure 18. Delay Time of FB Pin Open-Loop Protection (tD-OLP) vs. Temperature 28 120 27 110 25 IRT (uA) V DD-OVP (V) 26 24 23 22 100 90 80 21 20 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃ ) 35 50 65 80 95 110 125 Figure 20. Output Current from RT Pin (IRT) vs. Temperature 1.2 0.9 1.1 0.8 VRTTH2 (V) VRTTH1 (V) Figure 19. VDD Over-Voltage Protection (VDD-OVP) vs. Temperature 1 0.9 0.8 -40 20 Temperature (℃ ) FAN6754 — Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics (Continued) 0.7 0.6 0.5 -30 -15 0 25 50 75 85 100 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (℃ ) Temperature (℃) Figure 21. Over-Temperature Protection Threshold Voltage (VRTTH1) vs. Temperature Figure 22. Over-Temperature Protection Threshold Voltage (VRTTH2) vs. Temperature 120 120 115 V AC-OFF (V) VAC-ON (V) 115 110 110 105 100 105 95 100 90 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 Temperature (℃ ) -10 5 20 35 50 65 80 95 110 125 Temperature (℃ ) Figure 23. Brown-in (VAC-ON) vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 -25 Figure 24. Brownout (VAC-OFF) vs. Temperature www.fairchildsemi.com 10 Startup Current Gate Output / Soft Driving For startup, the HV pin is connected to the line input through an external diode and resistor; RHV, (1N4007 / 150KΩ recommended). Peak startup current drawn from the HV pin is (VAC × 2 ) / RHV and charges the hold-up capacitor through the diode and resistor. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the FAN6754 to keep the VDD until the auxiliary winding of the main transformer provides the operating current. The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 13V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI. Soft-Start For many applications, it is necessary to minimize the inrush current at startup. The built-in 8ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. Operating Current Operating current is around 1.7mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance. Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6754 inserts a synchronized, positive-going, ramp at every switching cycle. Green-Mode Operation The proprietary green-mode function provides off-time modulation to reduce the switching frequency in lightload and no-load conditions. VFB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage (VFB-N), switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz. Constant Output Power Limit When the SENSE voltage across sense resistor RSENSE reaches the threshold voltage, around 0.46V for low-line condition, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current proportional to tPD • VIN / LP. Since the delay is nearly constant regardless of the input voltage VIN, higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a power-limiter is controlled by the HV pin to solve the unequal power-limit problem. The power limiter is fed to the inverting input of the current limiting comparator. This results in a lower current limit at highline inputs than at low-line inputs. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and VFB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB–0.6)/4, the switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.46V for low-line output power limit. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Brownout and Constant Power Limited by HV Pin Unlike previous PWM controllers, FAN6754’s HV pin can detect the AC line voltage brownout function and adjust the current limit level. Using a fast diode and startup resistor to sample the AC line voltage, the peak value refreshes and is stored in a register at each sampling cycle. When internal update time is met, this peak value is used for brownout and current-limit level judgment. Equation 1 and 2 calculate the level of brownin or brownout converted to RMS value. For power saving, FAN6754 enlarges the sampling cycle to lower the power loss from HV sampling at light load condition. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 16.5V and 9V, respectively. During startup, the holdup capacitor must be charged to 16.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD until the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 9V during startup. This UVLO (RHV +1.6) hysteresis window ensures that hold-up capacitor is V )/ 2 AC - ON (RMS) = ( 0.9V × 1.6 adequate to supply VDD during startup. VAC - OFF (RMS) = ( 0.81V × © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 FAN6754 — Highly Integrated Green-Mode PWM Controller Functional Description (1) (RHV + 1.6) ) / 2 ; the unit of RHV is kΩ 1.6 (2) www.fairchildsemi.com 11 Thermal Protection An NTC thermistor, RNTC, in series with resistor RA, can be connected from the RT pin to ground. A constant current IRT is output from the RT pin. The voltage on the RT pin can be expressed as VRT=IRT • (RNTC + RPTC), where IRT is 100µA. At high ambient temperature, RNTC is smaller, such that VRT decreases. When VRT is less than 1.035V (VRTTH1), the PWM turns off after 16ms (tD-OTP1). If VRT is less than 0.7V (VRTTH2), PWM turns off after 185µs (tD-OTP2). 0.47 0.46 0.45 Vlimit (V) 0.44 Limited Power Control 0.43 0.42 The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, VDD begins decreasing. 0.41 0.4 0.39 0.38 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 When VDD goes below the turn-off threshold (9V) the controller is totally shut down and, VDD is continuously discharged to VDD-OLP (6.5V) by IDD-OLP to lower the average input power. This is called two-level UVLO. VDD is cycled again. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions. DC Voltage on HV Pin (V) Figure 25. Linearly Current Limit Curve VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents damage due to abnormal conditions. If the VDD voltage is over the overvoltage protection voltage (VDD-OVP) and lasts for tDVDDOVP, the PWM pulses are disabled until the VDD voltage drops below the UVLO, then starts again. Overvoltage conditions are usually caused by open feedback loops. © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 Noise Immunity Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN6754, and increasing the power MOS gate resistance improve performance. FAN6754 — Highly Integrated Green-Mode PWM Controller The HV pin can perform current limit to shrink the tolerance of OCP (Over-Current Protection) under full range of AC voltage, to linearly current limit curve as shown in Figure 25. FAN6754 also shrinks the Vlimit 2 level by half to lower the I RSENSE loss to increase the heavy-load efficiency. www.fairchildsemi.com 12 FAN6754 — Highly Integrated Green-Mode PWM Controller Physical Dimensions 5.00 4.80 A 0.65 3.81 8 5 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 R0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 26. 8-Pin Small Outline Package (SOP) Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 www.fairchildsemi.com 13 FAN6754 — Highly Integrated Green-Mode PWM Controller © 2010 Fairchild Semiconductor Corporation FAN6754 • Rev. 1.0.2 www.fairchildsemi.com 14