RENESAS R8CL35B

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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
RENESAS MCU
1.
REJ03B0243-0030
Rev.0.30
Jan 21, 2009
Overview
1.1
Features
The R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B
Group, R8C/L38B Group, and R8C/L3AB Group of single-chip MCUs incorporate the R8C CPU core, which
implements a powerful instruction set for a high level of efficiency and supports a 1 Mbyte address space, allowing
execution of instructions at high speed. In addition, the CPU core integrates a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, helps reduce the
number of system components.
The R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, and R8C/L3AA Group have data flash (1 KB × 4
blocks) with the background operation (BGO) function.
1.1.1
Applications
Household appliances, office equipment, audio equipment, consumer products, etc.
REJ03B0243-0030 Rev.0.30
Page 1 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
1.1.2
Differences between Groups
Tables 1.1 and 1.2 list the differences between the groups, Table 1.3 lists the I/O ports provided for each group,
and Table 1.4 lists the LCD Display Function Pins Provided for Each Group. Figures 1.13 to 1.17 show the pin
assignment for each group, and Tables 1.8 to 1.15 list product information.
The explanations in the chapters which follow apply to the R8C/L3AA Group only. Note the differences shown
below.
Table 1.1
Item
Data
flash
Differences between Groups (1)
Function
1 KB × 4 blocks with BGO
(background operation) function
Table 1.2
Differences between Groups (2)
R8C/L35A Group
R8C/L35B Group
R8C/L36A Group
R8C/L36B Group
R8C/L38A Group
R8C/L38B Group
Programmable I/O ports
41 pins
52 pins
68 pins
88 pins
High current drive ports
5 pins
8 pins
8 pins
16 pins
Item
I/O Ports
Interrupts
Timers
R8C/L35A Group, R8C/L36A Group R8C/L35B Group, R8C/L36B Group
R8C/L38A Group, R8C/L3AA Group R8C/L38B Group, R8C/L3AB Group
Provided
Not provided
Function
R8C/L3AA Group
R8C/L3AB Group
INT interrupt pins
5 pins
8 pins
8 pins
8 pins
Key input interrupt pins
4 pins
4 pins
8 pins
8 pins
1 pin
(I/O pin only)
2 pins
2 pins
2 pins
Timer RA pins
(I/O: 1, output: 1)
Timer RB pin (output: 1)
None
1 pin
1 pin
1 pin
Timer RD pin (I/O: 8)
None
None
8 pins
8 pins
Timer RE pin (output: 1)
None
1 pin
1 pin
1 pin
Timer RG pin
(I/O: 2, output: 2)
None
None
None
4 pins
A/D Converter
Analog input pin
10 pins
10 pins
16 pins
20 pins
LCD Drive
Control Circuit
LCD power supply
3 pins
(VL1, VL2, VL4)
4 pins
(VL1 to VL4)
4 pins
(VL1 to VL4)
4 pins
(VL1 to VL4)
Other Pin
Function
Common output pins
Max. 4 pins
Max. 8 pins
Max. 8 pins
Max. 8 pins
Segment output pins
Max. 24 pins
Max. 32 pins
Max. 48 pins
Max. 56 pins
Not supported
Not supported
Supported
Supported
52-pin LQFP
64-pin LQFP
80-pin LQFP
WKUP1
Packages
Note:
1. I/O ports are shared with I/O functions, such as interrupts or timers.
Refer to Tables 1.16 to 1.18, Pin Name Information by Pin Number, for details.
REJ03B0243-0030 Rev.0.30
Page 2 of 76
Jan 21, 2009
100-pin LQFP/
100-pin QFP
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.3
Programmable I/O Ports Provided for Each Group
R8C/L3AA Group
R8C/L3AB Group
Total: 88 I/O pins
R8C/L38A Group
R8C/L38B Group
Total: 68 I/O pins
R8C/L36A Group
R8C/L36B Group
Total: 52 I/O pins
R8C/L35A Group
R8C/L35B Group
Total: 41 I/O pins
Programmable
I/O Port
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
P0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
3
3
3
3
3
3
3
3
3
3
3
P2
3
3
3
3
−
−
−
−
3
3
3
3
−
−
−
−
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P3
−
−
−
−
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
3
3
3
P6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P7
3
3
3
3
−
−
−
−
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P10
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
3
3
3
3
3
3
3
P11
−
−
−
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P12
−
−
−
−
3
3
3
3
−
−
−
−
3
3
3
3
−
−
−
−
3
3
3
3
−
−
−
−
3
3
3
3
P13
−
−
−
−
3
3
3
3
−
−
−
−
3
3
3
3
−
−
−
−
3
3
3
3
3
3
3
3
3
3
3
3
Notes:
1. The symbol “3” indicates a programmable I/O port.
2. The symbol “-” indicates the settings should be made as follows:
- Set 1 to the corresponding PDi (i = 0 to 7 and 10 to 13) register. When read, the content is 1.
- Set 0 to the corresponding Pi (i = 0 to 7 and 10 to 13) register. When read, the content is 0.
- Set 0 to the corresponding P10DRR or P11DRR register. When read, the content is 0.
Table 1.4
LCD Display Function Pins Provided for Each Group
L3AA, L3AB Group
Common output: Max. 8
Segment output: Max. 56
L38A, L38B Group
Common output: Max. 8
Segment output: Max. 48
L36A, L36B Group
Common output: Max. 8
Segment output: Max. 32
L35A, L35B Group
Common output: Max. 4
Segment output: Max. 24
Shared
I/O Port
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P0
P1
−
−
−
−
SEG SEG SEG SEG
23
22
21
20
P2
P3
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
SEG SEG SEG SEG
23
22
21
20
−
−
−
−
−
−
−
−
−
−
−
−
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
11
10
9
8
15
14
13
12
11
10
9
8
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
23
22
21
20
19
18
17
16
23
22
21
20
19
18
17
16
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
27
26
25
24
31
30
29
28
27
26
25
24
31
30
29
28
27
26
25
24
31
30
29
28
27
26
25
24
−
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
39
38
37
36
35
34
33
32
39
38
37
36
35
34
33
32
39
38
37
36
35
34
33
32
39
38
37
36
35
34
33
32
P4
P5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
P6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
COM COM COM COM
0
1
2
3
P7
P12
−
−
−
−
CL2 CL1
−
−
−
−
−
−
−
−
−
−
−
−
SEG SEG SEG SEG
43
42
41
40
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
51
50
49
48
47
46
45
44
51
50
49
48
47
46
45
44
COM COM COM COM SEG SEG SEG SEG COM COM COM COM SEG SEG SEG SEG COM COM COM COM SEG SEG SEG SEG
0
1
2
3
55
54
53
52
0
1
2
3
55
54
53
52
0
1
2
3
55
54
53
52
−
−
−
−
CL2 CL1
−
VL1
VL1
−
VL2
−
−
−
VL4
−
−
−
−
−
−
CL2 CL1
−
−
−
−
−
−
CL2 CL1
VL1
VL1
VL2
VL2
VL2
VL3
VL3
VL3
VL4
VL4
VL4
−
−
Notes:
1. The symbol “−”indicates there is no LCD display function. Select the I/O port function with registers LSE1 to LSE7 for these
pins.
2. SEG52 to SEG55 can be used as COM7 to COM4.
3. The R8C/L35A Group and R8C/L35B Group do not have the VL3 pin.
The available bias settings are 1/3 bias, 1/2 bias, or static.
REJ03B0243-0030 Rev.0.30
Page 3 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
1.1.3
1. Overview
Specifications
Tables 1.5 to 1.7 list the specifications.
Table 1.5
Specifications (1)
Item
CPU
Function
Central processing unit
Memory
ROM/RAM
Data flash
Voltage detection circuit
Power
Supply
Voltage
Detection
I/O Ports Programmable R8C/L35A Group
I/O ports
R8C/L35B Group
R8C/L36A Group
R8C/L36B Group
R8C/L38A Group
R8C/L38B Group
R8C/L3AA Group
R8C/L3AB Group
Clock
Clock generation circuits
Specification
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Refer to Tables 1.8 to 1.15 Product Lists.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
• CMOS I/O ports: 41, selectable pull-up resistor
• High current drive ports: 5
• CMOS I/O ports: 52, selectable pull-up resistor
• High current drive ports: 8
• CMOS I/O ports: 68, selectable pull-up resistor
• High current drive ports: 8
• CMOS I/O ports: 88, selectable pull-up resistor
• High current drive ports: 16
4 circuits: XIN clock oscillation circuit
XCIN clock oscillation circuit (32 kHz)
High-speed on-chip oscillator (with frequency adjustment function)
Low-speed on-chip oscillator
• Oscillation stop detection:
XIN clock oscillation stop detection function
• Frequency divider circuit:
Division ratio selectable from 1, 2, 4, 8, and 16
• Low-power-consumption modes:
Standard operating mode (high-speed clock, low-speed clock, highspeed on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode, power-off mode
Real-time clock (timer RE)
Interrupts
R8C/L35A Group • Number of interrupt vectors: 69
R8C/L35B Group • External Interrupt: 9 (INT × 5, key input × 4)
• Priority levels: 7 levels
R8C/L36A Group • Number of interrupt vectors: 69
R8C/L36B Group • External Interrupt: 12 (INT × 8, key input × 4)
• Priority levels: 7 levels
R8C/L38A Group • Number of interrupt vectors: 69
R8C/L38B Group • External Interrupt: 16 (INT × 8, key input × 8)
• Priority levels: 7 levels
R8C/L3AA Group • Number of interrupt vectors: 69
R8C/L3AB Group • External Interrupt: 16 (INT × 8, key input × 8)
• Priority levels: 7 levels
Watchdog Timer
• 14 bits × 1 (with prescaler)
• Selectable reset start function
• Selectable low-speed on-chip oscillator for watchdog timer
DTC (Data Transfer Controller)
• 1 channel
• Activation sources: 38
• Transfer modes: 2 (normal mode, repeat mode)
REJ03B0243-0030 Rev.0.30
Page 4 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.6
Item
Timer
Specifications (2)
Function
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
Timer RG
Serial
Interface
1. Overview
UART0, UART1
UART2
Synchronous Serial
Communication Unit (SSU)
I2C bus
LIN Module
A/D
R8C/L35A Group
Converter
R8C/L35B Group
R8C/L36A Group
R8C/L36B Group
R8C/L38A Group
R8C/L38B Group
R8C/L3AA Group
R8C/L3AB Group
D/A Converter
Comparator A
Comparator B
R8C/L35A Group
LCD Drive
R8C/L35B Group
Control
R8C/L36A Group
Circuit
R8C/L36B Group
R8C/L38A Group
R8C/L38B Group
R8C/L3AA Group
R8C/L3AB Group
Specification
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode,
pulse period measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output:
6 pins, sawtooth wave modulation), complementary PWM mode (three-phase
waveform output: 6 pins, triangular wave modulation), PWM3 mode (PWM
output with fixed period: 2 pins)
8 bits × 1
Real-time clock mode (counting of seconds, minutes, hours, days of week),
output compare mode
16 bits × 1
Phase-counting mode,
timer mode (output compare function, input capture function),
PWM mode (output: 1 pin)
Clock synchronous serial I/O/UART × 2 channels
Clock synchronous serial I/O/UART, I2C mode (I2C-bus),
multiprocessor communication function
1 (shared with I2C-bus)
1 (shared with SSU)
Hardware LIN: 1 channel (timer RA, UART0 used)
10-bit resolution × 10 channels, including sample and hold function, with sweep
mode
10-bit resolution × 10 channels, including sample and hold function, with sweep
mode
10-bit resolution × 16 channels, including sample and hold function, with sweep
mode
10-bit resolution × 20 channels, including sample and hold function, with sweep
mode
8-bit resolution × 2 circuits
• 2 circuits (shared with voltage monitor 1 and voltage monitor 2)
• External reference voltage input available
2 circuits
Common output: Max. 4 pins
Bias: 1/2, 1/3
Segment output: Max. 24 pins
Duty: static, 1/2, 1/3, 1/4
Common output: Max. 8 pins
Segment output: Max. 32 pins (1)
Common output: Max. 8 pins
Bias: 1/2, 1/3, 1/4
Duty: static, 1/2, 1/3, 1/4, 1/8
Segment output: Max. 48 pins (1)
Common output: Max. 8 pins
Segment output: Max. 56 pins (1)
Voltage multiplier and dedicated regulator integrated
Note:
1. This applies when four pins are selected for common output.
REJ03B0243-0030 Rev.0.30
Page 5 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.7
Item
Flash
Memory
Specifications (2)
Function
R8C/L35A Group
R8C/L36A Group
R8C/L38A Group
R8C/L3AA Group
R8C/L35B Group
R8C/L36B Group
R8C/L38B Group
R8C/L3AB Group
Operating Frequency/
Supply Voltage
Current Consumption
Operating Ambient Temperature
Specification
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 1,000 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)
Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 3.5 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
Typ. 2 µA (VCC = 3.0 V, stop mode)
Typ. 1 µA (VCC = 3.0 V, power-off mode, timer RE enabled)
Typ. 0.02 µA (VCC = 3.0 V, power-off mode, timer RE disabled)
-20 to 85°C (N version)
-40 to 85°C (D version) (1)
Note:
1. Specify the D version if D version functions are to be used.
REJ03B0243-0030 Rev.0.30
Page 6 of 76
Jan 21, 2009
1. Overview
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
1.2
Product Lists
Tables 1.8 to 1.15 list product information for each group. Figure 1.1 to 1.8 show the Correspondence of Part No.,
with Memory Size and Package of R8C/Lx Group.
Table 1.8
Product List for R8C/L35A Group
Part No.
R5F2L357ANFP
R5F2L358ANFP
R5F2L35AANFP
R5F2L35CANFP
R5F2L357ADFP
R5F2L358ADFP
R5F2L35AADFP
R5F2L35CADFP
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
Internal ROM Capacity
Program ROM
Data Flash
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
Current of Jan 2009
Internal RAM
Capacity
6 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
Package Type
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
Remarks
N Version
D Version
(D): Under development
Part No. R 5 F 2L 35 C A N FP
Package type:
FP, FA: LQFP
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L35A Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Correspondence of Part No., with Memory Size and Package of R8C/L35A Group
REJ03B0243-0030 Rev.0.30
Page 7 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.9
Product List for R8C/L35B Group
Part No.
R5F2L357BNFP
R5F2L358BNFP
R5F2L35ABNFP
R5F2L35CBNFP
R5F2L357BDFP
R5F2L358BDFP
R5F2L35ABDFP
R5F2L35CBDFP
Internal ROM Capacity
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Current of Jan 2009
Internal RAM
Capacity
6 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
Package Type
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
Remarks
N Version
D Version
(D): Under development
Part No. R 5 F 2L 35 C B N FP
Package type:
FP, FA: LQFP
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L35B Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2
Correspondence of Part No., with Memory Size and Package of R8C/L35B Group
REJ03B0243-0030 Rev.0.30
Page 8 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.10
Product List for R8C/L36A Group
Part No.
R5F2L367ANFP
R5F2L367ANFA
R5F2L368ANFP
R5F2L368ANFA
R5F2L36AANFP
R5F2L36AANFA
R5F2L36CANFP
R5F2L36CANFA
R5F2L367ADFP
R5F2L367ADFA
R5F2L368ADFP
R5F2L368ADFA
R5F2L36AADFP
R5F2L36AADFA
R5F2L36CADFP
R5F2L36CADFA
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
Internal ROM Capacity
Program ROM
Data Flash
48 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
Current of Jan 2009
Internal RAM
Capacity
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
Package Type
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
Remarks
N Version
D Version
(D): Under development
Part No. R 5 F 2L 36 C A N FP
Package type:
FP, FA: LQFP
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L36A Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3
Correspondence of Part No., with Memory Size and Package of R8C/L36A Group
REJ03B0243-0030 Rev.0.30
Page 9 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.11
Product List for R8C/L36B Group
Part No.
R5F2L367BNFP
R5F2L367BNFA
R5F2L368BNFP
R5F2L368BNFA
R5F2L36ABNFP
R5F2L36ABNFA
R5F2L36CBNFP
R5F2L36CBNFA
R5F2L367BDFP
R5F2L367BDFA
R5F2L368BDFP
R5F2L368BDFA
R5F2L36ABDFP
R5F2L36ABDFA
R5F2L36CBDFP
R5F2L36CBDFA
Internal ROM Capacity
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
Current of Jan 2009
Internal RAM
Capacity
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
Package Type
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
Remarks
N Version
D Version
(D): Under development
Part No. R 5 F 2L 36 C B N FP
Package type:
FP, FA: LQFP
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L36B Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.4
Correspondence of Part No., with Memory Size and Package of R8C/L36B Group
REJ03B0243-0030 Rev.0.30
Page 10 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.12
Product List for R8C/L38A Group
Part No.
R5F2L387ANFP
R5F2L387ANFA
R5F2L388ANFP
R5F2L388ANFA
R5F2L38AANFP
R5F2L38AANFA
R5F2L38CANFP
R5F2L38CANFA
R5F2L387ADFP
R5F2L387ADFA
R5F2L388ADFP
R5F2L388ADFA
R5F2L38AADFP
R5F2L38AADFA
R5F2L38CADFP
R5F2L38CADFA
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
Internal ROM Capacity
Program ROM
Data Flash
48 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
Current of Jan 2009
Internal RAM
Capacity
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
Package Type
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
Remarks
N Version
D Version
(D): Under development
Part No. R 5 F 2L 38 C A N FP
Package type:
FP, FA: LQFP
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L38A Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.5
Correspondence of Part No., with Memory Size and Package of R8C/L38A Group
REJ03B0243-0030 Rev.0.30
Page 11 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.13
Product List for R8C/L38B Group
Part No.
R5F2L387BNFP
R5F2L387BNFA
R5F2L388BNFP
R5F2L388BNFA
R5F2L38ABNFP
R5F2L38ABNFA
R5F2L38CBNFP
R5F2L38CBNFA
R5F2L387BDFP
R5F2L387BDFA
R5F2L388BDFP
R5F2L388BDFA
R5F2L38ABDFP
R5F2L38ABDFA
R5F2L38CBDFP
R5F2L38CBDFA
Internal ROM Capacity
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
Current of Jan 2009
Internal RAM
Capacity
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
Package Type
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
Remarks
N Version
D Version
(D): Under development
Part No. R 5 F 2L 38 C B N FP
Package type:
FP, FA: LQFP
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L38B Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.6
Correspondence of Part No., with Memory Size and Package of R8C/L38B Group
REJ03B0243-0030 Rev.0.30
Page 12 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.14
Product List for R8C/L3AA Group
Part No.
R5F2L3A7ANFP
R5F2L3A7ANFA
R5F2L3A8ANFP
R5F2L3A8ANFA
R5F2L3AAANFP
R5F2L3AAANFA
R5F2L3ACANFP
R5F2L3ACANFA
R5F2L3A7ADFP
R5F2L3A7ADFA
R5F2L3A8ADFP
R5F2L3A8ADFA
R5F2L3AAADFP
R5F2L3AAADFA
R5F2L3ACADFP
R5F2L3ACADFA
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
Internal ROM Capacity
Program ROM
Data Flash
48 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
Current of Jan 2009
Internal RAM
Capacity
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
Package Type
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
Remarks
N Version
D Version
(D): Under development
Part No. R 5 F 2L 3A C A N FP
Package type:
FP: LQFP (0.50 mm pin pitch)
FA: LQFP (0.65 mm pin pitch)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L3AA Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.7
Correspondence of Part No., with Memory Size and Package of R8C/L3AA Group
REJ03B0243-0030 Rev.0.30
Page 13 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.15
Product List for R8C/L3AB Group
Part No.
R5F2L3A7BNFP
R5F2L3A7BNFA
R5F2L3A8BNFP
R5F2L3A8BNFA
R5F2L3AABNFP
R5F2L3AABNFA
R5F2L3ACBNFP
R5F2L3ACBNFA
R5F2L3A7BDFP
R5F2L3A7BDFA
R5F2L3A8BDFP
R5F2L3A8BDFA
R5F2L3AABDFP
R5F2L3AABDFA
R5F2L3ACBDFP
R5F2L3ACBDFA
Internal ROM Capacity
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
Current of Jan 2009
Internal RAM
Capacity
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
6 Kbytes
6 Kbytes
8 Kbytes
8 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
10 Kbytes
Package Type
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
Remarks
N Version
D Version
(D): Under development
Part No. R 5 F 2L 3A C B N FP
Package type:
FP: LQFP (0.50 mm pin pitch)
FA: LQFP (0.65 mm pin pitch)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/L3AB Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.8
Correspondence of Part No., with Memory Size and Package of R8C/L3AB Group
REJ03B0243-0030 Rev.0.30
Page 14 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
1.3
Block Diagrams
Figure 1.9 shows a Block Diagram of R8C/L35A and R8C/L35B Groups. Figure 1.10 shows a Block Diagram of
R8C/L36A and R8C/L36B Groups. Figure 1.11 shows a Block Diagram of R8C/L38A and R8C/L38B Groups.
Figure 1.12 shows a Block Diagram of R8C/L3AA and R8C/L3AB Groups.
I/O ports
8
4
4
8
Port P0
Port P2
Port P3
Port P4
Peripheral functions
Comparator A
A/D converter
(10 bits × 10 channels)
Comparator B
LCD drive control circuit
D/A converter
(8 bits × 2 channels)
Common output: Max. 4 pins
Segment output: Max. 24 pins
A0
A1
FB
R0L
R1L
4
4
Memory
R8C CPU core
R0H
R1H
R2
R3
5
DTC
LIN module
Watchdog timer
(14 bits)
4
Port P13
I C bus or SSU
(8 bits × 1)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Port P12
2
System clock generation
circuit
Port P11
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RG (16 bits × 1)
UART or
clock synchronous serial I/O
(8 bits × 3)
Port P7
Timers
ROM (1)
SB
USP
ISP
RAM (2)
INTB
PC
FLG
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.9
Block Diagram of R8C/L35A and R8C/L35B Groups
REJ03B0243-0030 Rev.0.30
Page 15 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
I/O ports
8
4
8
8
Port P0
Port P2
Port P3
Port P4
Peripheral functions
A/D converter
(10 bits × 10 channels)
Comparator B
LCD drive control circuit
D/A converter
(8 bits × 2 channels)
Common output: Max. 8 pins
Segment output: Max. 32 pins
A0
A1
FB
R0L
R1L
4
Memory
R8C CPU core
R0H
R1H
R2
R3
4
Port P13
Comparator A
8
DTC
LIN module
Watchdog timer
(14 bits)
8
Port P12
I2C bus or SSU
(8 bits × 1)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Port P11
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RG (16 bits × 1)
System clock generation
circuit
Port P7
Timers
UART or
clock synchronous serial I/O
(8 bits × 3)
ROM (1)
SB
USP
ISP
RAM (2)
INTB
PC
FLG
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.10
Block Diagram of R8C/L36A and R8C/L36B Groups
REJ03B0243-0030 Rev.0.30
Page 16 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
I/O ports
8
4
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P6
Peripheral functions
A/D converter
(10 bits × 16 channels)
Comparator B
LCD drive control circuit
D/A converter
(8 bits × 2 channels)
Common output: Max. 8 pins
Segment output: Max. 48 pins
A0
A1
FB
R0L
R1L
4
Memory
R8C CPU core
R0H
R1H
R2
R3
4
Port P13
Comparator A
8
DTC
LIN module
Watchdog timer
(14 bits)
8
Port P12
I2C bus or SSU
(8 bits × 1)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Port P11
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RG (16 bits × 1)
System clock generation
circuit
Port P7
Timers
UART or
clock synchronous serial I/O
(8 bits × 3)
ROM (1)
SB
USP
ISP
RAM (2)
INTB
PC
FLG
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.11
Block Diagram of R8C/L38A and R8C/L38B Groups
REJ03B0243-0030 Rev.0.30
Page 17 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
I/O ports
8
8
8
8
8
4
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Peripheral functions
Comparator B
LCD drive control circuit
D/A converter
(8 bits × 2 channels)
Common output: Max. 8 pins
Segment output: Max. 56 pins
A0
A1
FB
R0L
R1L
8
Memory
R8C CPU core
R0H
R1H
R2
R3
4
Port P13
A/D converter
(10 bits × 20 channels)
8
Port P12
Comparator A
8
DTC
LIN module
Watchdog timer
(14 bits)
8
Port P11
I2C bus or SSU
(8 bits × 1)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Port P10
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RG (16 bits × 1)
System clock generation
circuit
Port P7
Timers
UART or
clock synchronous serial I/O
(8 bits × 3)
ROM (1)
SB
USP
ISP
RAM (2)
INTB
PC
FLG
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.12
Block Diagram of R8C/L3AA and R8C/L3AB Groups
REJ03B0243-0030 Rev.0.30
Page 18 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
1.4
Pin Assignments
P0_6/SEG6
P0_7/SEG7
P2_4/SEG20/KI4
P2_5/SEG21/KI5
P2_6/SEG22/KI6
P2_7/SEG23/KI7
P3_0/SEG24/INT0
P3_1/SEG25/INT1
P3_2/SEG26/INT2
P3_3/SEG27/INT3
P4_0/SEG32/TXD1
P4_1/SEG33/RXD1
P4_2/SEG34/CLK1
Figures 1.13 to 1.17 show pin assignments (top view). Tables 1.16 to 1.18 list the pin name information by pin
number.
39 38 37 36 35 34 33 32 31 30 29 28 27
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
VL1
VL2
CL2/P12_3
CL1/P12_2
VL4
P13_3/AN3/CLK0/LVCMP2
P13_2/AN2/RXD0/LVCMP1
40
26
41
25
42
24
43
23
44
R8C/L35A Group
R8C/L35B Group
45
46
47
48
49
22
21
20
19
PLQP0052JA-A (52P6A-A)
(top view)
18
17
50
16
51
15
52
14
2
3
4
5
6
7
8
9 10 11 12 13
P13_1/AN1/DA1/TXD0/LVREF
P13_0/AN0/DA0
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
P12_1/XOUT
VSS/AVSS
P12_0/XIN
VCC/AVCC
P11_4/TRAIO/(INT4/RXD0)
1
P4_3/SEG35/TRCCLK/TRCTRG
P4_4/SEG36/TRCIOA/TRCTRG
P4_5/SEG37/TRCIOB
P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD/TRCIOB
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1
P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2
P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3
P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.13
Pin Assignment (Top View) of PLQP0052JA-A Package
REJ03B0243-0030 Rev.0.30
Page 19 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
P0_6/SEG6
P0_7/SEG7
P2_4/SEG20/KI4
P2_5/SEG21/KI5
P2_6/SEG22/KI6
P2_7/SEG23/KI7
P3_0/SEG24/INT0
P3_1/SEG25/INT1
P3_2/SEG26/INT2
P3_3/SEG27/INT3
P3_4/SEG28/INT4
P3_5/SEG29/INT5
P3_6/SEG30/INT6
P3_7/SEG31/INT7/ADTRG/TRCTRG
P4_0/SEG32/TXD1
P4_1/SEG33/RXD1
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
VL1
VL2
VL3
CL2/P12_3
CL1/P12_2
VL4
P13_3/AN3/CLK0/LVCMP2
P13_2/AN2/RXD0/LVCMP1
P13_1/AN1/DA1/TXD0/LVREF
P13_0/AN0/DA0
49
32
50
31
51
30
52
29
53
28
54
R8C/L36A Group
R8C/L36B Group
27
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
(top view)
23
55
56
57
58
59
60
61
26
25
24
22
21
20
62
19
63
18
64
17
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
P12_1/XOUT
VSS/AVSS
P12_0/XIN
VCC/AVCC
P11_7/TREO/(INT7/ADTRG)
P11_6/TRBO/(INT6)
P11_5/TRAO/(INT5)
P11_4/TRAIO/(INT4/RXD0)
P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3
P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3
1
P4_2/SEG34/CLK1
P4_3/SEG35/TRCCLK/TRCTRG
P4_4/SEG36/TRCIOA/TRCTRG
P4_5/SEG37/TRCIOB
P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD/TRCIOB
P7_0/SEG52/COM7
P7_1/SEG53/COM6
P7_2/SEG54/COM5
P7_3/SEG55/COM4
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1
P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.14
Pin Assignment (Top View) of PLQP0064KB-A and PLQP0064GA-A Packages
REJ03B0243-0030 Rev.0.30
Page 20 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
P2_1/SEG17/KI1
P2_2/SEG18/KI2
P2_3/SEG19/KI3
P2_4/SEG20/KI4
P2_5/SEG21/KI5
P2_6/SEG22/KI6
P2_7/SEG23/KI7
P3_0/SEG24/INT0
P3_1/SEG25/INT1
P3_2/SEG26/INT2
P3_3/SEG27/INT3
P3_4/SEG28/INT4
P3_5/SEG29/INT5
P3_6/SEG30/INT6
P3_7/SEG31/INT7/ADTRG/TRCTRG
P4_0/SEG32/TXD1
P4_1/SEG33/RXD1
P4_2/SEG34/CLK1
P4_3/SEG35/TRCCLK/TRCTRG
P4_4/SEG36/TRCIOA/TRCTRG
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P2_0/SEG16/KI0
P1_3/SEG11/AN15
P1_2/SEG10/AN14
P1_1/SEG9/AN13
P1_0/SEG8/AN12
P0_7/SEG7/AN11
P0_6/SEG6/AN10
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
VL1
VL2
VL3
CL2/P12_3
CL1/P12_2
VL4
P13_3/AN3/CLK0/LVCMP2
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
R8C/L38A Group
R8C/L38B Group
69
70
71
72
PLQP0080KB-A (80P6Q-A)
PLQP0080JA-A (FP-80W/FP-80WV)
(top view)
73
74
75
33
32
31
30
29
28
27
26
76
25
77
24
78
23
79
22
80
21
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
P13_2/AN2/RXD0/LVCMP1
P13_1/AN1/DA1/TXD0/LVREF
P13_0/AN0/DA0/WKUP1
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
P12_1/XOUT
VSS/AVSS
P12_0/XIN
VCC/AVCC
P11_7/TREO/(INT7/ADTRG)
P11_6/TRBO/(INT6)
P11_5/TRAO/(INT5)
P11_4/TRAIO/(INT4/RXD0)
P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3
P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3
P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2
1
P4_5/SEG37/TRCIOB
P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD/TRCIOB
P6_0/SEG44/TRDIOA0/TRDCLK
P6_1/SEG45/TRDIOB0
P6_2/SEG46/TRDIOC0
P6_3/SEG47/TRDIOD0
P6_4/SEG48/TRDIOA1
P6_5/SEG49/TRDIOB1
P6_6/SEG50/TRDIOC1
P6_7/SEG51/TRDIOD1
P7_0/SEG52/COM7
P7_1/SEG53/COM6
P7_2/SEG54/COM5
P7_3/SEG55/COM4
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.15
Pin Assignment (Top View) of PLQP0080KB-A and PLQP0080JA-A Packages
REJ03B0243-0030 Rev.0.30
Page 21 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
P1_7/SEG15
P2_0/SEG16/KI0
P2_1/SEG17/KI1
P2_2/SEG18/KI2
P2_3/SEG19/KI3
P2_4/SEG20/KI4
P2_5/SEG21/KI5
P2_6/SEG22/KI6
P2_7/SEG23/KI7
P3_0/SEG24/INT0
P3_1/SEG25/INT1
P3_2/SEG26/INT2
P3_3/SEG27/INT3
P3_4/SEG28/INT4
P3_5/SEG29/INT5
P3_6/SEG30/INT6
P3_7/SEG31/INT7/ADTRG/TRCTRG
P4_0/SEG32/TXD1
P4_1/SEG33/RXD1
P4_2/SEG34/CLK1
P4_3/SEG35/TRCCLK/TRCTRG
P4_4/SEG36/TRCIOA/TRCTRG
P4_5/SEG37/TRCIOB
P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD/TRCIOB
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P1_6/SEG14
P1_5/SEG13
P1_4/SEG12
P1_3/SEG11/AN15
P1_2/SEG10/AN14
P1_1/SEG9/AN13
P1_0/SEG8/AN12
P0_7/SEG7/AN11
P0_6/SEG6/AN10
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
VL1
VL2
VL3
CL2/P12_3
CL1/P12_2
VL4
P13_7/AN19/TRGCLKB
P13_6/AN18/TRGIOB
P13_5/AN17/TRGCLKA
P13_4/AN16/TRGIOA
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
R8C/L3AA Group
R8C/L3AB Group
85
86
87
88
89
90
41
40
39
38
37
36
PLQP0100KB-A (100P6Q-A)
(top view)
91
92
93
35
34
33
94
32
95
31
96
30
97
29
98
28
99
27
26
100
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P13_3/AN3/CLK0/LVCMP2
P13_2/AN2/RXD0/LVCMP1
P13_1/AN1/DA1/TXD0/LVREF
P13_0/AN0/DA0/WKUP1
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
P12_1/XOUT
VSS/AVSS
P12_0/XIN
VCC/AVCC
P11_7/TREO/(INT7/ADTRG)
P11_6/TRBO/(INT6)
P11_5/TRAO/(INT5)
P11_4/TRAIO/(INT4/RXD0)
P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3
P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3
P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2
P11_0/SCL/SSCK/(CLK2/INT0) /IVREF1/LVCOUT1
P10_7/(TRDIOD1/KI7)
P10_6/(TRDIOC1/KI6)
P10_5/(TRDIOB1/KI5)
1
P5_0/SEG40
P5_1/SEG41
P5_2/SEG42
P5_3/SEG43
P6_0/SEG44/TRDIOA0/TRDCLK
P6_1/SEG45/TRDIOB0
P6_2/SEG46/TRDIOC0
P6_3/SEG47/TRDIOD0
P6_4/SEG48/TRDIOA1
P6_5/SEG49/TRDIOB1
P6_6/SEG50/TRDIOC1
P6_7/SEG51/TRDIOD1
P7_0/SEG52/COM7
P7_1/SEG53/COM6
P7_2/SEG54/COM5
P7_3/SEG55/COM4
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
P10_0/(TRDIOA0/TRDCLK/KI0)
P10_1/(TRDIOB0/KI1)
P10_2/(TRDIOC0/KI2)
P10_3/(TRDIOD0/KI3)
P10_4/(TRDIOA1/KI4)
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.16
Pin Assignment (Top View) of PLQP0100KB-A Package
REJ03B0243-0030 Rev.0.30
Page 22 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
P1_4/SEG12
P1_5/SEG13
P1_6/SEG14
P1_7/SEG15
P2_0/SEG16/KI0
P2_1/SEG17/KI1
P2_2/SEG18/KI2
P2_3/SEG19/KI3
P2_4/SEG20/KI4
P2_5/SEG21/KI5
P2_6/SEG22/KI6
P2_7/SEG23/KI7
P3_0/SEG24/INT0
P3_1/SEG25/INT1
P3_2/SEG26/INT2
P3_3/SEG27/INT3
P3_4/SEG28/INT4
P3_5/SEG29/INT5
P3_6/SEG30/INT6
P3_7/SEG31/INT7/ADTRG/TRCTRG
P4_0/SEG32/TXD1
P4_1/SEG33/RXD1
P4_2/SEG34/CLK1
P4_3/SEG35/TRCCLK/TRCTRG
P4_4/SEG36/TRCIOA/TRCTRG
P4_5/SEG37/TRCIOB
P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD/TRCIOB
P5_0/SEG40
P5_1/SEG41
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
80 79
P1_3/SEG11/AN15
P1_2/SEG10/AN14
P1_1/SEG9/AN13
P1_0/SEG8/AN12
P0_7/SEG7/AN11
P0_6/SEG6/AN10
P0_5/SEG5/AN9
P0_4/SEG4/AN8
P0_3/SEG3/AN7
P0_2/SEG2/AN6
P0_1/SEG1/AN5
P0_0/SEG0/AN4
VL1
VL2
VL3
CL2/P12_3
CL1/P12_2
VL4
P13_7/AN19/TRGCLKB
P13_6/AN18/TRGIOB
78 77
76
75 74
73
72
71 70
69
68
67 66
65 64
63
62
61
60 59
58
57 56
55
54
53 52
51
81
50
82
49
83
48
84
47
85
46
86
45
R8C/L3AA Group
R8C/L3AB Group
87
88
89
90
91
44
43
42
41
40
39
92
PRQP0100JD-B (100P6F-A)
(top view)
93
94
95
96
38
37
36
35
97
34
98
33
99
32
100
31
2
3
4
5
6
7
8
9
10
11 12
13 14 15
16
17
18 19
20
21 22
23
24 25
26
27
28 29
30
P13_5/AN17/TRGCLKA
P13_4/AN16/TRGIOA
P13_3/AN3/CLK0/LVCMP2
P13_2/AN2/RXD0/LVCMP1
P13_1/AN1/DA1/TXD0/LVREF
P13_0/AN0/DA0/WKUP1
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
P12_1/XOUT
VSS/AVSS
P12_0/XIN
VCC/AVCC
P11_7/TREO/(INT7/ADTRG)
P11_6/TRBO/(INT6)
P11_5/TRAO/(INT5)
P11_4/TRAIO/(INT4/RXD0)
P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3
P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3
P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2
P11_0/SCL/SSCK/(CLK2/INT0) /IVREF1/LVCOUT1
P10_7/(TRDIOD1/KI7)
P10_6/(TRDIOC1/KI6)
P10_5/(TRDIOB1/KI5)
P10_4/(TRDIOA1/KI4)
P10_3/(TRDIOD0/KI3)
P10_2/(TRDIOC0/KI2)
1
P5_2/SEG42
P5_3/SEG43
P6_0/SEG44/TRDIOA0/TRDCLK
P6_1/SEG45/TRDIOB0
P6_2/SEG46/TRDIOC0
P6_3/SEG47/TRDIOD0
P6_4/SEG48/TRDIOA1
P6_5/SEG49/TRDIOB1
P6_6/SEG50/TRDIOC1
P6_7/SEG51/TRDIOD1
P7_0/SEG52/COM7
P7_1/SEG53/COM6
P7_2/SEG54/COM5
P7_3/SEG55/COM4
P7_4/COM3
P7_5/COM2
P7_6/COM1
P7_7/COM0
P10_0/(TRDIOA0/TRDCLK/KI0)
P10_1/(TRDIOB0/KI1)
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.17
Pin Assignment (Top View) of PRQP0100JD-B Package
REJ03B0243-0030 Rev.0.30
Page 23 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.16
Pin Name Information by Pin Number (1)
Pin Number
L3AA
L38A L36A L35A
L3AB
L38B L36B L35B
(Note 2)
1 [3]
2 [4]
80
1
61
62
51
52
3 [5]
2
63
1
4 [6]
3
64
2
5 [7]
4
1
3
6 [8]
7 [9]
8 [10]
5
6
7
2
3
4
4
5
6
9 [11]
8
5
7
10 [12]
9
6
8
11 [13]
10
7
9
Control
Pin
WKUP1
(3)
Port
Interrupt
I/O Pin Functions for Peripheral Modules
A/D Converter,
D/A Converter,
2
Serial
IC
SSU
Comparators A, B,
Timer
Interface
bus
Voltage Detection
Circuit
P13_3
P13_2
CLK0
RXD0
AN3/LVCMP2
AN2/LVCMP1
P13_1
TXD0
AN1/DA1/LVREF
P13_0
LCD
drive
control
circuit
AN0/DA0
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
XOUT
VSS/
AVSS
XIN
VCC/
AVCC
P12_1
12 [14]
11
8
10
13 [15]
12
9
11
14 [16]
13
10
12
15 [17]
14
11
P11_7
16 [18]
15
12
17 [19]
16
13
18 [20]
17
14
19 [21]
18
15
20 [22]
19
21 [23]
22 [24]
P12_0
(INT7)
TREO
P11_6
(INT6)
TRBO
P11_5
(INT5)
TRAO
13
P11_4
(INT4)
TRAIO
14
P11_3
(INT3)
16
15
P11_2
(INT2)
20
17
16
P11_1
(INT1)
(CTS2/RTS2)
(RXD2/SCL2/
TXD2/SDA2)
(RXD2/SCL2/
TXD2/SDA2)
21
18
17
P11_0
(INT0)
(CLK2)
23 [25]
P10_7
(KI7)
(TRDIOD1)
24 [26]
P10_6
(KI6)
(TRDIOC1)
25 [27]
P10_5
(KI5)
(TRDIOB1)
26 [28]
P10_4
(KI4)
(TRDIOA1)
27 [29]
P10_3
(KI3)
(TRDIOD0)
28 [30]
P10_2
(KI2)
(TRDIOC0)
29 [31]
P10_1
(KI1)
(TRDIOB0)
30 [32]
P10_0
(KI0)
(TRDIOA0/
TRDCLK)
(ADTRG)
(RXD0)
IVCMP3
SCS
SSO
SDA
SSI
SSCK
IVREF3
IVCMP1/LVCOUT2
SCL
IVREF1/LVCOUT1
31 [33]
32 [34]
22
23
19
20
18
19
P7_7
P7_6
COM0
COM1
33 [35]
34 [36]
24
25
21
22
20
21
P7_5
P7_4
35 [37]
26
23
P7_3
36 [38]
27
24
P7_2
37 [39]
28
25
P7_1
38 [40]
29
26
P7_0
39 [41]
30
COM2
COM3
SEG55/
COM4
SEG54/
COM5
SEG53/
COM6
SEG52/
COM7
SEG51
P6_7
TRDIOD1
Notes:
1. The pin in parentheses can be assigned by a program.
2. The number in brackets indicates the pin number for the 100P6F package.
3. The WKUP1 pin is not available in the R8C/L35A, R8C/L35B, R8C/L36A, and R8C/L36B Groups.
REJ03B0243-0030 Rev.0.30
Page 24 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.17
Pin Name Information by Pin Number (2)
Pin Number
I/O Pin Functions for Peripheral Modules
L3AA
L38A L36A L35A
L3AB
L38B L36B L35B
(Note 2)
Control
Pin
Port
40 [42]
41 [43]
42 [44]
43 [45]
44 [46]
45 [47]
31
32
33
34
35
36
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
46 [48]
37
P6_0
47 [49]
48 [50]
49 [51]
50 [52]
Interrupt
Timer
Serial
Interface
SSU
I2C
bus
A/D Converter,
D/A Converter,
Comparators A, B,
Voltage Detection
Circuit
TRDIOC1
TRDIOB1
TRDIOA1
TRDIOD0
TRDIOC0
TRDIOB0
TRDIOA0/
TRDCLK
LCD
drive
control
circuit
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
P5_3
P5_2
P5_1
P5_0
SEG43
SEG42
SEG41
SEG40
TRCIOD/
TRCIOB
TRCIOC/
TRCIOB
TRCIOB
TRCIOA/
TRCTRG
TRCCLK/
TRCTRG
51 [53]
38
27
22
P4_7
52 [54]
39
28
23
P4_6
53 [55]
40
29
24
P4_5
54 [56]
41
30
25
P4_4
55 [57]
42
31
26
P4_3
56 [58]
57 [59]
58 [60]
43
44
45
32
33
34
27
28
29
P4_2
P4_1
P4_0
59 [61]
46
35
P3_7
INT7
60 [62]
47
36
P3_6
INT6
SEG30
61 [63]
48
37
P3_5
INT5
SEG29
62 [64]
49
38
P3_4
INT4
SEG28
63 [65]
50
39
30
P3_3
INT3
SEG27
64 [66]
51
40
31
P3_2
INT2
SEG26
65 [67]
52
41
32
P3_1
INT1
SEG25
66 [68]
53
42
33
P3_0
INT0
SEG24
67 [69]
54
43
34
P2_7
KI7
SEG23
68 [70]
55
44
35
P2_6
KI6
SEG22
69 [71]
56
45
36
P2_5
KI5
SEG21
70 [72]
57
46
37
P2_4
KI4
SEG20
71 [73]
58
P2_3
KI3
SEG19
72 [74]
59
P2_2
KI2
SEG18
73 [75]
60
P2_1
KI1
SEG17
74 [76]
61
P2_0
KI0
SEG16
62
63
64
65
66
67
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
75 [77]
76 [78]
77 [79]
78 [80]
79 [81]
80 [82]
81 [83]
82 [84]
83 [85]
84 [86]
47
48
38
39
SEG39
SEG38
SEG37
SEG36
SEG35
CLK1
RXD1
TXD1
TRCTRG
SEG34
SEG33
SEG32
ADTRG
AN15
AN14
AN13
AN12
AN11 (3)
AN10 (3)
Notes:
1. The pin in parentheses can be assigned by a program.
2. The number in brackets indicates the pin number for the 100P6F package.
3. Pins AN10 and AN11 are not available in the R8C/L35A, R8C/L35B, R8C/L36A, and R8C/L36B Groups.
REJ03B0243-0030 Rev.0.30
Page 25 of 76
Jan 21, 2009
SEG31
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.18
Pin Name Information by Pin Number (3)
Pin Number
L3AA
L38A L36A L35A
L3AB
L38B L36B L35B
(Note 2)
85 [87]
86 [88]
87 [89]
68
69
70
49
50
51
40
41
42
88 [90]
89 [91]
90 [92]
91 [93]
92 [94]
93 [95]
94 [96]
95 [97]
96 [98]
97 [99]
98 [100]
99 [1]
100 [2]
71
72
73
74
75
76
77
78
79
52
53
54
55
56
57
58
59
60
43
44
45
46
47
Control
Pin
48
49
50
Port
Interrupt
Timer
I/O Pin Functions for Peripheral Modules
A/D Converter,
D/A Converter,
Serial
SSU I2C bus Comparators A, B,
Interface
Voltage Detection
Circuit
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
AN9
AN8
AN7
AN6
AN5
AN4
P12_3
P12_2
P13_7
P13_6
P13_5
P13_4
TRGCLKB
TRGIOB
TRGCLKA
TRGIOA
Notes:
1. The pin in parentheses can be assigned by a program.
2. The number in brackets indicates the pin number for the 100P6F package.
REJ03B0243-0030 Rev.0.30
Page 26 of 76
Jan 21, 2009
AN19
AN18
AN17
AN16
LCD
drive
control
circuit
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VL1
VL2
VL3
CL2
CL1
VL4
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
1.5
Pin Functions
Tables 1.19 and 1.20 list pin functions.
Table 1.19
Pin Functions (1)
Item
Pin Name
I/O Type
Description
Power supply input
VCC, VSS
−
Apply 1.8 V to 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Driving this pin low resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
Power-off mode exit WKUP0
input
I
This pin is provided for input to exit the mode used in power-off
mode. Connect to VSS when not using power-off mode.
WKUP1
I
This pin is provided for input to exit the mode used in power-off
mode.
XIN clock input
XIN
I
XIN clock output
XOUT
O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic oscillator or a crystal oscillator between pins
XIN and XOUT. (1) To use an external clock, input it to the XIN
pin and leave the XOUT pin open.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
INT0 to INT7
I
INT interrupt input pins.
Key input interrupt
KI0 to KI7
I
Key input interrupt input pins
Timer RA
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between pins XCIN and XCOUT. (1)
To use an external clock, input it to the XCIN pin and leave the
XCOUT pin open.
TRAIO
I/O
TRAO
O
Timer RA output pin
Timer RB
TRBO
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
TRCTRG
I
External trigger input pin
Timer RD
Timer RA I/O pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RC I/O pins
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O pins
TRDCLK
I
Timer RE
TREO
O
Divided clock output pin
Timer RG
TRGCLKA, TRGCLKB
I
Timer RG input pins
Serial interface
TRGIOA, TRGIOB
I/O
External clock input pin
Timer RG I/O pins
CLK0, CLK1, CLK2
I/O
RXD0, RXD1, RXD2
I
Transfer clock I/O pins
TXD0, TXD1, TXD2
O
Serial data output pins
CTS2
I
Transmission control input pin
RTS2
O
Reception control output pin
SCL2
I/O
I2C mode clock I/O pin
SDA2
I/O
I2C mode data I/O pin
Serial data input pins
I: Input
O: Output
I/O: Input and output
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
REJ03B0243-0030 Rev.0.30
Page 27 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 1.20
Pin Functions (2)
Item
I2C
bus
SSU
Pin Name
I/O Type
Description
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
Data I/O pin
SSO
I/O
Reference voltage
input
VREF
I
Reference voltage input pin for the A/D converter and the D/A
converter
A/D converter
AN0 to AN11
I
A/D converter analog input pins
ADTRG
I
AD external trigger input pin
D/A converter
DA0, DA1
O
D/A converter output pins
Comparator A
LVCMP1, LVCMP2
I
Comparator A analog voltage input pins
LVREF
I
Comparator A reference voltage input pin
LVCOUT1, LVCOUT2
O
Comparator A output pins
Comparator B
IVCMP1, IVCMP3
I
Comparator B analog voltage input pins
IVREF1, IVREF3
I
Comparator B reference voltage input pins
Voltage detection
circuit
LVCMP2
I
Detection target voltage input pin for voltage detection 2
I/O ports
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0, P5_3,
P6_0 to P6_7
P7_0 to P7_7,
P10_0 to P10_7,
P11_0 to P11_7,
P12_0 to P12_3,
P13_0 to P13_7
Segment output
SEG0 to SEG55
O
LCD segment output pins
Common output
COM0 to COM7
O
LCD common output pins
Voltage multiplier
capacity connect
pins
CL1, CL2
O
Connect pins for the LCD control voltage multiplier
VL1
I/O
Apply the voltage: 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VL4.
VL1 can be used as the reference potential input or output pin
when setting the voltage multiplier.
LCD power supply
VL2 to VL4
I/O
I
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Ports P10_0 to P10_7 and P11_0 to P11_7 can be used as
LED drive ports.
I: Input
O: Output
I/O: Input and output
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
REJ03B0243-0030 Rev.0.30
Page 28 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit (CPU)
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register banks.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
INTBH
Interrupt table register
INTBL
The 4 high-order bits of INTB are INTBH and
the 16 low-order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers configure a register bank.
There are two sets of register banks.
Figure 2.1
CPU Registers
REJ03B0243-0030 Rev.0.30
Page 29 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0243-0030 Rev.0.30
Page 30 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0243-0030 Rev.0.30
Page 31 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
3. Memory
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
3.
Memory
Figure 3.1 is a Memory Map of each group. Each group has a 1-Mbyte address space from addresses 00000h to
FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For
example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 6-Kbyte internal
RAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as a
stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral
function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be
accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0FFD8h
0XXXXh
02C00h
02FFFh
03000h
Reserved area
0FFDCh
SFR
(Refer to 4. Special Function
Registers (SFRs))
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
Internal ROM
(program ROM)
0FFFFh
(Reserved)
Reset
0FFFFh
Internal ROM
(program ROM)
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte),
block C (1 Kbyte), and block D (1 Kbyte).
2. Blank spaces are reserved. No access is allowed.
ZZZZZh
FFFFFh
Internal ROM
Part Number
Capacity
Address
0YYYYh
Internal RAM
Address
ZZZZZh
Capacity
Address
0XXXXh
01BFFh
R5F2L357A***, R5F2L367A***, R5F2L387A***, R5F2L3A7A***
48 Kbytes
04000h
−
6 Kbytes
R5F2L358A***, R5F2L368A***, R5F2L388A***, R5F2L3A8A***
64 Kbytes
04000h
13FFFh
8 Kbytes
023FFh
R5F2L35AA***, R5F2L36AA***, R5F2L38AA***, R5F2L3AAA***
96 Kbytes
04000h
1BFFFh
10 Kbytes
02BFFh
R5F2L35CA***, R5F2L36CA***, R5F2L38CA***, R5F2L3ACA***
128 Kbytes
04000h
23FFFh
10 Kbytes
02BFFh
Available
R5F2L357B***, R5F2L367B***, R5F2L387B***, R5F2L3A7B***
48 Kbytes
04000h
−
6 Kbytes
01BFFh
R5F2L358B***, R5F2L368B***, R5F2L388B***, R5F2L3A8B***
64 Kbytes
04000h
13FFFh
8 Kbytes
023FFh
10 Kbytes
02BFFh
10 Kbytes
02BFFh
R5F2L35AB***, R5F2L36AB***, R5F2L38AB***, R5F2L3AAB***
96 Kbytes
04000h
1BFFFh
R5F2L35CB***, R5F2L36CB***, R5F2L38CB***, R5F2L3ACB***
128 Kbytes
04000h
23FFFh
Figure 3.1
Memory Map
REJ03B0243-0030 Rev.0.30
Page 32 of 76
Jan 21, 2009
Data Flash
Not
available
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.16 list SFR
information.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
SFR Information (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00100000b
00100000b
00h
00h
00h
XXh (2)
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
Power-Off Mode Control Register 0
POMCR0
X0000000b
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
00h
When shipping
00h
00h
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
FRA4
FRA5
FRA6
When Shipping
When Shipping
When Shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit/Comparator A Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (4)
00100000b (5)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
1100X010b (4)
1100X011b (5)
10001010b
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. The CWR bit in the RSTFR register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off mode. Hardware reset, software
reset, or watchdog timer reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
REJ03B0243-0030 Rev.0.30
Page 33 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Address
Register
003Ah
Voltage Monitor 2 Circuit Control Register
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
Flash Memory Ready Interrupt Control Register
0042h
0043h
INT7 Interrupt Control Register
0044h
INT6 Interrupt Control Register
0045h
INT5 Interrupt Control Register
0046h
INT4 Interrupt Control Register
0047h
Timer RC Interrupt Control Register
0048h
Timer RD0 Interrupt Control Register
0049h
Timer RD1 Interrupt Control Register
004Ah
Timer RE Interrupt Control Register
004Bh
UART2 Transmit Interrupt Control Register
004Ch
UART2 Receive Interrupt Control Register
004Dh
Key Input Interrupt Control Register
004Eh
A/D Conversion Interrupt Control Register
004Fh
SSU Interrupt Control Register / IIC bus Interrupt Control Register (2)
0050h
0051h
UART0 Transmit Interrupt Control Register
0052h
UART0 Receive Interrupt Control Register
0053h
UART1 Transmit Interrupt Control Register
0054h
UART1 Receive Interrupt Control Register
0055h
INT2 Interrupt Control Register
0056h
Timer RA Interrupt Control Register
0057h
0058h
Timer RB Interrupt Control Register
0059h
INT1 Interrupt Control Register
005Ah
INT3 Interrupt Control Register
005Bh
005Ch
005Dh
INT0 Interrupt Control Register
005Eh
UART2 Bus Collision Detection Interrupt Control Register
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
Timer RG Interrupt Control Register
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
Voltage monitor 1 / Comparator A1 Interrupt Control Register
0073h
Voltage monitor 2 / Comparator A2 Interrupt Control Register
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ03B0243-0030 Rev.0.30
Page 34 of 76
Jan 21, 2009
VW2C
Symbol
After Reset
10000010b
FMRDYIC
XXXXX000b
INT7IC
INT6IC
INT5IC
INT4IC
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
S2RIC
KUPIC
ADIC
SSUIC/IICIC
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
TRGIC
XXXXX000b
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3) (1)
DTC Activation Control Register
Register
Symbol
DTCTL
00h
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTC Activation Enable Register 4
DTC Activation Enable Register 5
DTC Activation Enable Register 6
DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN4
DTCEN5
DTCEN6
00h
00h
00h
00h
00h
00h
00h
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
UART2 Digital Filter Function Select Register
URXDF
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 35 of 76
Jan 21, 2009
After Reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Address
Register
00C0h
A/D Register 0
00C1h
00C2h
A/D Register 1
00C3h
00C4h
A/D Register 2
00C5h
00C6h
A/D Register 3
00C7h
00C8h
A/D Register 4
00C9h
00CAh
A/D Register 5
00CBh
00CCh
A/D Register 6
00CDh
00CEh
A/D Register 7
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
A/D Mode Register
00D5h
A/D Input Select Register
00D6h
A/D Control Register 0
00D7h
A/D Control Register 1
00D8h
D/A 0 Register
00D9h
D/A 1 Register
00DAh
00DBh
00DCh
D/A Control Register
00DDh
00DEh
00DFh
00E0h
Port P0 Register
00E1h
Port P1 Register
00E2h
Port P0 Direction Register
00E3h
Port P1 Direction Register
00E4h
Port P2 Register
00E5h
Port P3 Register
00E6h
Port P2 Direction Register
00E7h
Port P3 Direction Register
00E8h
Port P4 Register
00E9h
Port P5 Register
00EAh
Port P4 Direction Register
00EBh
Port P5 Direction Register
00ECh
Port P6 Register
00EDh
Port P7 Register
00EEh
Port P6 Direction Register
00EFh
Port P7 Direction Register
00F0h
00F1h
00F2h
00F3h
00F4h
Port P10 Register
00F5h
Port P11 Register
00F6h
Port P10 Direction Register
00F7h
Port P11 Direction Register
00F8h
Port P12 Register
00F9h
Port P13 Register
00FAh
Port P12 Direction Register
00FBh
Port P13 Direction Register
00FCh
00FDh
00FEh
00FFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 36 of 76
Jan 21, 2009
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
After Reset
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
ADMOD
ADINSEL
ADCON0
ADCON1
DA0
DA1
00h
11000000b
00h
00h
00h
00h
DACON
00h
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
P10
P11
PD10
PD11
P12
P13
PD12
PD13
XXh
XXh
00h
00h
XXh
XXh
00h
00h
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Timer RE Counter Data Register
Timer RE Minute Data Register / Timer RE Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
XXh
XXh
XXh
XXh
XXXXX0XXb
XXh
00001000b
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
TRCOER
TRCADCR
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
Timer RD Control Expansion Register
Timer RD Trigger Control Register
Timer RD Start Register
Timer RD Mode Register
Timer RD PWM Mode Register
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
TRDECR
TRDADCR
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
00h
00h
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
00h
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 37 of 76
Jan 21, 2009
After Reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Address
Register
0140h
Timer RD Control Register 0
0141h
Timer RD I/O Control Register A0
0142h
Timer RD I/O Control Register C0
0143h
Timer RD Status Register 0
0144h
Timer RD Interrupt Enable Register 0
0145h
Timer RD PWM Mode Output Level Control Register 0
0146h
Timer RD Counter 0
0147h
0148h
Timer RD General Register A0
0149h
014Ah
Timer RD General Register B0
014Bh
014Ch
Timer RD General Register C0
014Dh
014Eh
Timer RD General Register D0
014Fh
0150h
Timer RD Control Register 1
0151h
Timer RD I/O Control Register A1
0152h
Timer RD I/O Control Register C1
0153h
Timer RD Status Register 1
0154h
Timer RD Interrupt Enable Register 1
0155h
Timer RD PWM Mode Output Level Control Register 1
0156h
Timer RD Counter 1
0157h
0158h
Timer RD General Register A1
0159h
015Ah
Timer RD General Register B1
015Bh
015Ch
Timer RD General Register C1
015Dh
015Eh
Timer RD General Register D1
015Fh
0160h
UART1 Transmit/Receive Mode Register
0161h
UART1 Bit Rate Register
0162h
UART1 Transmit Buffer Register
0163h
0164h
UART1 Transmit/Receive Control Register 0
0165h
UART1 Transmit/Receive Control Register 1
0166h
UART1 Receive Buffer Register
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
Timer RG Mode Register
0171h
Timer RG Count Control Register
0172h
Timer RG Control Register
0173h
Timer RG Interrupt Enable Register
0174h
Timer RG Status Register
0175h
Timer RG I/O Control Register
0176h
Timer RG Counter
0177h
0178h
Timer RG General Register A
0179h
017Ah
Timer RG General Register B
017Bh
017Ch
Timer RG General Register C
017Dh
017Eh
Timer RG General Register D
017Fh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 38 of 76
Jan 21, 2009
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
U1MR
U1BRG
U1TB
U1C0
U1C1
U1RB
TRGMR
TRGCNTC
TRGCR
TRGIER
TRGSR
TRGIOR
TRG
TRGGRA
TRGGRB
TRGGRC
TRGGRD
After Reset
00h
10001000b
10001000b
11100000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
01000000b
00h
10000000b
11110000b
11100000b
00h
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Address
Register
0180h
Timer RA Pin Select Register
0181h
Timer RB/RC Pin Select Register
0182h
Timer RC Pin Select Register 0
0183h
Timer RC Pin Select Register 1
0184h
Timer RD Pin Select Register 0
0185h
Timer RD Pin Select Register 1
0186h
0187h
Timer RG Pin Select Register
0188h
UART0 Pin Select Register
0189h
UART1 Pin Select Register
018Ah
UART2 Pin Select Register 0
018Bh
UART2 Pin Select Register 1
018Ch
SSU/IIC Pin Select Register
018Dh
Key Input Pin Select Register
018Eh
INT Interrupt Input Pin Select Register
018Fh
I/O Function Pin Select Register
0190h
0191h
0192h
0193h
SS Bit Counter Register
0194h
SS Transmit Data Register L / IIC bus Transmit Data Register (2)
0195h
SS Transmit Data Register H
0196h
SS Receive Data Register L / IIC bus Receive Data Register (2)
0197h
SS Receive Data Register H (2)
0198h
SS Control Register H / IIC bus Control Register 1 (2)
0199h
SS Control Register L / IIC bus Control Register 2 (2)
019Ah
SS Mode Register / IIC bus Mode Register (2)
019Bh
SS Enable Register / IIC bus Interrupt Enable Register (2)
019Ch
SS Status Register / IIC bus Status Register (2)
019Dh
SS Mode Register 2 / Slave Address Register (2)
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
Flash Memory Status Register
01B3h
01B4h
Flash Memory Control Register 0
01B5h
Flash Memory Control Register 1
01B6h
Flash Memory Control Register 2
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ03B0243-0030 Rev.0.30
Page 39 of 76
Jan 21, 2009
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
TRDPSR0
TRDPSR1
00h
00h
00h
00h
00h
00h
After Reset
TRGPSR
U0SR
U1SR
U2SR0
U2SR1
SSUIICSR
KISR
INTSR
PINSR
00h
00h
00h
00h
00h
00h
00h
00h
00h
SSBR
SSTDR/ICDRT
SSTDRH
SSRDR/ICDRR
SSRDRH
SSCRH/ICCR1
SSCRL/ICCR2
SSMR/ICMR
SSER/ICIER
SSSR/ICSR
SSMR2/SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00010000b/00011000b
00h
00h/0000X000b
00h
FST
10000X00b
FMR0
FMR1
FMR2
00h
00h
00h
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address
Register
01C0h
Address Match Interrupt Register 0
01C1h
01C2h
01C3h
Address Match Interrupt Enable Register 0
01C4h
Address Match Interrupt Register 1
01C5h
01C6h
01C7h
Address Match Interrupt Enable Register 1
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
Port P0 Pull-Up Control Register
01E1h
Port P1 Pull-Up Control Register
01E2h
Port P2 Pull-Up Control Register
01E3h
Port P3 Pull-Up Control Register
01E4h
Port P4 Pull-Up Control Register
01E5h
Port P5 Pull-Up Control Register
01E6h
Port P6 Pull-Up Control Register
01E7h
Port P7 Pull-Up Control Register
01E8h
01E9h
01EAh
Port 10 Pull-Up Control Register
01EBh
Port 11 Pull-Up Control Register
01ECh
Port 12 Pull-Up Control Register
01EDh
Port 13 Pull-Up Control Register
01EEh
01EFh
01F0h
Port P10 Drive Capacity Control Register
01F1h
Port P11 Drive Capacity Control Register
01F2h
01F3h
01F4h
01F5h
Input Threshold Control Register 0
01F6h
Input Threshold Control Register 1
01F7h
Input Threshold Control Register 2
01F8h
Comparator B Control Register 0
01F9h
01FAh
External Input Enable Register 0
01FBh
External Input Enable Register 1
01FCh
INT Input Filter Select Register 0
01FDh
INT Input Filter Select Register 1
01FEh
Key Input Enable Register 0
01FFh
Key Input Enable Register 1
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 40 of 76
Jan 21, 2009
Symbol
RMAD0
AIER1
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
P0PUR
P1PUR
P2PUR
P3PUR
P4PUR
P5PUR
P6PUR
P7PUR
00h
00h
00h
00h
00h
00h
00h
00h
P10PUR
P11PUR
P12PUR
P13PUR
00h
00h
00h
00h
P10DRR
P11DRR
00h
00h
VLT0
VLT1
VLT2
INTCMP
00h
00h
00h
00h
INTEN
INTEN1
INTF
INTF1
KIEN
KIEN1
00h
00h
00h
00h
00h
00h
AIER0
RMAD1
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Information (9) (1)
Address
Register
0200h
LCD Control Register
0201h
LCD Bias Control Register
0202h
LCD Display Control Register
0203h
LCD Clock Control Register
0204h
0205h
0206h
LCD Port Select Register 0
0207h
LCD Port Select Register 1
0208h
LCD Port Select Register 2
0209h
LCD Port Select Register 3
020Ah
LCD Port Select Register 4
020Bh
LCD Port Select Register 5
020Ch
LCD Port Select Register 6
020Dh
LCD Port Select Register 7
020Eh
020Fh
0210h
LCD Display Data Register
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 41 of 76
Jan 21, 2009
LCR0
LCR1
LCR2
LCR3
Symbol
After Reset
00h
00h
X0000000b
00h
LSE0
LSE1
LSE2
LSE3
LSE4
LSE5
LSE6
LSE7
00h
00h
00h
00h
00h
00h
00h
00h
LRA0L
LRA1L
LRA2L
LRA3L
LRA4L
LRA5L
LRA6L
LRA7L
LRA8L
LRA9L
LRA10L
LRA11L
LRA12L
LRA13L
LRA14L
LRA15L
LRA16L
LRA17L
LRA18L
LRA19L
LRA20L
LRA21L
LRA22L
LRA23L
LRA24L
LRA25L
LRA26L
LRA27L
LRA28L
LRA29L
LRA30L
LRA31L
LRA32L
LRA33L
LRA34L
LRA35L
LRA36L
LRA37L
LRA38L
LRA39L
LRA40L
LRA41L
LRA42L
LRA43L
LRA44L
LRA45L
LRA46L
LRA47L
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Information (10) (1)
Address
Register
0240h
LCD Display Data Register
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
LCD Display Control Data Register
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 42 of 76
Jan 21, 2009
Symbol
LRA48L
LRA49L
LRA50L
LRA51L
LRA52L
LRA53L
LRA54L
LRA55L
LRA56L
LRA57L
LRA58L
LRA59L
LRA60L
LRA61L
LRA62L
LRA63L
LRA64L
LRA65L
LRA66L
LRA67L
LRA68L
LRA69L
LRA70L
LRA71L
LRA72L
LRA73L
LRA74L
LRA75L
LRA76L
LRA77L
LRA78L
LRA79L
LRA80L
LRA81L
LRA82L
LRA83L
LRA84L
LRA85L
LRA86L
LRA87L
LRA88L
LRA89L
LRA90L
LRA91L
LRA92L
LRA93L
LRA94L
LRA95L
LRA0H
LRA1H
LRA2H
LRA3H
LRA4H
LRA5H
LRA6H
LRA7H
LRA8H
LRA9H
LRA10H
LRA11H
LRA12H
LRA13H
LRA14H
LRA15H
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Information (11) (1)
Address
Register
0280h
LCD Display Control Data Register
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 43 of 76
Jan 21, 2009
Symbol
LRA16H
LRA17H
LRA18H
LRA19H
LRA20H
LRA21H
LRA22H
LRA23H
LRA24H
LRA25H
LRA26H
LRA27H
LRA28H
LRA29H
LRA30H
LRA31H
LRA32H
LRA33H
LRA34H
LRA35H
LRA36H
LRA37H
LRA38H
LRA39H
LRA40H
LRA41H
LRA42H
LRA43H
LRA44H
LRA45H
LRA46H
LRA47H
LRA48H
LRA49H
LRA50H
LRA51H
LRA52H
LRA53H
LRA54H
LRA55H
LRA56H
LRA57H
LRA58H
LRA59H
LRA60H
LRA61H
LRA62H
LRA63H
LRA64H
LRA65H
LRA66H
LRA67H
LRA68H
LRA69H
LRA70H
LRA71H
LRA72H
LRA73H
LRA74H
LRA75H
LRA76H
LRA77H
LRA78H
LRA79H
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.12
4. Special Function Registers (SFRs)
SFR Information (12) (1)
Address
Register
02C0h
LCD Display Control Data Register
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 44 of 76
Jan 21, 2009
Symbol
LRA80H
LRA81H
LRA82H
LRA83H
LRA84H
LRA85H
LRA86H
LRA87H
LRA88H
LRA89H
LRA90H
LRA91H
LRA92H
LRA93H
LRA94H
LRA95H
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.13
Address
2C00h
2C01h
2C02h
2C03h
2C04h
2C05h
2C06h
2C07h
2C08h
2C09h
2C0Ah
:
:
2C3Ah
2C3Bh
2C3Ch
2C3Dh
2C3Eh
2C3Fh
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
4. Special Function Registers (SFRs)
SFR Information (13) (1)
Register
Symbol
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Control Data 0
DTCD0
DTC Control Data 1
DTCD1
DTC Control Data 2
DTCD2
DTC Control Data 3
DTCD3
DTC Control Data 4
DTCD4
DTC Control Data 5
DTCD5
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 45 of 76
Jan 21, 2009
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.14
4. Special Function Registers (SFRs)
SFR Information (14) (1)
Address
Register
2C70h
DTC Control Data 6
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
DTC Control Data 7
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
DTC Control Data 8
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
DTC Control Data 9
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
DTC Control Data 10
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
DTC Control Data 11
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
DTC Control Data 12
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
DTC Control Data 13
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 46 of 76
Jan 21, 2009
Symbol
DTCD6
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.15
4. Special Function Registers (SFRs)
SFR Information (15) (1)
Address
Register
2CB0h
DTC Control Data 14
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
DTC Control Data 15
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
DTC Control Data 16
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
DTC Control Data 17
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
DTC Control Data 18
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
DTC Control Data 19
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
DTC Control Data 20
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
DTC Control Data 21
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
REJ03B0243-0030 Rev.0.30
Page 47 of 76
Jan 21, 2009
Symbol
DTCD14
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 4.16
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
2D01h
4. Special Function Registers (SFRs)
SFR Information (16) (1)
DTC Control Data 22
Register
Symbol
DTCD22
DTC Control Data 23
DTCD23
0FFDBh
Option Function Select Register 2
:
0FFFFh
Option Function Select Register
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. This register cannot be changed by a program. Use a flash programmer to write to it.
REJ03B0243-0030 Rev.0.30
Page 48 of 76
Jan 21, 2009
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
OFS2
(Note 2)
OFS
(Note 2)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
5.
Electrical Characteristics
5.1
Absolute Maximum Ratings
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
VCC/AVCC Supply voltage
VI
Input voltage
Unit
−0.3 to 6.5
V
XIN
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XIN
XIN-XOUT oscillation on
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
−0.3 to VL2
V
R8C/L35A, R8C/L35B
VL1 to VL4
V
R8C/L36A, R8C/L36B,
R8C/L38A, R8C/L38B,
R8C/L3AA, R8C/L3AB
VL1 to VL3
V
VL3
VL2 to VL4
V
VL4
VL3 to 6.5
V
VL1
VL2
−0.3 to VCC + 0.3
V
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XIN-XOUT oscillation on
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
Other pins
VO
Rated Value
Output voltage XOUT
XOUT
−0.3 to VL2
V
R8C/L35A, R8C/L35B
VL1 to VL4
V
R8C/L36A, R8C/L36B,
R8C/L38A, R8C/L38B,
R8C/L3AA, R8C/L3AB
VL1 to VL3
V
VL3
VL2 to VL4
V
VL4
−0.3 to 6.5
V
CL1, CL2
−0.3 to 6.5
V
COM0 to COM7
−0.3 to VL4
V
−0.3 to VL4
V
VL1
VL2
SEG0 to SEG55
Other pins
−40°C ≤ Topr ≤ 85°C
Pd
Power dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
−0.3 to VCC + 0.3
V
500
mW
−20 to 85 (N version) /
−40 to 85 (D version)
°C
−65 to 150
°C
Note:
1. For the register settings for each operation, refer to 7. I/O Ports and 9. Clock Generation Circuit of Hardware Manual
(REJ09B0441).
REJ03B0243-0030 Rev.0.30
Page 49 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
5.2
Recommended Operating Conditions
Table 5.2
Recommended Operating Conditions
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Sum of all pins IOH(peak)
Min.
1.8
−
0.8 VCC
0.8 VCC
0.9 VCC
0.5 VCC
0.55 VCC
0.65 VCC
0.65 VCC
0.7 VCC
0.8 VCC
0.85 VCC
0.85 VCC
0.85 VCC
0
0
0
0
0
0
0
0
0
0
0
0
−
Standard
Typ.
−
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max.
5.5
−
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.2 VCC
0.2 VCC
0.05 VCC
0.2 VCC
0.2 VCC
0.2 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.55 VCC
0.45 VCC
0.35 VCC
−160
Sum of all pins IOH(avg)
−
−
−80
mA
Port P10, P11 (2)
Other pins
Average output Port P10, P11 (2)
“H” current (1)
Other pins
Peak sum output Sum of all pins IOL(peak)
“L” current
Average sum
Sum of all pins IOL(avg)
output “L” current
Peak output “L” Port P10, P11 (2)
current
Other pins
Average output Port P10, P11 (2)
“L” current (1)
Other pins
XIN clock input oscillation frequency
−
−
−
−
−
−
−
−
−
−
−40
−10
−20
−5
160
mA
mA
mA
mA
mA
−
−
80
mA
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.8 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
−
−
−
−
−
−
−
32
−
−
−
−
−
−
32.768
−
40
10
20
5
20
5
50
40
mA
mA
mA
mA
MHz
MHz
kHz
MHz
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
−
−
−
−
0
0
−
−
−
−
−
−
20
5
20
5
20
5
MHz
MHz
MHz
MHz
MHz
MHz
Symbol
Parameter
Conditions
VCC/AVCC Supply voltage
VSS/AVSS Supply voltage
Input “H” voltage Other than CMOS input
VIH
CMOS Input level
input
switching
function
(I/O port)
Input level selection
: 0.35 VCC
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
VIL
Input “L” voltage Other than CMOS input
CMOS Input level
input
switching
function
(I/O port)
Input level selection
: 0.35 VCC
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
IOH(sum)
IOH(sum)
IOH(peak)
IOH(avg)
IOL(sum)
IOL(sum)
IOL(peak)
IOL(avg)
f(XIN)
Peak sum output
“H” current
Average sum
output “H” current
Peak output “H”
current
XCIN clock input oscillation frequency
f(XCIN)
fOCO40M When used as the count source for timer RC, timer RD, or
timer RG (3)
fOCO-F fOCO-F frequency
−
System clock frequency
f(BCLK)
CPU clock frequency
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
Notes:
1. The average output current indicates the average value of current measured during 100 ms.
2. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.
3. fOCO40M can be used as the count source for timer RC, timer RD, or timer RG in the range of VCC = 2.7 V to 5.5V.
REJ03B0243-0030 Rev.0.30
Page 50 of 76
Jan 21, 2009
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
P0
P1
P2
P3
P4
P5_0 to P5_3
P6
P7
P10
P11
P12_0 to P12_3
P13
Figure 5.1
30 pF
Ports P0 to P4, P5_0 to P5_3, P6, P7, P10, P11, P12_0 to P12_3, and P13 Timing
Measurement Circuit
REJ03B0243-0030 Rev.0.30
Page 51 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
5.3
Peripheral Function Characteristics
Table 5.3
A/D Converter Characteristics
(VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) /
−40 to 85°C (D version), unless otherwise specified.)
Symbol
Parameter
−
Resolution
−
Absolute accuracy
Conditions
8-bit mode
φAD
Max.
Unit
−
−
10
Bit
AN0 to AN19 input
−
−
±3
LSB
Vref = AVCC = 3.3 V
AN0 to AN19 input
−
−
±5
LSB
Vref = AVCC = 3.0 V
AN0 to AN19 input
−
−
±5
LSB
Vref = AVCC = 2.2 V
AN0 to AN19 input
−
−
±5
LSB
Vref = AVCC = 5.0 V
AN0 to AN19 input
−
−
±2
LSB
Vref = AVCC = 3.3 V
AN0 to AN19 input
−
−
±2
LSB
Vref = AVCC = 3.0 V
AN0 to AN19 input
−
−
±2
LSB
Vref = AVCC = 2.2 V
AN0 to AN19 input
−
−
±2
LSB
(1)
2
−
20
MHz
3.2 ≤ Vref = AVCC ≤ 5.5 V (1)
2
−
16
MHz
2.7 ≤ Vref = AVCC ≤ 5.5 V (1)
2
−
10
MHz
2.2 ≤ Vref = AVCC ≤ 5.5 V (1)
2
−
5
MHz
4.0 ≤ Vref = AVCC ≤ 5.5 V
A/D conversion clock
Typ.
Vref = AVCC = 5.0 V
Vref = AVCC
10-bit mode
Standard
Min.
−
Tolerance level impedance
−
3
−
kΩ
DNL
Differential non-linearity error
−
−
±1
LSB
tCONV
Conversion time
10-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.15
−
−
µs
8-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.15
−
−
µs
0.75
−
−
µs
−
45
−
µA
2.2
−
AVCC
V
0
−
Vref
V
tSAMP
Sampling time
φAD = 20 MHz
IVref
Vref current
Vcc = 5 V, XIN = f1 = φAD = 20 MHz
Vref
Reference voltage
VIA
Analog input voltage
(2)
Notes:
1. When the CPU and flash memory stop, the A/D conversion result will be undefined.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
REJ03B0243-0030 Rev.0.30
Page 52 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.4
D/A Converter Characteristics
(VCC/AVCC = Vref = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C
(D version), unless otherwise specified.)
Symbol
Parameter
Standard
Conditions
Min.
Typ.
Max.
Unit
−
Resolution
−
−
8
Bit
−
Absolute accuracy
−
−
2.5
LSB
tsu
Setup time
−
−
3
µs
RO
Output resistor
−
6
−
kΩ
IVref
Reference power input current
−
−
1.5
mA
(Note 1)
Note:
1. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included.
Table 5.5
Comparator A Characteristics
(VCC = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
LVREF
External reference voltage input range
1.4
−
VCC
V
LVCMP1,
LVCMP2
External comparison voltage input
range
−0.3
−
VCC + 0.3
V
−
Offset
mV
−
Comparator output delay time (1)
−
Comparator operating current
−
50
200
At falling, VI = Vref − 100 mV
−
3
−
µs
At falling, VI = Vref − 1 V or below
−
1.5
−
µs
At rising, VI = Vref + 100 mV
−
2
−
µs
At rising, VI = Vref + 1 V or above
−
0.5
−
µs
VCC = 5.0 V
−
0.5
−
µA
Note:
1. When the digital filter is disabled.
Table 5.6
Comparator B Characteristics
(VCC = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
0
−
VCC − 1.4
−0.3
−
VCC + 0.3
V
−
5
100
mV
V
Vref
IVREF1, IVREF3 input reference voltage
VI
IVCMP1, IVCMP3 input voltage
−
Offset
td
Comparator output delay time (1)
VI = Vref ± 100 mV
−
0.1
−
µs
ICMP
Comparator operating current
VCC = 5.0 V
−
17.5
−
µA
Note:
1. When the digital filter is disabled.
REJ03B0243-0030 Rev.0.30
Page 53 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.7
Flash Memory (Program ROM) Characteristics
(VCC = 2.7 to 5.5 V and Topr = 0 to 60°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
−
Program/erase endurance (1)
1,000 (2)
−
−
times
−
Byte program time
−
80
TBD
µs
−
Block erase time
−
0.3
TBD
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
5 + CPU clock
× 3 cycles
ms
−
Interval from erase start/restart until
following suspend request
0
−
−
µs
−
Suspend interval necessary for autoerasure to complete
33
−
−
ms
−
Time from suspend until erase restart
−
−
30 + CPU clock
× 1 cycle
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
1.8
−
5.5
V
−
Program, erase temperature
0
−
60
°C
−
Data hold time (6)
20
−
−
year
Ambient temperature = 55°C
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
REJ03B0243-0030 Rev.0.30
Page 54 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.8
Flash Memory (Data flash Block A to Block D) Characteristics
(VCC = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Standard
Conditions
Min.
Typ.
Max.
Unit
−
Program/erase endurance (1)
10,000 (2)
−
−
times
−
Byte program time
(program/erase endurance ≤ 1,000 times)
−
160
TBD
µs
−
Byte program time
(program/erase endurance > 1,000 times)
−
300
−
µs
−
Block erase time
(program/erase endurance ≤ 1,000 times)
−
0.2
−
s
−
Block erase time
(program/erase endurance > 1,000 times)
−
0.3
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
5 + CPU clock
× 3 cycles
ms
−
Interval from erase start/restart until
following suspend request
0
−
−
µs
−
Suspend interval necessary for autoerasure to complete
33
−
−
ms
−
Time from suspend until erase restart
−
−
30 + CPU clock
× 1 cycle
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
1.8
−
5.5
V
−
Program, erase temperature
−20 (6)
−
85
°C
−
Data hold time (7)
20
−
−
year
Ambient temperature = 55 °C
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. −40°C for D version.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST6 bit
Fixed time
Clock-dependent
time
td(SR-SUS)
FST6: Bit in FST register
FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
REJ03B0243-0030 Rev.0.30
Page 55 of 76
Jan 21, 2009
Access restart
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.9
Voltage Detection 0 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Vdet0
Parameter
Standard
Unit
Min.
Typ.
Max.
Voltage detection level Vdet0_0 (1)
TBD
1.90
TBD
V
(1)
TBD
2.35
TBD
V
Voltage detection level Vdet0_2 (1)
TBD
2.85
TBD
V
Voltage detection level Vdet0_3 (1)
TBD
3.80
TBD
V
At the falling of Vcc from 5 V
to (Vdet0_0 − 0.1) V
−
6
150
µs
VCA25 = 1, VCC = 5.0 V
−
1.5
−
µA
−
−
100
µs
Voltage detection level Vdet0_1
−
Condition
Voltage detection 0 circuit response time
(3)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit
operation starts (2)
Notes:
1. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
3. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.10
Voltage Detection 1 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet1_0 (1)
At the falling of VCC
TBD
2.20
TBD
V
Voltage detection level Vdet1_1 (1)
At the falling of VCC
TBD
2.35
TBD
V
Voltage detection level Vdet1_2 (1)
At the falling of VCC
TBD
2.50
TBD
V
Voltage detection level Vdet1_3
(1)
At the falling of VCC
TBD
2.65
TBD
V
Voltage detection level Vdet1_4
(1)
At the falling of VCC
TBD
2.80
TBD
V
Voltage detection level Vdet1_5 (1)
At the falling of VCC
TBD
2.95
TBD
V
Voltage detection level Vdet1_6 (1)
At the falling of VCC
TBD
3.10
TBD
V
Voltage detection level Vdet1_7
(1)
At the falling of VCC
TBD
3.25
TBD
V
Voltage detection level Vdet1_8
(1)
At the falling of VCC
TBD
3.40
TBD
V
Voltage detection level Vdet1_9 (1)
At the falling of VCC
TBD
3.55
TBD
V
Voltage detection level Vdet1_A (1)
At the falling of VCC
TBD
3.70
TBD
V
Voltage detection level Vdet1_B
(1)
At the falling of VCC
TBD
3.85
TBD
V
Voltage detection level Vdet1_C
(1)
At the falling of VCC
TBD
4.00
TBD
V
Voltage detection level Vdet1_D (1)
At the falling of VCC
TBD
4.15
TBD
V
Voltage detection level Vdet1_E (1)
At the falling of VCC
TBD
4.30
TBD
V
(1)
At the falling of VCC
TBD
4.45
TBD
V
Vdet1_0 to Vdet1_5
selected
−
0.07
−
V
Vdet1_6 to Vdet1_F
selected
−
0.10
−
V
Voltage detection 1 circuit response time (2)
At the falling of Vcc from
5 V to (Vdet1_0 − 0.1) V
−
60
150
µs
−
Voltage detection circuit self power consumption
VCA26 = 1, VCC = 5.0 V
−
1.7
−
µA
td(E-A)
Waiting time until voltage detection circuit operation
starts (3)
−
−
100
µs
Vdet1
Voltage detection level Vdet1_F
−
−
Hysteresis width at the rising of Vcc in voltage
detection 1 circuit
Notes:
1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
REJ03B0243-0030 Rev.0.30
Page 56 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.11
Voltage Detection 2 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Vdet2
Parameter
Voltage detection level Vdet2_0 (1)
Voltage detection level
Standard
Condition
Vdet2_EXT (1)
Min.
Typ.
Unit
Max.
At the falling of VCC
TBD
4.00
TBD
V
At the falling of LVCMP2
TBD
1.34
TBD
V
−
0.10
−
V
−
20
150
µs
−
1.7
−
µA
−
−
100
µs
−
Hysteresis width at the rising of Vcc in voltage detection
2 circuit
−
Voltage detection 2 circuit response time (2)
At the falling of Vcc from
5 V to (Vdet2_0 − 0.1) V
−
Voltage detection circuit self power consumption
VCA27 = 1, VCC = 5.0 V
td(E-A)
Waiting time until voltage detection circuit operation
starts (3)
Notes:
1. The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register.
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.12
Power-on Reset Circuit Characteristics (2)
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol
trth
Parameter
Condition
Standard
Min.
Typ.
Max.
0
−
50000
External power VCC rise gradient (1)
Unit
mV/msec
Notes:
1. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1)
Vdet0 (1)
trth
trth
External
Power VCC
0.5 V
Voltage detection 0
circuit response time
tw(por) (2)
Internal
reset signal
1
× 32
fOCO-S
1
× 32
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual (REJ09B0441) for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Characteristics
REJ03B0243-0030 Rev.0.30
Page 57 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.13
High-speed On-Chip Oscillator Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Symbol
−
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
TBD
40
TBD
MHz
High-speed on-chip oscillator frequency when
the FRA4 register correction value is written into
the FRA1 register and the FRA5 register
correction value into the FRA3 register (2)
TBD
36.864
TBD
MHz
High-speed on-chip oscillator frequency when
the FRA6 register correction value is written into
the FRA1 register and the FRA7 register
correction value into the FRA3 register
TBD
32
TBD
MHz
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 2.7 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 2.2 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 2.2 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
High-speed on-chip oscillator frequency after
reset
High-speed on-chip oscillator frequency
temperature • supply voltage dependence (1)
VCC = 5.0 V, Topr = 25°C
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
100
450
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
400
−
µA
Notes:
1. This indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator.
2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.14
Low-speed On-Chip Oscillator Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
112.5
125
137.5
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
30
100
kHz
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
3
−
µA
fOCO-WDT
Low-speed on-chip oscillator frequency for the
watchdog timer
60
125
250
kHz
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
30
100
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
2
−
µA
Table 5.15
Power Supply Circuit Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = 25°C, unless otherwise specified.)
Symbol
td(P-R)
Parameter
Condition
Time for internal power supply stabilization during
power-on (1)
Note:
1. Waiting time until the internal power supply generation circuit stabilizes during power-on.
REJ03B0243-0030 Rev.0.30
Page 58 of 76
Jan 21, 2009
Standard
Min.
Typ.
Max.
−
−
2000
Unit
µs
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.16
LCD Drive Control Circuit Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C
(D version), unless otherwise specified.)
Symbol
Parameter
VLCD
LCD power supply voltage
VL3
VL3 voltage
VL2
VL2 voltage
VL1
VL1 voltage
−
VL1 internally-generated voltage accuracy (1)
Condition
Standard
Min.
Typ.
Max.
Unit
2.2
−
5.5
V
VL2
−
VL4
V
R8C/L35A, R8C/L35B
VL1
−
VL4
V
R8C/L36A, R8C/L36B,
R8C/L38A, R8C/L38B,
R8C/L3AA, R8C/L3AB
VL1
−
VL3
V
VLCD = VL4
1
−
VL2
V
Setting
voltage
−0.4
Setting
voltage
Setting
voltage
+0.4
V
f(FR)
Frame frequency
50
−
180
Hz
ILCD
LCD drive control circuit current
−
(Note 2)
−
µA
Notes:
1. The voltage is selected with bits LVLS0 to LVLS3 in the LCR1 register.
2. Refer to Table 5.19 DC Characteristics (2), Table 5.21 DC Characteristics (4), and Table 5.23 DC Characteristics (6).
Table 5.17
Power-Off Mode Characteristics
(VCC = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C
(D version), unless otherwise specified.)
Symbol
−
Parameter
Power-off mode operating supply voltage
REJ03B0243-0030 Rev.0.30
Page 59 of 76
Jan 21, 2009
Condition
Standard
Min.
Typ.
Max.
2.2
−
5.5
Unit
V
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
5.4
DC Characteristics
Table 5.18
Symbol
VOH
DC Characteristics (1) [4.0 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Standard
Condition
Output “H” voltage
VOL
Output “L” voltage
VT+-VT-
Hysteresis INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3, KI4,
KI5, KI6, KI7,
TRAIO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRGCLKA, TRGCLKB,
TRGIOA, TRGIOB,
ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
Min.
Typ.
Max.
Unit
Port P10, P11 (1)
VCC = 5V
IOH = −20 mA VCC − 2.0
−
VCC
Other pins
VCC = 5V
IOH = −5 mA
VCC − 2.0
−
VCC
V
VCC = 5V
IOL = 20 mA
−
−
2.0
V
VCC = 5V
IOL = 5 mA
Port P10, P11
(1)
Other pins
RESET,
WKUP0, WKUP1
V
−
−
2.0
V
0.1
0.5
−
V
0.2
1.0
−
V
µA
IIH
Input “H” current
VI = 5 V
−
−
5.0
IIL
Input “L” current
VI = 0 V
−
−
−5.0
µA
VI = 0 V
25
50
100
kΩ
RPULLUP Pull-up resistance
RfXIN
Feedback XIN
resistance
−
0.3
−
MΩ
RfXCIN
Feedback XCIN
resistance
−
14
−
MΩ
VRAM
RAM hold voltage
1.8
−
−
V
During stop mode
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.
REJ03B0243-0030 Rev.0.30
Page 60 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.19
DC Characteristics (2) [4.0 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Condition
Oscillation
Circuit
XIN XCIN
Symbol Parameter
(2)
Power
Highsupply
speed
current (1) clock
mode
ICC
20
MHz
16
MHz
10
MHz
20
MHz
16
MHz
10
MHz
Off
Highspeed
on-chip
Off
oscillator
mode
Off
LowOff
speed
on-chip
oscillator
mode
LowOff
speed
clock
Off
mode
Wait
mode
Off
Off
Off
Off
Off
Off
Off
Other
Max Unit
Min. Typ.
(3)
.
No
−
division
No
−
division
No
−
division
−
Divideby-8
Divide−
by-8
Divide−
by-8
No
−
division
−
Divideby-8
Divide- MSTIIC = 1
by-16 MSTTRD = 1
MSTTRC = 1
MSTTRG = 1
Divide- FMR27 = 1
by-8
VCA20 = 0
−
7.0
−
5.6 12.5 mA
−
3.6
−
mA
−
3.0
−
mA
−
2.2
−
mA
−
1.5
−
mA
−
7.0
15
mA
−
3.0
−
mA
−
1
−
mA
−
90
−
100 400 µA
Flash memory off
Program operation on RAM
−
55
While a WAIT instruction is executed
Peripheral clock operation
−
15
100 µA
While a WAIT instruction is executed
Peripheral clock off
−
4
90
µA
LCD drive control
circuit (4)
When external division
resistors are used
LCD drive control
circuit (5)
When the internal
voltage multiplier is used
While a WAIT instruction is executed
Peripheral clock off
Timer RE operation in real-time clock mode
−
7
−
µA
−
12
−
µA
−
3.5
−
µA
Topr = 25°C
Peripheral clock off
−
2.0
5.0
µA
Topr = 85°C
Peripheral clock off
−
15
−
µA
Power-off 0
Topr = 25°C
Power-off 0
Topr = 85°C
Power-off 1
Topr = 25°C
Power-off 1
Topr = 85°C
−
0.02 0.2
−
0.4
−
µA
−
1.3
2.6
µA
−
1.5
−
µA
Off
Off
125
kHz
32
kHz
Off
Off
No
FMR27 = 1
division VCA20 = 0
32
kHz
Off
Off
No
FMSTP = 1
division VCA20 = 0
Off
Off
Off
125
kHz
−
Off
Off
Off
125
kHz
−
Off
32
kHz
Off
Off
−
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
32
kHz
Off
Off
−
Off
Off
Off
Off
−
Off
Off
Off
Off
−
PowerOff
off mode
Off
Off
Off
Off
−
Off
Off
Off
−
−
Off
32
kHz
32
kHz
Off
Off
−
−
Off
Off
−
−
Off
5.
Off
Standard
Low-PowerCPU
Consumption
Clock
Setting
Off
Stop
mode
Notes:
1.
2.
3.
4.
Off
On-Chip
Oscillator
HighLowSpeed Speed
Off
125
kHz
Off
125
kHz
Off
125
kHz
Off
125
kHz
Off
125
kHz
Off
125
kHz
20 MHz 125
kHz
20 MHz 125
kHz
4 MHz
125
kHz
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
−
While a WAIT
instruction is
executed
Peripheral clock off
Timer RE operation
in real-time clock
mode
15
mA
400 µA
−
µA
µA
Vcc = 4.0 V to 5.5 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 5.0 V
VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors.
The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
REJ03B0243-0030 Rev.0.30
Page 61 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.20
DC Characteristics (3) [2.7 V ≤ Vcc < 4.0 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol
VOH
Parameter
Output “H” voltage
VOL
Output “L” voltage
VT+-VT-
Hysteresis
Condition
Standard
Min.
Typ.
Max.
Unit
Port P10, P11 (1)
IOH = −5 mA VCC − 0.5
−
VCC
Other pins
IOH = −1 mA VCC − 0.5
−
VCC
V
Port P10, P11 (1)
IOL = 5 mA
−
0.5
V
Other pins
IOL = 1 mA
−
V
−
−
0.5
V
INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3, KI4,
KI5, KI6, KI7,
TRAIO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRGCLKA, TRGCLKB,
TRGIOA, TRGIOB,
ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
0.05
0.4
−
V
RESET,
WKUP0, WKUP1
0.1
0.8
−
V
IIH
Input “H” current
VI = 3 V
−
−
5.0
µA
IIL
Input “L” current
VI = 0 V
−
−
−5.0
µA
VI = 0 V
30
100
170
kΩ
−
0.3
−
MΩ
−
14
−
MΩ
1.8
−
−
V
RPULLUP Pull-up resistance
RfXIN
Feedback resistance XIN
RfXCIN
Feedback resistance XCIN
VRAM
RAM hold voltage
During stop mode
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.
REJ03B0243-0030 Rev.0.30
Page 62 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.21
DC Characteristics (4) [2.7 V ≤ Vcc < 4.0 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Condition
Oscillation
Circuit
XIN XCIN
Symbol Parameter
(2)
Power
Highsupply
speed
current (1) clock
mode
ICC
20
MHz
10
MHz
20
MHz
10
MHz
Off
Off
Off
Off
Off
Off
Off
LowOff
speed
on-chip
oscillator
mode
LowOff
speed
clock
Off
mode
Off
Off
125
kHz
32
kHz
Off
Off
No
FMR27 = 1
division VCA20 = 0
32
kHz
Off
Off
No
FMSTP = 1
division VCA20 = 0
Off
Off
Off
125
kHz
−
Off
Off
Off
125
kHz
−
Off
32
kHz
Off
Off
−
Off
Off
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
Off
32
kHz
Off
Off
−
Off
Off
Off
Off
−
Off
Off
Off
Off
−
PowerOff
off mode
Off
Off
Off
Off
−
Off
Off
Off
−
−
Off
32
kHz
32
kHz
Off
Off
−
−
Off
Off
−
−
Off
Other
No
−
division
No
−
division
Divide−
by-8
−
Divideby-8
No
−
division
Divide−
by-8
No
−
division
−
Divideby-8
Divide- MSTIIC = 1
by-16 MSTTRD = 1
MSTTRC = 1
MSTTRG = 1
Divide- FMR27 = 1
by-8
VCA20 = 0
Off
Stop
mode
5.
Off
Standard
Low-PowerCPU
Consumption
Clock
Setting
Highspeed
on-chip
Off
oscillator
mode
Off
Wait
mode
Notes:
1.
2.
3.
4.
Off
On-Chip
Oscillator
HighLowSpeed Speed
Off
125
kHz
Off
125
kHz
Off
125
kHz
Off
125
kHz
20 MHz 125
kHz
20 MHz 125
kHz
10 MHz 125
kHz
10 MHz 125
kHz
4 MHz
125
kHz
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
−
Max Unit
Min. Typ.
(3)
.
−
7.0 14.5 mA
−
3.6
10
mA
−
3.0
−
mA
−
1.5
−
mA
−
7.0 14.5 mA
−
3.0
−
mA
−
4.0
−
mA
−
1.7
−
mA
−
1
−
mA
−
85
390 µA
−
90
400 µA
Flash memory off
Program operation on RAM
−
50
−
µA
While a WAIT instruction is executed
Peripheral clock operation
−
15
90
µA
While a WAIT instruction is executed
Peripheral clock off
−
5
80
µA
LCD drive control
circuit (4)
When external division
resistors are used
LCD drive control
circuit (5)
When the internal
voltage multiplier is used
While a WAIT instruction is executed
Peripheral clock off
Timer RE operation in real-time clock mode
−
5
−
µA
−
11
−
µA
−
3.5
−
µA
Topr = 25°C
Peripheral clock off
−
2
5.0
µA
Topr = 85°C
Peripheral clock off
−
13.0
−
µA
Power-off 0
Topr = 25°C
Power-off 0
Topr = 85°C
Power-off 1
Topr = 25°C
Power-off 1
Topr = 85°C
−
0.02 0.2
−
0.3
−
µA
−
1.0
2.0
µA
−
1.2
−
µA
While a WAIT
instruction is
executed
Peripheral clock off
Timer RE operation
in real-time clock
mode
µA
Vcc = 2.7 V to 4.0 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 3.0 V
VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors.
The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
REJ03B0243-0030 Rev.0.30
Page 63 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.22
DC Characteristics (5) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol
VOH
Parameter
Output “H” voltage
VOL
Output “L” voltage
VT+-VT-
Hysteresis
Condition
Standard
Min.
Typ.
Max.
Unit
Port P10, P11 (1)
IOH = −2 mA VCC − 0.5
−
VCC
Other pins
IOH = −1 mA VCC − 0.5
−
VCC
V
Port P10, P11 (1)
IOL = 2 mA
−
0.5
V
Other pins
IOL = 1 mA
−
V
−
−
0.5
V
INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3, KI4,
KI5, KI6, KI7,
TRAIO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRGCLKA, TRGCLKB,
TRGIOA, TRGIOB,
ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
0.05
0.4
−
V
RESET,
WKUP0, WKUP1
0.1
0.8
−
V
IIH
Input “H” current
VI = 1.8 V
−
−
4.0
µA
IIL
Input “L” current
VI = 0 V
−
−
−4.0
µA
VI = 0 V
60
160
420
kΩ
−
0.3
−
MΩ
−
14
−
MΩ
1.8
−
−
V
RPULLUP Pull-up resistance
RfXIN
Feedback resistance XIN
RfXCIN
Feedback resistance XCIN
VRAM
RAM hold voltage
During stop mode
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.
REJ03B0243-0030 Rev.0.30
Page 64 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.23
DC Characteristics (6) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Condition
Oscillation
Circuit
XIN XCIN
Symbol Parameter
(2)
Power
Highsupply
speed
current (1) clock
mode
Highspeed
on-chip
oscillator
mode
ICC
Off
Off
Off
Off
LowOff
speed
on-chip
oscillator
mode
LowOff
speed
clock
Off
mode
Off
Off
125
kHz
32
kHz
Off
Off
No
FMR27 = 1
division VCA20 = 0
32
kHz
Off
Off
No
FMSTP = 1
division VCA20 = 0
Off
Off
Off
125
kHz
−
Off
Off
Off
125
kHz
−
Off
32
kHz
Off
Off
−
32
kHz
Off
Off
−
Off
Off
Off
Off
−
Off
Off
Off
Off
−
PowerOff
off mode
Off
Off
Off
Off
−
Off
Off
Off
−
−
Off
32
kHz
32
kHz
Off
Off
−
−
Off
Off
−
−
Off
Notes:
1.
2.
3.
4.
5.
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
Off
Stop
mode
Other
No
−
division
Divide−
by-8
No
−
division
−
Divideby-8
Divide- MSTIIC = 1
by-16 MSTTRD = 1
MSTTRC = 1
MSTTRG = 1
Divide- FMR27 = 1
by-8
VCA20 = 0
Off
Off
Standard
Low-PowerCPU
Consumption
Clock
Setting
5
MHz
5
MHz
Off
Wait
mode
Off
On-Chip
Oscillator
HighLowSpeed Speed
Off
125
kHz
Off
125
kHz
5 MHz
125
kHz
5 MHz
125
kHz
4 MHz
125
kHz
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
−
Max Unit
Min. Typ.
(3)
.
−
2.2
−
mA
−
0.8
−
mA
−
2.5
10
mA
−
1.7
−
mA
−
1
−
mA
−
90
300 µA
−
90
400 µA
Flash memory off
Program operation on RAM
−
45
−
µA
While a WAIT instruction is executed
Peripheral clock operation
−
15
90
µA
While a WAIT instruction is executed
Peripheral clock off
−
4
80
µA
LCD drive control
circuit (4)
When external division
resistors are used
LCD drive control
circuit (5)
When the internal
voltage multiplier is used
While a WAIT instruction is executed
Peripheral clock off
Timer RE operation in real-time clock mode
−
4
−
µA
−
11
−
µA
−
3.5
−
µA
Topr = 25°C
Peripheral clock off
−
2.0
5.0
µA
Topr = 85°C
Peripheral clock off
−
13
−
µA
Power-off 0
Topr = 25°C
Power-off 0
Topr = 85°C
Power-off 1
Topr = 25°C
Power-off 1
Topr = 85°C
−
0.02 0.2
−
0.3
−
µA
−
0.8
1.6
µA
−
1.1
−
µA
While a WAIT
instruction is
executed
Peripheral clock off
Timer RE operation
in real-time clock
mode
µA
Vcc = 1.8 V to 2.7 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 2.2 V
VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open.The standard value does not include the current that flows through external division resistors.
The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
REJ03B0243-0030 Rev.0.30
Page 65 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
5.5
AC Characteristics
Table 5.24
Timing Requirements of Clock Synchronous Serial I/O with Chip Select
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C
(D version), unless otherwise specified.)
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
4
−
−
tCYC (1)
tSUCYC
tSUCYC
SSCK clock cycle time
tHI
SSCK clock “H” width
0.4
−
0.6
tLO
SSCK clock “L” width
0.4
−
0.6
tSUCYC
tRISE
SSCK clock rising
time
Master
−
−
1
tCYC (1)
Slave
−
−
1
µs
tFALL
SSCK clock falling
time
Master
−
−
1
tCYC (1)
−
−
1
µs
tSU
SSO, SSI data input setup time
100
−
−
ns
tH
SSO, SSI data input hold time
1
−
−
tCYC (1)
tLEAD
SCS setup time
Slave
1tCYC + 50
−
−
ns
tLAG
SCS hold time
Slave
1tCYC + 50
−
−
ns
tOD
SSO, SSI data output delay time
−
−
1
tCYC (1)
tSA
SSI slave access time
tOR
Slave
SSI slave out open time
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
Note:
1. 1tCYC = 1/f1(s)
REJ03B0243-0030 Rev.0.30
Page 66 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
REJ03B0243-0030 Rev.0.30
Page 67 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
REJ03B0243-0030 Rev.0.30
Page 68 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
tHI
VIH or VOH
SSCK
VIL or VOL
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.6
tH
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
REJ03B0243-0030 Rev.0.30
Page 69 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.25
Timing Requirements of I2C bus Interface (1)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version),
unless otherwise specified.)
Symbol
Parameter
Condition
Standard
Typ.
−
12tCYC + 600 (1)
−
3tCYC + 300 (1)
Min.
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
tSCLL
SCL input “L” width
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
SDA input bus-free time
5tCYC (1)
tSTAH
Start condition input hold time
3tCYC (1)
tSTAS
Retransmit start condition input setup time
tSTOP
Stop condition input setup time
tSDAS
Data input setup time
tSDAH
Data input hold time
Max.
−
ns
−
ns
−
300
−
ns
ns
−
1tCYC (1)
−
−
−
ns
3tCYC (1)
−
−
ns
3tCYC (1)
−
−
ns
1tCYC + 40 (1)
10
−
−
ns
−
−
ns
5tCYC + 500
−
−
−
(1)
VIH
SDA
VIL
tBUF
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
REJ03B0243-0030 Rev.0.30
Page 70 of 76
Jan 21, 2009
P(2)
tSDAS
tSDAH
ns
−
Note:
1. 1tCYC = 1/f1(s)
tSTAH
Unit
ns
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.26
Timing Requirements of XIN and XCIN
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version),
unless otherwise specified.)
Standard
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Parameter
VCC = 2.2V, Topr = 25°C
Min.
200
90
90
14
7
7
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
Max.
−
−
−
−
−
−
VCC = 3V, Topr = 25°C
Min.
50
24
24
14
7
7
Max.
−
−
−
−
−
−
VCC = 5V, Topr = 25°C
Min.
50
24
24
14
7
7
Max.
−
−
−
−
−
−
Unit
ns
ns
ns
µs
µs
µs
tC(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.8
Table 5.27
Input Timing of XIN and XCIN
Timing Requirements of TRAIO
(VCC = 1.8 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version),
unless otherwise specified.)
Standard
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Parameter
VCC = 2.2V, Topr = 25°C
Min.
500
200
200
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
Max.
−
−
−
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
Input Timing of TRAIO
REJ03B0243-0030 Rev.0.30
Page 71 of 76
Jan 21, 2009
VCC = 3V, Topr = 25°C
Min.
300
120
120
Max.
−
−
−
VCC = 5V, Topr = 25°C
Min.
100
40
40
Max.
−
−
−
Unit
ns
ns
ns
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Electrical Characteristics
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Table 5.28
Timing Requirements of Serial Interface
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version),
unless otherwise specified.)
Standard
Symbol
Parameter
VCC = 2.2V, Topr = 25°C
VCC = 3V, Topr = 25°C
VCC = 5V, Topr = 25°C
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
800
−
300
−
200
−
ns
tW(CKH)
CLKi input “H” width
400
−
150
−
100
−
ns
tW(CKL)
CLKi input “L” width
400
−
150
−
100
−
ns
td(C-Q)
TXDi output delay time
−
200
−
80
−
50
ns
th(C-Q)
TXDi hold time
0
−
0
−
0
−
ns
tsu(D-C)
RXDi input setup time
150
−
70
−
50
−
ns
th(C-D)
RXDi input hold time
90
−
90
−
90
−
ns
i = 0 to 2
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.10
Table 5.29
Input and Output Timing of Serial Interface
Timing Requirements of External Interrupt INTi (i = 0 to 7) and Key Input Interrupt KIi
(i = 0 to 7)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version),
unless otherwise specified.)
Standard
Symbol
Parameter
VCC = 2.2V, Topr = 25°C
VCC = 3V, Topr = 25°C
VCC = 5V, Topr = 25°C
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tW(INH)
INTi input “H” width, KIi input “H” width
1000 (1)
−
380 (1)
−
250 (1)
−
ns
tW(INL)
INTi input “L” width, KIi input “L” width
1000 (2)
−
380 (2)
−
250 (2)
−
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
INTi input
(i = 0 to 7)
tW(INL)
KIi input
(i = 0 to 7)
Figure 5.11
tW(INH)
Input Timing of External Interrupt INTi and Key Input Interrupt KIi
REJ03B0243-0030 Rev.0.30
Page 72 of 76
Jan 21, 2009
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
Package Dimensions
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology web site.
JEITA Package Code
P-LQFP52-10x10-0.65
RENESAS Code
PLQP0052JA-A
Previous Code
52P6A-A
MASS[Typ.]
0.3g
HD
*1
D
39
27
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
26
bp
c1
c
E
*2
HE
b1
Reference
Symbol
14
1
Terminal cross section
ZE
52
13
ZD
Index mark
A
A1
A2
c
F
e
y
L
*3
bp
x
Jan 21, 2009
Min
9.9
9.9
Nom
10.0
10.0
1.4
11.8 12.0
11.8 12.0
0.05
0.27
0.09
0°
L1
Detail F
REJ03B0243-0030 Rev.0.30
Page 73 of 76
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Dimension in Millimeters
e
x
y
ZD
ZE
L
L1
0.35
Max
10.1
10.1
12.2
12.2
1.7
0.1 0.15
0.32 0.37
0.30
0.145 0.20
0.125
8°
0.65
0.13
0.10
1.1
1.1
0.5 0.65
1.0
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
Package Dimensions
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
c
Reference
Symbol
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Terminal cross section
ZE
17
c1
*2
E
HE
b1
16
Index mark
ZD
c
A
*3
A1
y
e
A2
F
bp
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A
Dimension in Millimeters
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
MASS[Typ.]
0.7g
HD
*1
D
33
48
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
c
Reference
Symbol
*2
E
HE
c1
b1
ZE
Terminal cross section
64
17
c
Index mark
A2
16
ZD
A
1
A1
F
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
REJ03B0243-0030 Rev.0.30
Page 74 of 76
Detail F
*3
bp
x
Jan 21, 2009
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
1.0
1.0
0.3 0.5 0.7
1.0
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
Package Dimensions
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
40
61
bp
E
c
*2
HE
c1
b1
Reference
Symbol
Terminal cross section
ZE
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
80
21
1
20
ZD
Index mark
A1
*3
c
A
y
bp
e
A2
F
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-LQFP80-14x14-0.65
RENESAS Code
PLQP0080JA-A
Previous Code
FP-80W / FP-80WV
Dimension in Millimeters
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
MASS[Typ.]
0.6g
HD
*1
D
41
60
61
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
HE
b1
Terminal cross section
ZE
80
Reference
Symbol
c
c1
*2
E
bp
21
1
20
ZD
c
A
A1
F
A2
Index mark
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L
y
e
REJ03B0243-0030 Rev.0.30
Page 75 of 76
*3
L1
bp
Detail F
x
Jan 21, 2009
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.27 0.32 0.37
0.30
0.09 0.145 0.20
0.125
8°
0°
0.65
0.13
0.10
0.825
0.825
0.35 0.5 0.65
1.0
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
Package Dimensions
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
y
*3
e
bp
A1
c
A
A2
F
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JD-B
Previous Code
100P6F-A
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
MASS[Typ.]
1.8g
Under development
HD
*1
D
80
51
81
50
E
*2
HE
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference Dimension in Millimeters
Symbol
100
31
30
c
F
A2
Index mark
ZD
A1
A
1
L
*3
e
y
REJ03B0243-0030 Rev.0.30
Page 76 of 76
bp
Jan 21, 2009
x
Detail F
D
E
A2
HD
HE
A
A1
bp
c
e
x
y
ZD
ZE
L
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
0°
10°
0.65
0.13
0.10
0.575
0.825
0.4 0.6 0.8
REVISION HISTORY
REVISION HISTORY
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Datasheet
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Datasheet
Description
Rev.
Date
0.01
May 19, 2008
−
First Edition issued
0.02
Jul 10, 2008
3
Table 1.4
CPU Specification: Minimum instruction execution time revised
DTC Specification: Activation sources 33→38
4
Table 1.5
R8C/L35A, R8C/L35B Groups: Specification revised
5
Table 1.6
Operating Frequency/Supply Voltage: Specification revised
Page
6 to 13
Summary
Table 1.7 to Table 1.14
Current of May 2008→Current of Jul 2008
10 to 11 Table 1.11 and Table 1.12 (P)→(D)
23
Table 1.15
WKUP1→WKUP1(3)
0.10
Jul 30, 2008
32
Table 4.1
RSTFR: 0XXX00XXb→XXXX00XXb
POMCR0: 00h→XX0000XXb
33
Table 4.2
0072h Voltage monitor 1/Compare A1 interrupt Control Register
→Voltage monitor 1/Comparator A1 interrupt Control Register
0073h Voltage monitor 2/Compare A2 interrupt Control Register
→Voltage monitor 2/Comparator A2 interrupt Control Register
36
Table 4.5
TRECR1: XXX0X0XXb→XXXXX0XXb
38
Table 4.7
0194h
SS Transmit Data Register→SS Transmit Data Register L
0195h
SS Transmit Data Register SSTDR
→SS Transmit Data Register H SSTDRH
0196h
SS Receive Data Register→SS Receive Data Register L
IIC bus Shift Register ICDRS deleted
0197h
SS Receive Data Register SSRDR
→SS Receive Data Register H SSRDRH
39
Table 4.8
01E0h to 01E7h: FFh→00h
3
Table 1.4
Watchdog Timer: Specification 15 bits→14 bits
5
Table 1.6
Flash Memory: Function R8C/L36B Group→R8C/L36A Group
14 to 17 Figure 1.9 to Figure 1.12
Watchdog Timer 15 bits→14 bits
A-1
REVISION HISTORY
Rev.
Date
0.10
Jul 30, 2008
0.30
Jan 21, 2009
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Datasheet
Description
Page
Summary
18 to 22 Figure 1.13 to Figure 1.17
P4_6/SEG38/TRCIOC→P4_6/SEG38/TRCIOC/TRCIOB
P4_7/SEG39/TRCIOD→P4_7/SEG39/TRCIOD/TRCIOB
24
Table 1.16
Timer TRCIOD→TRCIOD/TRCIOB
TRCIOC→TRCIOC/TRCIOB
32
Table 4.1
0020h: After Reset XX0000XXb→X0000000b
Note 2 revised
1
1.1 revised
2
1.1.2 revised
Table 1.2 revised
3
Table 1.3 Note 2 added
Table 1.4 added
5
Table 1.6 revised
6
Table 1.7 revised
7 to 14
Table 1.8 to Table 1.15 revised
15
Figure 1.9 revised
16
Figure 1.10 revised
19
Figure 1.13 revised
20
Figure 1.14 revised
24
Table 1.16 Note 3 revised
25
Table 1.17 Note 3 added
33
Table 4.1
000Bh: After Reset XXXX00XXb→XXh
Note 2 revised
39
Table 4.7
018Fh added
41
Table 4.9
0202h: After Reset 00h→X0000000b
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A-2
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© 2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.2
Date: Jul. 08, 2009
RENESAS TECHNICAL UPDATE
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Renesas Technology Corp.
Product
Category
Title
Applicable
Products
MPU&MCU
Document
No.
TN-R8C-A002B/E
Specification Changes in the R8C/L35A Group,
R8C/L35B Group, R8C/L36A Group, R8C/L36B Group,
R8C/L38A Group, R8C/L38B Group, R8C/L3AA Group
R8C/L3AB Group Hardware Manual
Information
Category
Technical Notification
Reference
Document
Described below
R8C/L35A Group, R8C/L35B Group
R8C/L36A Group, R8C/L36B Group
R8C/L38A Group, R8C/L38B Group
R8C/L3AA Group and R8C/L3AB Group
Rev.
2.00
Lot No.
−−
(8) in section 1-1 and section 2-8 have been revised in Revision 2.00.
1. Overview
The below changes have been made to the specifications described in the datasheet and hardware manual of the R8C/L3AA
Group, R8C/L3AB Group, R8C/L38A Group, R8C/L38B Group, R8C/L36A Group, R8C/L36B Group, R8C/L35A Group and
R8C/L35B Group.
1-1. Changes
(1) Removed the high-speed on-chip oscillator
(2) Changed the flash memory suspend function specifications
(3) Changed the flash memory suspend electrical characteristics
(4) Changed the timer RG specifications
(5) Changed the LCD port specifications
(6) Removed the voltage monitor 0 reset/power-on reset
(7) Removed the voltage monitor 1 /comparator A1 and voltage monitor 2 / comparator A2 functions
(8) Note on reducing power current
1-2. Reference Documents
The information in this document applies to the R8C/L35A Group, R8C/L35B Group, R8C/L36A Group, R8C/L36B Group,
R8C/L35A Group, R8C/L38B Group, R8C/L3AA Group, R8C/L3AB Group Hardware Manual Rev.0.30 and Datasheet
Rev.0.30.
2. Description
2-1. Removed the High-Speed On-Chip Oscillator
The high-speed on-chip oscillator function has been removed.
Do NOT select the high-speed on-chip oscillator as the clock source for the CPU clock or peripheral functions.
Descriptions regarding the high-speed on-chip oscillator in the reference documents shown in 1-2, other than descriptions
shown in this technical update, are invalid.
(c) 2009. Renesas Technology Corp., All rights reserved.
Page 1 of 8
RENESAS TECHNICAL UPDATE TN-R8C-A002B/E
Date: Jul. 08, 2009
2-1-1. Register Settings Related to the Clock Generation Circuit
2-1-1-1. High-Speed On-Chip Oscillator Control Register 0 (FRA0)
(1) Do NOT set FRA00 bit to 1 (high-speed on-chip oscillator on) [refer to Figure 2-1]
(2) Do NOT set FRA01 bit to 1 (high-speed on-chip oscillator selected as fOCO clock source) [refer to Figure 2-1].
The fOCO is a clock source of timer RA.
(3) Do NOT set FRA03 bit to 1 (fOCO-F divided by 128 selected as a clock source of fOCO128) [refer to Figure 2-1].
fOCO128 is used as an input-capture signal of timers RC and RD.
2-1-1-2. System Clock Control Register 3 (CM3)
(1) Do NOT set bits CM37 to CM36 bits to 10b (high-speed on-chip oscillator selected as CPU clock when the MCU exits
wait mode or stop mode) [refer to Figure 2-2].
2-1-1-3. High-Speed On-Chip Oscillator Control Register i (FRAi) (i = 1 to 7)
(1) Do NOT set the register related to the high-speed on-chip oscillator division select (FRA2) or registers related to
frequency adjustment (FRA1 and FRA3 to FRA7).
2-1-2. Register Settings Related to Timer RA
2-1-2-1. High-Speed On-chip Oscillator Control Register 0 (FRA0)
(1) Do NOT set the FRA01 bit to 1 (high-speed on-chip oscillator selected for the fOCO clock) [refer to Figure 2-1]. The
high-speed on-chip oscillator clock cannot be selected as the timer RA count source.
2-1-3 Register Settings Related to Timer RC
2-1-3-1. Timer RC Control Register 1 (TRCCR1)
(1) Do NOT set bits TCK2 to TCK0 to 110b (fOCO40M selected as the timer RC count source) [refer to Figure 2-3].
(2) Do NOT set bits TCK2 to TCK0 to 111b (fOCO-F selected as the timer RC count source) [refer to Figure 2-3].
2-1-3-2. High-speed On-Chip Oscillator Control Register 0 (FRA0)
(1) Do NOT set the FRA03 bit to 1 (fOCO-F divided by 128 selected as the fOCO 128 clock) [refer to Figure 2-1]. For the
timer RC input-capture function, fOCO-F divided by 128 cannot be selected for the input-capture trigger input of the TRCGRA
register.
2-1-4. Register Settings Related to Timer RD
2-1-4-1. Timer RD Control Register 0, 1 (TRDCR0, TRDCR1)
(1) Do NOT set bits TCK2 to TCK0 to 110b (fOCO40M selected as the timer RD count source) [refer to Figure 2-4].
(2) Do NOT set bits TCK2 to TCK0 to 111b (fOCO-F selected as the timer RD count source) [refer to Figure 2-4].
2-1-4-2. High-speed On-Chip Oscillator Control Register 0 (FRA0)
(1) Do NOT set the FRA03 bit to 1 (fOCO-F divided by 128 cannot be selected for the input-capture trigger input of the
TRDGRA0 register [refer to Figure 2-1]. For the timer RD input-capture function, fOCO-F divided by 128 cannot be selected for
the input-capture trigger input of the TRDGRA register.
Page 2 of 8
RENESAS TECHNICAL UPDATE TN-R8C-A002B/E
Date: Jul. 08, 2009
2-1-5. Timer RG Control Register Settings
2-1-5-1. Timer RG Control Register (TRGCR)
(1) Do NOT set bits TCK2 to TCK0, the count source select bits in the timer RG control register (TRGCR), to 110b (fOCO40M
selected as a count source of timer RG) [refer to Figure 2-5].
2-1-6. Register Settings for the A/D Converter
2-1-6-1. A/D Mode Register (ADMOD)
(1) Do NOT set the CKS2 bit to 1 (fOCO-F selected as the A/D converter operating clock source) [refer to Figure 2-6].
Do NOT set.
Do NOT set.
Do NOT set.
Figure 2-1.High-Speed On-Chip Oscillator Control Register 0 (FRA0) Setting
Page 3 of 8
RENESAS TECHNICAL UPDATE TN-R8C-A002B/E
Date: Jul. 08, 2009
Do NOT set.
Figure 2-2. System Clock Control Register 3 (CM3) Setting
Page 4 of 8
RENESAS TECHNICAL UPDATE TN-R8C-A002B/E
Date: Jul. 08, 2009
Do NOT set.
Figure 2-3. Timer RC Control Register 1 (TRCCR1) Setting
Do NOT set.
Figure 2-4. Timer RD Control Register 0,1 (TRDCR0, TRDCR1) Setting
Page 5 of 8
RENESAS TECHNICAL UPDATE TN-R8C-A002B/E
Date: Jul. 08, 2009
Do NOT set. See 2-4.
Do NOT set. See 2-1-5-1.
Figure 2-5. Timer RG Control Register (TRGCR) Setting
Do NOT set.
Figure 2-6. A/D Mode Register (ADMOD) Setting
Page 6 of 8
RENESAS TECHNICAL UPDATE TN-R8C-A002B/E
Date: Jul. 08, 2009
2-2. Changes in the Flash Memory Suspend Function
Flash programming operation is disabled when the auto-erasure is suspended while using the flash memory suspend
function.
Program is also not available with Data Flash driver in condition indicated in
.
Figure 2-7. Flash Memory Suspend Function
2-3. Changes in the Flash Memory Suspend Function Electrical Characteristics
Wait for at least 33 ms after the erase start/restart request before the making the next erase/suspend request. This is
described as the “Interval from erase start/restart until suspend” in the hardware manual [refer to Figure 2-7].
33
ms
33
ms
Figure 2-8. Flash Memory Suspend Electrical Characteristics
Page 7 of 8
RENESAS TECHNICAL UPDATE TN-R8C-A002B/E
Date: Jul. 08, 2009
2-4. Change in the Timer RG Function
Do NOT set the count source select bits (TCK2 to TCK0) in the timer RG control register (TRGCR) to 001b (f2 selected as
the count source of timer RG) [refer to Figure 2-5].
2-5. Changes in the LCD Port Function
2-5-1. LCD Port Select Register 0 (LSE0)
This information applies to the R8C/L35A Group, R8C/L36A Group, R8C/L35B Group, and R8C/L36B Group.
Do NOT set bits LSE06 and LSE07 to 1 (SEG6 and SEG7 port functions selected). P0_6/SEG6 and P0_7/SEG7 cannot be
used as segment pins SEG6 and SEG7. P0_6/SEG6 and P0_7/SEG7 can be used as I/O ports P0_6 and P0_7.
2-5-2. LCD Port Select Register 2 (LSE2)
This information applies to the R8C/L38A Group and R8C/L38B Group.
Do NOT set the LSE16 bit to 1 (SEG16 port function selected). P2_0/SEG16/KI0 cannot be used as segment pin SEG16.
P2_0/SEG16/KI0 can be used as I/O port P0_2 and KI0.
2-6. Voltage Monitor 0 Reset and Power-On Reset
The voltage monitor 0 reset and power-on reset cannot be used. Use a hardware reset to reset the MCU. In the documents
listed in section 1-2, descriptions of the voltage monitor 0 reset and power-on reset are invalid.
2-7. Removed the Voltage Monitor 1 / Comparator A1 Interrupt and Voltage Monitor 2 / Comparator A2 Interrupt Functions
Voltage monitor 1 / comparator A1 and voltage monitor 2 / comparator A2 cannot be used. In the documents listed in section
1-2, description of the voltage monitor 0 reset or power-on reset are invalid.
2-8. Note on Reducing Power Current
Write 00h to the POMCR0 register (address 0020h) by a program. Current consumption may increase until 00h is written to
the POMCR0 register.
Sample code: MOV.B #00H, 0020H
3. Other Note
Note regarding pins P12_1 and P12_0.
P12_1 and P12_0 are shared with XIN and XOUT. When XIN is used as a clock, these ports cannot be used as I/O ports.
4. Slated Changes
Contact the Renesas Technology sales department for schedule and products with high-speed on-chip oscillator.
- End of description -
Page 8 of 8