Untitled

Gold IPTM Program
UMC’s advanced deep sub-micron process technologies
offer tremendous opportunities to IC designers looking to
profit from market-leading products. However, unprecedented design complexity, increasingly competitive markets and dramatically shortened life cycles often mitigate
these opportunities. Solutions to these challenges have
become critical.
UMC’s goal is to provide its customers with a vast offering
of compatible library and IP elements that can be easily
incorporated into an SOC in a “plug and play” fashion. In
order to achieve interoperability among IPs, UMC has encouraged all of its partners to follow a set of IP creation
standards:
1.
The Gold IP program continues to lead the foundry industry in the hardening of standard library elements, mixed
signal and analog cores, and timing-critical cores through
its Silicon Shuttle R multi-chip test wafer program. The
results are coded in the Gold IP catalog according to the
core’s maturity in UMC silicon (Bronze=Softcore or GDSII, Silver=Hardcore available and silicon verified,
Gold=Production). As the catalog evolves, the Gold IP program continues to emphasize the “Interoperability” of IP
cores, leveraging alliances with IP platform developers, design service providers, and EDA companies, as well as
industry associations such as the Virtual Socket Interface Alliance (VSIA). The Gold IP Program continues to
bring faster time-to-market and design risk mitigation to
its customers.
2.
Standardization of process: All IP cores are developed
in the UMC standard mainstream process for each
technology node.
Standardization for standard cell and I/O architecture:
UMC has adopted Virtual Silicon’s 0.15um and 0.13um
and Faraday’s 0.13um architectures under UMC’s open
architecture initiative for standard cell and I/O. Open
architecture will also be offered to customers for our
90nm process from UMC.
As a member of the IP Protection Development Working
Group (DWG) at VSIA, UMC has driven the industry standard of IP tracking and identification tagging tools [VSIA
standard version 1.0 (IPP 1 1.0)].
Table of Contents
Free-of-Charge Libraries
Non-Free Libraries
IP Catalog
PLL
ADC
DAC
ANALOG/MIXED-MODE
BUS INTERFACE
MICROCONTROLLER AND MICROPROCESSOR
MICROPROCESSOR PERIPHERAL
DSP
COMMUNICATIONS
CONSUMER
STORAGE
INTEGRATED PLATFORM
DESIGN-FOR-TEST
EMBEDDED NON-VOLATILE MACRO
EMBEDDED SRAM MACRO
EMBEDDED ARRAY
MEMORY SUB-SYSTEM
Silicon Shuttle Program
IP Vendor Contact
Page 2
Page 12
Page 23
Page 23
Page 25
Page 25
Page 26
Page 28
Page 31
Page 32
Page 33
Page 33
Page 35
Page 35
Page 36
Page 36
Page 37
Page 37
Page 38
Page 38
Page 39
Page 40
1
Free-of-Charge Libraries
UMC has revolutionized the foundry industry by offering
our customers comprehensive free-of-charge libraries for
designs implemented with UMC’s advanced process technologies, ranging from 0.25um to the leading edge 0.13um
technology. UMC has partnered with leading full service
library providers, Artisan Components, Faraday Technology, and Virtual Silicon Technology, to provide silicon verified standard cells, I/Os, memory compilers, and PLL compilers.
Artisan, Faraday, and Virtual Silicon provide free basic support for UMC customers for their free-of-charge library products. Additional services can be provided by these vendors under a separate service agreement. These services
include creating additional EDA views, re-characterization
over an extended voltage and temperature range, custom
developments for standard cells, I/Os, and memories.
To download the Artisan libraries:
http://www.artisan.com/programs/freelibrary/umc.html
To download the VST libraries:
http://www.virtual-silicon.com/part/libr/lb_umc_ov.html
To download the Faraday libraries:
http://www.faraday.com.tw/component/lib/umc_lib.html
Virtual Silicon 0.13um Library - High Speed (Low-K) Process
Standard Cell
552 high density standard cells
9-track cell architecture, performance optimized for
300~800 MHZ
Average cell density of 200K gates/sq.mm
Multiple drive strengths
Layout using metal 1 only
Scan version of every flip-flop available
Fully contacted well ties
Accurate modeling and characterization for timing
and power
Open architecture developers kit available
Inline and Staggered I/O
400+ 3.3V I/O pads
Pad pitch: 70um (in-line), 35um (staggered)
Multiple current drives up to 16mA
Input buffer types - Pull-up/pull-down resistor, pad
keeper, normal/Schmitt
Output and bi-directional buffer types with slew rate
control
Silicon proven ESD and latch-up structures
Analog power pads, crystal pads
Open architecture developers kit available
PLL Compiler
Programmable input, output frequencies and
duty cycle
Input frequency range: 20 MHz - 200 MHz
Output frequency range: 50MHz - 1GHz
PLL module entirely located in the I/O pad rings
Dedicated analog power supply pins
Build-in ESD and latch-up protection structures
Single Port SRAM, Dual Port SRAM, Two Port
Register File, and Diffusion ROM Compilers
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Routable over the core with higher metal layer
Ability to compile to multiple aspect ratio
Scan and BIST support
Size
Architecture
Word
Bit
Single Port
Sync. SRAM
64 - 256K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 1.19
Worst: 1.88
Dual Port
Sync. SRAM
64 - 64K
(Increment: 2X mux)
2 - 64
(Increment: 1)
4, 8, 16, 32
128 bit - 256 Kbit
4K x 16
Typical: 1.30
Worst: 2.20
Two Port Sync.
Register File
32 - 2K
(Increment: 2X mux)
2 - 144
(Increment: 1)
2, 4, 8
64 bit - 72 Kbit
128 x 144
Typical: 1.08
Worst: 1.72
Diffusion ROM
64 - 256K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 1.32
Worst: 2.10
Mux
2
Access Time (ns)
Free-of-Charge Libraries
Virtual Silicon 0.13um Library - Standard Performance (FSG) Process
Standard Cell
510+ high density standard cells
9-track cell architecture, performance optimized for
300~800 MHZ
Average cell density of 200K gates/sq.mm
Multiple drive strengths
Layout using metal 1 only
Scan version of every flip-flop available
Fully contacted well ties
Accurate modeling and characterization for timing
and power
Open architecture developers kit available
Inline and Staggered I/O
400+ 3.3V I/O pads
Pad pitch: 70um (in-line), 35um (staggered)
Multiple current drives up to 16mA
Input buffer types - Pull-up/pull-down resistor, pad
keeper, normal/Schmitt
Output and bi-directional buffer types with slew rate
control
Silicon proven ESD and latch-up structures
Analog power pads, crystal pads
Open architecture developers kit available
PLL Compiler
Programmable input, output frequencies and duty
cycle
Input frequency range: 20 MHz - 200 MHz
Output frequency range: 50MHz - 1GHz
PLL module entirely located in the I/O pad rings
Dedicated analog power supply pins
Build-in ESD and latch-up protection structures
Single Port SRAM, Dual Port SRAM, Two Port
Register File, and Diffusion ROM Compilers
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Routable over the core with higher metal layer
Ability to compile to multiple aspect ratio
Scan and BIST support
Mux
Size
Architecture
Word
Bit
Single Port
Sync. SRAM
64 - 256K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 1.19
Worst: 1.88
Dual Port
Sync. SRAM
64 - 64K
(Increment: 2X mux)
2 - 64
(Increment: 1)
4, 8, 16, 32
128 bit - 256 Kbit
4K x 16
Typical: 1.30
Worst: 2.20
Two Port Sync.
Register File
32 - 2K
(Increment: 2X mux)
2 - 144
(Increment: 1)
2, 4, 8
64 bit - 72 Kbit
128 x 144
Typical: 1.08
Worst: 1.72
Diffusion ROM
64 - 256K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 1.32
Worst: 2.10
3
Access Time (ns)
Free-of-Charge Libraries
Faraday 0.13um Library - High Speed (Low-K) Process
Standard Cell and I/O
Power supply (internal logic and I/O): 1.2V.
Second power supply (I/O): 3.3V.
12-track cell architecture; Cell high =4.8um.
X grid = 0.4um, Y grid = 0.4um.
Very High speed: gate delay = 17.0ps/stage @ 1.2V,
F.O. = 1.
Power Consumption: 0.012µW/Gate/MHz @ 1.2V, 2Input NAND, F.O. = 2.
Gate density: 160K Gates/mm2 @Utilization = 100%.
Fat/Slim profile I/O optimized for Core/Pad limited
design.
Programmable input characteristics for pull up/down/
keeper and Schmitt trigger.
Programmable output driving current 2-8mA by steps
of 2mA, 4-16mA by steps of 4mA.
Programmable output slew rate control.
Programmable X’tal oscillator pads.
Mixed 1.2V/3.3V interface.
Wide selection of I/O buffers: 3.3V, 3.3V with 5V
tolerant.
Single Port SRAM, Dual Port SRAM, Two Port
Register File, and Via2 ROM Memory Instances
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Provides both high speed and low power SRAMs
Ability to compile to multiple aspect ratio
Scan and BIST support
Power port connection support
Zero hold time for inputs
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
128 - 128K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8, 16
128 bit - 1 Mbit
4K x 16
Typical: 1.25
Worst: 2
Single Port 2Mb
Sync. SRAM
4096 - 256K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8, 16
4 K bit - 2 Mbit
64K x 16
Typical: 3
Worst: 4.8
Dual Port
Sync. SRAM
64 - 32K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8
64 bit - 512 Kbit
4K x 16
Typical: 1.42
Worst: 2.27
Two Port Sync.
Register File
16 - 4K
(Increment: 1X mux)
1 - 144
(Increment: 1)
2, 4, 8, 16
16 bit - 72 Kbit
128 x 144
Typical: 1.44
Worst: 2.3
2 - 128
(Increment: 1)
1, 2, 4, 8
256 bit - 2 Mbit
4K x 16
Typical: 1.67
Worst: 2.67
Via2 ROM
128 - 128K
(Increment: 2X mux)
4
Free-of-Charge Libraries
Faraday 0.13um Library - Low Leakage (FSG) Process
Standard Cell and I/O:
Power supply (internal logic and I/O): 1.2V
Second power supply (I/O): 3.3V
8-track cell architecture; Cell high = 3.2um.
X grid = 0.4um, Y grid = 0.4um.
Gate delay = 33ps/stage @ 1.2V, F.O. = 1
Low power: 0.006µW/Gate/MHz @ 1.2V, 2-Input
NAND, F.O. = 2
Ultra high density: 250K Gates/mm2 @Utilization =
100% (i.e. 1million transistors / mm2)
Fat/Slim profile I/O optimized for Core/Pad limited
design
Programmable input characteristics for pull up/down/
keeper and Schmitt trigger
Programmable output driving current 2-8mA by steps
of 2mA, 4-16mA by steps of 4mA.
Programmable output slew rate control
Programmable X’tal oscillator pads
Mixed 1.2V/3.3V interface
Wide selection of I/O buffers: 3.3V, 3.3V with 5V
tolerant.
Single Port SRAM, Dual Port SRAM, Two Port
Register File, and Via2 ROM Memory Instances
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Provides both high speed and low power SRAMs
Ability to compile to multiple aspect ratio
Scan and BIST support
Power port connection support
Zero hold time for inputs
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
128 - 128K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8, 16
128 bit - 1 Mbit
4K x 16
Typical: 1.8
Worst: 2.98
Single Port 2Mb
Sync. SRAM
4096 - 256K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8, 16
4 K bit - 2 Mbit
64K x 16
Typical: 4.5
Worst: 7.2
Dual Port
Sync. SRAM
64 - 32K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8
64 bit - 512 Kbit
4K x 16
Typical: 2.1
Worst: 3.4
Two Port Sync.
Register File
16 - 4K
(Increment: 1X mux)
1 - 144
(Increment: 1)
2, 4, 8, 16
16 bit - 72 Kbit
128 x 144
Typical: 1.98
Worst: 3.2
2 - 128
(Increment: 1)
1, 2, 4, 8
256 bit - 2 Mbit
4K x 16
Typical: 2.5
Worst: 4.0
Via2 ROM
128 - 128K
(Increment: 2X mux)
5
Free-of-Charge Libraries
Faraday 0.13um Library - High Speed (FSG) Process
Standard Cell and I/O:
Power supply (internal logic and I/O): 1.2V
Second power supply (I/O): 3.3V
8-track cell architecture; Cell high = 3.2um.
X grid = 0.4um, Y grid = 0.4um.
Gate delay = 17ps/stage @ 1.2V, F.O. = 1
Low power: 0.006µW/Gate/MHz @ 1.2V, 2-Input
NAND, F.O. = 2
Ultra high density: 250K Gates/mm2 @Utilization =
100% (i.e. 1million transistors / mm2)
Fat/Slim profile I/O optimized for Core/Pad limited
design
Programmable input characteristics for pull up/down/
keeper and Schmitt trigger
Programmable output driving current 2-8mA by steps of
2mA, 4-16mA by steps of 4mA.
Programmable output slew rate control
Programmable X’tal oscillator pads
Mixed 1.2V/3.3V interface
Wide selection of I/O buffers: 3.3V, 3.3V with 5V
tolerant.
Single Port SRAM, Dual Port SRAM, Two Port
Register File, and Via2 ROM Instances
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Provides both high speed and low power SRAMs
Ability to compile to multiple aspect ratio
Scan and BIST support
Power port connection support
Zero hold time for inputs
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
128 - 128K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8, 16
128 bit - 1 Mbit
4K x 16
Typical: 1.25
Worst: 2
Single Port 2Mb
Sync. SRAM
4096 - 256K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8, 16
4 Kbit - 2 Mbit
64K x 16
Typical: 3
Worst: 4.8
Dual Port
Sync. SRAM
64 - 32K
(Increment: 2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8
64 bit - 512 Kbit
4K x 16
Typical: 1.42
Worst: 2.2
Two Port Sync.
Register File
16 - 4K
(Increment: 1X mux)
1 - 144
(Increment: 1)
2, 4, 8, 16
16 bit - 72 Kbit
128 x 144
Typical: 1.44
Worst: 2.3
2 - 128
(Increment: 1)
1, 2, 4, 8
256 bit - 2 Mbit
4K x 16
Typical: 1.67
Worst: 2.67
Via2 ROM
128 - 128K
(Increment: 2X mux)
6
Free-of-Charge Libraries
Virtual Silicon 0.15um Library
Standard Cell
500+ high density standard cells
8-track cell architecture, performance optimized for
300~800 MHZ
Average cell density of 150K gates/sq.mm
Multiple drive strengths
Layout using metal 1 only
Scan version of every flip-flop available
Fully contacted well ties
Accurate modeling and characterization for timing
and power
Open architecture developers kit available
PLL Compiler
Programmable input, output frequencies and duty
cycle
Input frequency range: 20 MHz - 200 MHz
Output frequency range: 50MHz - 1GHz
PLL module entirely located in the I/O pad rings
Dedicated analog power supply pins
Build-in ESD and latch-up protection structures
Clock Synthesizer
Excellent stability and noise-immunity and low jitter
Entire module located in the I/O and rings
Reference frequency range: 12.5 MHz-50MHz
Output frequency range:25MHz-400MHz
Inline and Staggered I/O
700+ 3.3V &3.3V/5VT I/O pads
Pad pitch: 60um (in-line), 40um (staggered)
Multiple current drives up to 24mA
Input buffer types - Pull-up/pull-down resistor, pad
keeper, normal/Schmitt
Output and bi-directional buffer types with slew rate
control
Silicon proven ESD and latch-up structures
Analog power pads, crystal pads
Open architecture developers kit available
Single Port SRAM, Single Port Borderless SRAM,
Dual Port SRAM, Two Port Register File, and
Diffusion ROM Compilers
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Routable over the core with higher metal layer
Ability to compile to multiple aspect ratio
Scan and BIST support
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
64 - 256K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 1.20
Worst: 2.08
Borderless Bitcell
Single Port
Sync. SRAM
64 - 256K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 1.10
Worst: 1.88
Dual Port
Sync. SRAM
64 - 64K
(Increment: 2X mux)
2 - 64
(Increment: 1)
4, 8, 16, 32
128 bit - 256 Kbit
4K x 16
Typical: 1.40
Worst: 2.41
Two Port Sync.
Register File
32 - 2K
(Increment: 2X mux)
2 - 144
(Increment: 1)
2, 4, 8
64 bit - 72 Kbit
128 x 144
Typical: 1.20
Worst: 1.95
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 1.76
Worst: 2.96
Diffusion ROM
64 - 256K
(Increment: 2X mux)
7
Free-of-Charge Libraries
Artisan 0.18um Library
Standard Cell
478 high-density standard cells
9-track cell architecture
Average cell density of 111K gates/sq.mm
Multiple drive strengths
Routable in 3, 4, 5 or more metal layers
Comprehensive design tool support
Process specific electrical and physical tuning
Single Port and Dual Port SRAM Compilers
Exceptional speed
Broadly configurable
Low active power and leakage-only standby current
Complete set of tool models and characterization data
Flexible power routing
Zero hold time (data, address and control inputs)
Inline I/O
600+ 3.3V/5VT
Pad pitch: 60 um
Input: pull-up/pull-down, Schmitt trigger, LVTTL, CMOS
Output: multiple current up tp 24mA with 3 slew rate
options
Special pads: clock, crystal oscillator, corner, power
and ground
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
16 - 8K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16
32 bit - 512 Kbit
4K x 16
Typical: 1.21
Worst: 2.13
Dual Port
Sync. SRAM
16 - 8K
(Increment: 2X mux)
2 - 128
(Increment: 1)
32 bit - 512 Kbit
4K x 16
Typical: 1.28
Worst: 2.26
4, 8, 16
8
Free-of-Charge Libraries
Virtual Silicon 0.18um Library
Standard Cell
500+ high performance standard cells
11-track cell architecture, performance optimized for
200~700 MHz
Average cell density of 90K gates/sq.mm
Multiple drive strengths
Layout using metal 1 only
Scan version of every flip-flop available
Fully contacted well ties
Accurate modeling and characterization for timing and
power
Open architecture developers kit available
PLL Compilers
Programmable input, output frequencies and duty
cycle
Input frequency range: 20 MHz - 200 MHz
Output frequency range: 50MHz -900MHz
PLL module entirely located in the I/O pad rings
Dedicated analog power supply pins
Build-in ESD and latch-up protection structures
Single Port Synchronons SRAM and Two Port
Register File Compilers
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Routable over the core with higher metal layer
Ability to compile to multiple aspect ratio
Scan and BIST support
Inline and Staggered I/O
700+ 3.3V & 3.3V/5VT I/O pads
Pad pitch: 60um (In-line), 40um (Staggered)
Multiple current drives up to 24mA
Input: Pull-up/pull-down resistor, pad keeper, normal/
Schmitt
Output and bi-directional with slew rate control
Silicon proven ESD and latch-up structures
Analog power pads, crystal pads
Open architecture developers kit available
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
32 - 4K
(Increment: 2X mux)
2 - 128
(Increment: 1)
2, 4, 8, 16
32 bit - 256 Kbit
4K x 16
Typical: 1.80
Worst: 3.36
Two Port
Register File
8 - 1K
(Increment: 2X mux)
4 - 128
(Increment: 1)
1, 2, 4
32 bit - 64 Kbit
128K x 64
Typical: 1.37
Worst: 2.38
9
Free-of-Charge Libraries
Artisan 0.25um Library
Standard Cell
437+ high density standard cells
8-track cell architecture
Average cell density of 64K gates/sq.mm
Multiple drive strengths
Routable in 3, 4, or 5 metal layers
Comprehensive design tool support
Process specific electrical and physical tuning
Inline I/O
600+ 2.5V/3.3VT
Pad pitch: 72um
Multiple current drives up to 24mA
3 slew rate options
Input characteristics: pull-up/pull-down, Schmitt
trigger, LVTTL CMOS
Output characteristics: N-channel and P-channel open
drain
Special pads: clock, crystal oscillator, corner, power
and ground
Fully verified tool models
Single Port SRAM and Dual Port Memory Compilers
Exceptional speed
Broadly configurable
Low active power and leakage-only standby current
Complete set of tool models and characterization data
Flexible power routing
Zero hold time (data, address and control inputs)
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
16 - 8K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16
32 bit - 512 Kbit
4K x 16
Typical: 1.55
Worst: 2.43
Dual Port
Sync. SRAM
16 - 8K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16
32 bit - 512 Kbit
4K x 16
Typical: 1.68
Worst: 2.83
10
Free-of-Charge Libraries
Virtual Silicon 0.25um Library
Standard Cells
500+ high performance standard cells
11-track cell architecture, performance optimized for
150~400 MHz
Average cell density of 45K gates/sq.mm
Multiple drive strengths
Hand-crafted layout
Scan version of every flip-flop available
Fully contacted well ties
Accurate modeling and characterization for timing and
power
Inline I/O
70+ 3.3V I/O pads
Pad pitch: 60um
Multiple current drives up to 24mA
Input buffer types - Pull-up/pull-down resistor, pad
keeper, clock driver and normal/Schmitt
Output and bi-directional buffer types with slew rate
control
Silicon proven ESD and latch-up structures
Two Port Register File
Synchronous reads/writes
Static design with zero standby current
Automated EDA views
Routable over the core with higher metal layer
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Two Port
Register
8 - 256
(Increment: 2X mux)
(Increment: 2)
NA
32 bit - 18 Kbit
128 x 64
Typical: 1.37
Worst: 2.48
GlobalCAD 0.35um library
GlobalCAD 0.5um library
Standard cell and I/O
450+ cells
Silicon proven
Accurate timing characterization
Support most of the EDA tools
Optimized for Cadence and Avanti place & route tools
High routing density, routability, high speed and low
power
Routable for 3,4,5 metals
3.3V, 5V I/O
Drive strength 4,8,12,16, and 24 mA
Latchup performance: 500 mA
ESD protection: 2.5kV HBM
Low current leakage
Standard cell and I/O
300+ cells
Silicon proven
Accurate timing characterization
Support most of the EDA tools
Optimized for Cadence and Avanti place & route tools
High routing density, routability, high speed and low
power
Routable for 2,3,4 metals
5V I/O
Drive strength 4,8,12,16, and 24 mA
Latchup performance: 500 mA
ESD protection: 2.5kV HBM
Low current leakage
11
Non-Free Libraries
In addition to the UMC free-of-charge libraries, several vendors have developed UMC library elements that are available to our foundry customers on a fee basis. The following section lists those vendors and offerings:
Virage 0.13um Memory Compiler
UMC
Process
Type
Word
Width
(bits/word)
Word
Width
(word)
Max
Size
(K bits)
Max
Configuration
Aspect
Ratio
(Yes/No)
Tcyc for
2Kx16,4Kx16
Block (Worst
Cond);
32x32 for
Reg. File
Ta for
2Kx16,4Kx16
Block (Worst
Cond);
32x32 for
Reg. File
Bit/Byte
write
capability
Redundancy
Built-In
SP HD
ASAP
HS/SP/LL
2 - 128
16 - 16K
32 - 512K
16Kx32
Yes: 4, 8, 16
2.19, 2.72
2.17, 2.69
Yes
No
DP HD
ASAP
HS/SP/LL
2 - 128
16 - 8K
32 - 512K
8Kx64
Yes: 4, 8, 16
2.37, 3.04
2.35, 3.01
Yes
No
1P
HS/SP
Register
file
2 - 128
8 - 512
16 - 16K
512x32
Yes: 1, 2, 4
2.39
1.55
Yes
No
2P
HS/SP/LL
Register
file
2 - 256
8 - 1024
16 - 64K
1Kx64
Yes: 1, 2, 4
1.370
1.04
Yes
No
ROM
HS/SP/LL
8 - 64
256 - 64K
2K - 1M
64Kx16
Yes: 16, 32, 64
3.41, 4.7
2.29, 3.03
No
No
SP HS
ASAP
HS/SP
2 - 256
16 - 16K
32 - 512K
16Kx32
Yes: 4, 8, 16
1.39, 1.55
1.33, 1.53
Yes
No
DP HS
ASAP
HS/SP
2 - 256
32 - 8K
64 - 512K
8Kx64
Yes: 4, 8, 16
1.49, 1.74
1.34, 1.61
Yes
No
SP
STAR
HD-4M
HS/SP/LL
8 - 256
128 - 64K
16K - 4M
64Kx64
Yes: 8, 16, 32
2.67, 2.98
2.65, 2.96
Yes
Yes
HS/SP
SP
STAR
HS-512K
2 - 256
16 - 16K
32 - 512K
16Kx32
Yes: 4, 8, 16
1.47, 1.68
1.45, 1.66
Yes
Yes
HS/SP
DP
STAR
HS-512K
2 - 256
32 - 8K
64 - 512K
8Kx64
Yes: 4, 8, 16
1.49, 1.74
1.42, 1.69
Yes
Yes
B-CAM
144K
HS/SP
4 - 144
16 - 1K
64 - 144K
1Kx144
Yes: 2
5.39, 5.43
5.03, 5.09
Yes
No
T-CAM
144K
HS/SP
4 - 144
16 - 1K
64 - 144K
1Kx144
Yes: 2
7.0, 7.21
6.46, 6.62
Yes
No
12
Non-Free Libraries
Virtual Silicon 0.13um Library - Low Leakage Process
Standard Cell
522 high density standard cells
9-track cell architecture
Average cell density of 200K gates/sq.mm
Multiple drive strengths
Layout using metal 1 only
Scan version of every flip-flop available
Fully contacted well ties
Accurate modeling and characterization for timing and
power
Open architecture developers kit available
Inline and Staggered I/O
400+ 3.3V I/O pads
Pad pitch: 70um (in-line), 35um (staggered)
Multiple current drives up to 16mA
Input buffer types - Pull-up/pull-down resistor, pad
keeper, normal/Schmitt
Output and bi-directional buffer types with slew rate
control
Silicon proven ESD and latch-up structures
Analog power pads, crystal pads
Open architecture developers kit available
PLL Compiler
Programmable input, output frequencies and duty
cycle
Input frequency range: 24 MHz - 200 MHz
Output frequency range: 50MHz - 1GHz
PLL module entirely located in the I/O pad rings
Dedicated analog power supply pins
Build-in ESD and latch-up protection structures
Single Port SRAM, Dual Port SRAM, Two Port
Register File, and Diffusion ROM Compilers
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Routable over the core with higher metal layer
Ability to compile to multiple aspect ratio
Scan and BIST support
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
64 - 256K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 2.40
Worst: 3.75
64 - 64K
(Increment: 2X mux)
2 - 64
(Increment: 1)
4, 8, 16, 32
128 bit - 256 Kbit
4K x 16
Typical: 2.58
Worst: 4.40
32 - 2K
(Increment: 2X mux)
2 - 144
(Increment: 1)
2, 4, 8
64 bit - 72 Kbit
128 x 144
Typical: 2.21
Worst: 3.45
64 - 256K
(Increment: 2X mux)
2 - 128
(Increment: 1)
4, 8, 16, 32
128 bit - 1 Mbit
4K x 16
Typical: 2.65
Worst: 4.21
Sync. SRAM
Dual Port
Sync. SRAM
Two Port
Sync. Register File
Diffusion ROM
13
Non-Free Libraries
Dolphin 0.13um Library
Standard Cells
Full custom standard cell library consisting of about
500 cells
Single metal layer design for high routing utilization
10-track layout
High speed and high density
Accurate timing and power models
Complete models and views for synthesis and
functional simulation tools
Memory Compilers with and without Redundancy
Single port SRAM, Dual port SRAM, 2-Port Register
File and 4-Port Register File compilers using RAMpilerTM
development system and user interface
RAMpiler +TM with row and column redundancy of up
to 2 rows & 2 columns/IOs
- Synchronous reads/writes
- Static design with zero standby current
- Ability to compile to multiple aspect ratios
- Up to 1.1Mbit single instance
- Up to 288 bit word
- Up to 16K words deep
- Fully routable over the memory with higher metal
layers
- Small set-up and zero hold times
- Power ring size based on frequency of operation
and load
- Multiple pin placement and layer options
- Multiple power ring metal layer and configuration
options
- Register output options
- Multiple output drive strengths
- Different power ring design configurations
- Bit Write Mask or Word (global write) options
- Write through, transparent write
- BIST Mux option on the inputs
- Row redundancy
- Column/IO redundancy
2-Port (1R/1W) register file compiler
4-Port (2R/2W) register file compiler
Standard I/Os
Staggered pad design with 30µm pitch
Core/Area I/O pads for flip chip (C4) 200µm & 225µm
LVCMOS, LVTTL & Schmitt Trigger input
I/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with
3.3V output
I/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with
3.3V output /5.0V tolerance
I/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with
2.5V output
I/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with
2.5V output /3.3V tolerance
Pull-up, pull-down, sustain level options
4 different slew rate keeper options, JTAG inputs for
testability, Schmitt trigger inputs
Level shifts from 1.2V core up to 3.3V I/O supply and
from 3.3V to 1.2V
Specialty Memories
Binary BCAM memories and CAM compilers using
CAMpilerTM technology
Ternary TCAM memories and CAM compilers using
CAMpilerTM technology
Custom single instance large density SRAMS with
redundancy up to 24 Mbits
Custom Register Files with different configurations
such as: 1W/4R, 3W/3R, 1W/8R, 2W/4R, 3W/5R,
etc.
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port (1R/W)
4 - 16K
(Increment: 4X mux)
2 - 288
(Increment: 1)
4, 8, 16
8 bit - 1296 Kbit
4K x 16
Typical: 1.23
Worst: 2.09
4 - 8K
(Increment: 4X mux)
2 - 288
(Increment: 1)
4, 8, 16
8 bit - 288 Kbit
64K x 16
Typical: 1.29
Worst: 2.21
1 - 8K
(Increment: 2X mux)
2 - 144
(Increment: 1)
1, 2, 4, 8,16
2 bit - 288 Kbit
128 x 144
Typical: 1.59
Worst: 2.29
1 - 8K
(Increment: 1X mux)
2 - 144
(Increment: 1)
1, 2, 4, 8, 16
2 bit - 288 Kbit
128 x 44
Typical: NA
Worst: NA
Sync. SRAM
Dual Port (2R/W)
Sync. SRAM
Two Port Sync.
Register File (1R/1W)
4-Port Register File
14
Non-Free Libraries
Nurlogic 0.13um Library
Standard Cells
1000+ high performance standard cells
9-track cell architecture high speed
Average cell density of 156K gates/sq.mm
8-track cell architecture high density
Average cell density of 192K gates/sq.mm
Multiple drive strengths
Silicon proven
Scan version of every flip-flop available
Compatible with mixed signal environment
Accurate timing and power models
In-line and staggered I/O
3.3V
Pad pitch: 70um (In-line), 35um (Staggered)
Multiple current drives up to 16mA
Pull ups, Pull downs, switchable
Hysteresis
Built-in level shifting
GlobalCAD 0.15um library
Standard cell andI/O
450+ cells
Silicon proven
Accurate timing characterization
Support most of the EDA tools
Optimized for Cadence and Avanti place & route tools
High routing density, routability, high speed and low
power
Routable for 3,4,5 metals
1.2/1.5V, 3.3V I/O
Drive strength 4,8,12,16, and 24 mA
Latchup performance: 200 mA
ESD protection: 2.0kV HBM
Low current leakage
Silicon Design Solutions 0.15um Memories
Architecture
1- Port (1R/W)
Sync./Asnc.
Word
Bit
Mux
Size
Access Time (ns)
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.18
Worst: 1.83
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.18
Worst: 1.83
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.2
Worst: 1.88
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.01
Worst: 1.76
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
4 bit - 65 Kbit
64 x 64
Typical: 1.2
Worst: 1.83
Register File
2-Port (1R/1W)
Sync./Asnc.
Register File
3-Port (1R/1W)
Sync./Asnc.
Register File
4-Port (1R/1W)
Sync./Asnc.
Register File
4-Port (1R/1W)
Sync./Asnc.
1, 2, 4
Register File
15
Non-Free Libraries
Virage 0.18um Memory Compiler
Word
Width
(bits/word)
Word
Depth
(words)
Max
Size
(Kbits)
Max
Configuration
Aspect
Ration
(Yes/NO)
Tcyc for
2Kx16, 4Kx16
Block (Worst
Cond);
32x32 for
Reg. File
Ta for
2Kx16, 4Kx16
Block (Worst
Cond);
32x32 for
Reg. File
Bit/Byte
write
capability
Redundancy
Built-in
SP HD
SRAM
2 - 128
16 - 16K
32 - 512K
16 - 32K
Yes: 4,8,16
3.03, 3.33
2.99, 3.3
Yes
No
DP HD
SRAM
2 - 128
16 - 8K
32 - 256K
8x32K
Yes: 4,8,16
3.24, 3.67
3.19, 3.64
Yes
No
2P Register
File
2 - 256
8 - 1024
16 - 16K
1Kx16
Yes: 1,2,4
2.02
1.7
Yes
No
ROM
8 - 64
256 - 64K
2K - 1M
64Kx16
Yes: 16,32,64
4.09, 5.8
3.14, 4.34
No
No
SP HS
SRAM
2 - 256
16 - 16K
32 - 512K
16Kx32
4,8,16
2.15, 2.45
2.13, 2.42
Yes
No
DP HS
SRAM
2 - 256
32 - 8K
64 - 256K
8Kx32
4,8,16
2.44, 2.81
2.42, 2.78
Yes
No
SP STAR
HD-4M(SRAM with
redundancy)
8 - 256
128 - 64K
16K - 4M
64Kx64
Yes: 8,16,32
3.8, 4.1
3.6, 3.89
Yes
Yes
SP STAR
HS-512K
2 - 256
16 - 16K
32 - 512K
16Kx32
4,8,16
2.31, 2.61
2.29, 2.58
Yes
Yes
DP STAR
HS-512K(SRAM
with
redundancy
2 -256
32 - 8K
64 - 256K
8Kx32
4,8,16
2.6, 2.97
2.58, 2.94
Yes
Yes
T-CAM 32K
16 - 64
16 - 512
1K - 32K
512Kx64
1
6.46
3.81
No
No
Silicon Design Solutions 0.18um Memories
Architecture
Word
Bit
Mux
Size
Access Time (ns)
1-Port (1R/W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.67
Worst: 2.92
2-Port (1R, 1W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.66
Worst: 2.90
3-Port (2R, 1W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.72
Worst: 3.0
4-Port (3R, 1W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.72
Worst: 2.97
4- Port (2R, 2W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
2 - 256
(Increment: 1)
1, 2, 4
4 bit - 65 Kbit
64 x 64
Typical: 1.68
Worst: 2.93
16
Non-Free Libraries
Faraday 0.18um Library
Standard Cell
400+ high performance standard cells
9-track cell architecture
Average cell density >120K gates/sq.mm
Optimized multiple drive strengths
High porosity and routability
Scan version of every flip-flop available
Ultra low power cell available
Gated input for preventing leakage
Fully tool models support
Inline and Staggered I/O
1.8V, 3.3V I/O pads
1.8V/2.5VT, 3.3V/5VT I/O pads
Support over 500+ IO Functions
Pad pitch: 65um (In-line), 40um (Stagger)
Programmable current drives and slew rate control
from 2mA to 16mA
Programmable pull-up/pull-down resistor, normal/
Schmitt trigger
Provide 90+ programming features in one I/O
In-line to staggered I/O corner available
Analog
Excellent high PSRR and low jitter Phase-Locked
Loops
10-Bit DAC 200MHz
8-Bit ADC 135MHz
Power-on-reset circuit
Low VDD Detector
RC oscillators
Voltage Regulators
Comparators
Crystal pads
Single Port SRAM, Dual Port SRAM, and Via2 ROM
Compilers
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Provides both high speed and low power SRAMs
Ability to compile to multiple aspect ratio
Scan and BIST support
Power port connections support
Zero hold time for inputs
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
4 - 256K
(Increment:2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8, 16
4 bit - 2 Mbit
4K x 16
Typical: 1.4
Worst: 2.2
Dual Port
Sync. SRAM
4 - 32K
(Increment:2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8
4 bit - 512 Kbit
4K x 16
Typical: 1.7
Worst: 2.6
Via2 ROM
128 - 128K
(Increment:128X mux)
2 - 128
(Increment: 1)
1, 2, 4, 8
256 bit - 2 Mbit
4K x 16
Typical: 2
Worst: 3.2
Nurlogic 0.18um Library
Standard Cell
1000+ High Performance standard cells
9-track cell architecture
Average cell density of 73K gates/sq.mm
Multiple drive strengths
Silicon proven
Scan version of every flip-flop available
Compatible with mixed signal environment
Accurate timing and power models
In-line and staggered I/O
3.3V/5VT
Pad pitch: 76.8um (In-line), 38.4um (Staggered)
Multiple current drives up to 16mA
Pull ups, Pull downs, switchable
Hysteresis
Built-in level shifting
17
Non-Free Libraries
GlobalCAD 0.18um library
Standard cell and I/O
450+ cells
Silicon proven
Accurate timing characterization
Support most of the EDA tools
Optimized for Cadence and Avanti place & route tools
High routing density, routability, high speed and low
power
Routable for 3,4,5,6 metals
1.8V, 3.3V I/O
Drive strength 4,8,12,16, and 24 mA
Latchup performance: 200 mAmp
ESD protection: 2.0kV HBM
Low current leakage
Single Port SRAM, Two Port SRAM, Dual Port
SRAM and Via2 Mask ROM Memory Instances
Synchronous reads/writes
Static design with zero standby current
Bytes write capability
Provides both high speed and low power SRAMs
Ability to compile to multiple aspect ratio
Power port connections support
Architecture
Word
Bit
Mux
Size
Single Port
Sync. SRAM
32 - 8K
(Increment:8X mux)
8 - 64
(Increment: 1)
4, 8, 16
128 bit - 512 Kbit
Dual Port
Sync. SRAM
32 - 8K
(Increment:8X mux)
8 - 64
(Increment: 1)
4, 8,16
128 bit - 256 Kbit
Two Port
Sync. SRAM
32 - 8K
(Increment:8X mux)
8 - 64
(Increment: 1)
4, 8, 16
128 bit - 256 Kbit
Via2 MROM
32 - 8K
(Increment:128X mux)
1 - 64
(Increment: 1)
4, 8, 16, 32, 64
32 bit - 2 Mbit
Dolphin 0.18 um Library
Standard I/O
Staggered pad design with 35,50,70 um pitch
I/O pads for flip chip(C4) 240um &250um
I/O Drive strengths 2/4/6/8/10/12mA 1.8V core with
3.3V output
Pull-up, pull-down, sustain level options
4 different slew rate keeper options, JTAG inputs for
testability, Schmitt trigger inputs
Level shifts from 1.8 V core up to 3.3 V I/O supply
18
Non-Free Libraries
Faraday 0.25um Library
Standard Cells
400+ high performance standard cells
8-track cell architecture
Average cell density >60K gates/sq.mm
Optimized multiple drive strengths
High porosity and routability
Scan version of every flip-flop available
Ultra low power cell available
Gated input for preventing leakage
Fully tool models support
Inline and Staggered I/O
2.5V, 3.3V I/O pads
2.5V/3.3VT, 3.3V/5VT I/O pads
Support over 500+ IO Functions
Pad pitch: 65um (In-line), 40um (Stagger)
Programmable current drives and slew rate control
from 2mA to 16mA
Programmable pull-up/pull-down resistor, normal/
Schmitt trigger
Provide 90+ programming features in one I/O pad
In-line to staggered I/O corner available
Analog
Excellent high PSRR and low jitter Phase-Locked
Loops
10-Bit DAC 200MHz
8-Bit ADC 135MHz
Power-on-reset circuit
Low VDD Detector
RC oscillators
Voltage Regulators
Comparators
Crystal pads
Single Port SRAM, Dual Port SRAM, Diffusion and
Via2 ROM Compilers
Synchronous reads/writes
Static design with zero standby current
Byte write capability
Provides both high speed and low power SRAMs
Ability to compile to multiple aspect ratio
Scan and BIST support
Power port connections support
Zero hold time for inputs
Architecture
Word
Bit
Mux
Size
Access Time (ns)
Single Port
Sync. SRAM
4 - 256K
(Increment:2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8, 16
4 bit - 2 Mbit
4K x 16
Typical: 1.9
Worst: 3.1
Dual Port
Sync. SRAM
4 - 16K
(Increment:2X mux)
1 - 128
(Increment: 1)
1, 2, 4, 8
4 bit - 160 Kbit
4K x 16
Typical: 2.1
Worst: 3.3
Via2 ROM
128 - 64K
(Increment:128X mux)
2 - 128
(Increment: 1)
1, 2, 4, 8
256 bit - 1 Mbit
4K x 16
Typical: 2.1
Worst: 3.5
Diffusion ROM
128 - 64K
(Increment:128X mux)
2 - 128
(Increment: 1)
1, 2, 4, 8
256 bit - 1 Mbit
4K x 16
Typical: 7.3
Worst: 12.1
19
Non-Free Libraries
Nurlogic 0.25um Library
Memories
Single port register files, 24Kbits
Two port register files, 24Kbits
Standard Cells
1000+ cells
10-track cell architecture
Average cell density of 36K gates/sq.mm
Multiple drive strengths
Silicon proven
Scan version of every flip-flop available
Compatible with mixed signal environment
Accurate timing and power models
Analog
800MHz Phase Locked Loop (PLL)
266MHz Video Phase Locked Loop (PLL)
Fast Crystal Oscillator 4-33 MHz
In-line and Staggered I/O
3.3V/5VT
Pad pitch: 76.8mm (In-line), 52.8mm (Staggered)
Multiple current drives up to 16mA
Pull ups, Pull downs, switchable
Hysteresis
Built-in level shifting
Silicon Design Solutions 0.25um Memories
Architecture
Word
Bit
Mux
Size
Access Time (ns)
1-Port (1R/W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
1 - 256
(Increment: 1)
1, 2, 4
2 bit - 65 Kbit
64 x 64
Typical: 2.21
Worst: 3.58
2-Port (1R, 1W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
1 - 256
(Increment: 1)
1, 2, 4
2 bit - 65 Kbit
64 x 64
Typical: 2.16
Worst: 3.50
3-Port (2R, 1W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
1 - 256
(Increment: 1)
1, 2, 4
2 bit - 65 Kbit
64 x 64
Typical: 2.29
Worst: 3.70
4-Port (3R, 1W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
1 - 256
(Increment: 1)
1, 2, 4
2 bit - 65 Kbit
64 x 64
Typical: 2.20
Worst: 3.54
4- Port (2R, 2W)
Sync./Async
Register File
2 - 1K
(Increment: 1)
1 - 256
(Increment: 1)
1, 2, 4
2 bit - 65 Kbit
64 x 64
Typical: 2.18
Worst: 3.51
20
Non-Free Libraries
GlobalCAD 0.25um library
Features
450+ cells
Silicon proven
Accurate timing characterization
Support most of the EDA tools
Optimized for Cadence and Avanti place & route tools
High routing density, routability, high speed and low
power
Routable for 3,4,5,6 metals
2.5V, 3.3V, 5V I/O
Drive strength 4,8,12,16, and 24 mA
Latchup performance: 500 mA
ESD protection: 2.5kV HBM
Low current leakage
Single Port SRAM, Two Port SRAM, Dual Port
SRAM and Via2 Mask ROM Memory Instances
Synchronous reads/writes
Static design with zero standby current
Bytes write capability
Provides both high speed and low power SRAMs
Ability to compile to multiple aspect ratio
Power port connections support
Architecture
Word
Bit
Mux
Size
Single Port
Sync. SRAM
32 - 8K
(Increment:8X mux)
8 - 64
(Increment: 1)
4, 8, 16
128 bit - 512 Kbit
Dual Port
Sync. SRAM
32 - 8K
(Increment:8X mux)
8 - 64
(Increment: 1)
4, 8,16
128 bit - 256 Kbit
Two Port
Sync. SRAM
32 - 8K
(Increment:8X mux)
8 - 64
(Increment: 1)
4, 8, 16
128 bit - 256 Kbit
Via2 ROM
32 - 8K
(Increment:128X mux)
1 - 64
(Increment: 1)
4, 8, 16, 32, 64
32 bit - 2 Mbit
21
*
TMDS
GMII
*
DVI
LDTPhy
*
RGMII
HT K8 Phy
K7bus
GTL
I2C
USB2.0
USB1.1
PCI-X
PCI
AGP
SSTL
DDR-I/II
PECL
HSTL
HSDL
LVTTL
LVDS
CML
Technology Vendors
LVPECL
Special I/O
2x 4x 8x
0.13um
Dolphin
Leda
*
*
*
*
Macrotech
*
NurLogic
*
Faraday(LL)
*
*
*
*
*
*
*
*
Q4/02
Q4/02
Q4/02
*
*
GlobalCAD
Leda
VST
0.18um
Dolphin
*
*
Q4/02
Q4/02
*
*
*
*
*
*
*
*
*
*
Q3/02
*
*
*
*
*
Q4/02
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
(Low Power)
Faraday
*
GlobalCAD
*
*
*
*
Nurlogic
*
*
*
*
VST
0.25um
*
Q3/02
Q3/02
Leda
Q3/02
*
*
Nurlogic
*
Faraday
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Q3/02
*
*
*
*
*
*
*
GlobalCAD
GlobalCAD
*
*
Faraday
0.35um
*
Q2/02
Dolphin
VST
*
*
Q3/02
*
*
*
*
*
*
Q3/02
Faraday
Q4/02
*
GlobalCAD
0.15um
*
*
*
*
*
*
*
Faraday
VST
*
*
*
*
*
*
22
*
IP Catalog
UMC is helping designers and system developers overcome system-on-chip (SOC) and time-to-market hurdles by
providing easy access to third party IP blocks ready for integration into customer designs. Our goal is to build a
catalog of third party IP mega-cells customizable to UMC process technology. “Interoperability” of IP remains a
major element of our program, speeding customer time-to-market and lowering the risks associated with very deep
sub-micron design. The third party IP included in our IP catalog is characterized according to the following Gold IP
guidelines:
Bronze: Softcore or GDSII available
Silver: Hardcore available, silicon verified
Gold: Production verified
PLL
Part Number
ETI-2800
PLL8001
PLL8002
PLL8002D
PLL8003
PLL8005
PLL8007
PLL8011
PLL9011
PLL9011T
PLLA002
U103A
PLL
TC_UM13A3910_PL
TC_UM13A3920_DL
TC_UM13A3930_PD
LDPLL10-13
LDPLL10-18
LDPLL11-13
LDPLL3-13
LDPLL38-18
LDPLL39-15
LDPLL40-15
LDPLL6-13
LDPLL8-18
PLL2-15
125 MHz PLL
266MHz DeSkew PLL
CEPLL
PLL
Description
PLL, Fout < 800MHz
3.3V,ckout:2.5-280Mhz,N=1~32
3.3V, ckout:15-200Mhz,N/M=3/2 bit
Bronze
b
ckout:20-200Mhz,N/M=6/3
ckout:20-200Mhz,N/M=6/3
ckout:20-200Mhz,N/M=8/8
ckout:20-300Mhz,N/M=6/6
Gold
0.35um
0.35um
0.35um
3.3V, ckout:40-400Mhz,N/M=3/2 bit
3.3V,ckout:2.5-280Mhz,N=1~64
3.3V, ckout:5-280Mhz,N=1-32
3.3V, ckout:5-280Mhz,N=1-64
3.3V,
2.5V,
2.5V,
1.8V,
Silver
0.35um
0.35um
0.35um
0.35um
bit
bit
bit
bit
0.25um
0.25um
0.18um
b
PLL up to 1Ghz freq synthesis is possible (0.25um).
Silicon proven on 480MHz
programmable PLL clock generator. Integrated MUL
and DIV
Programmable PLL(250 MHz to 800 MHz)
DLL (Logic design—Synthesizable)
Phase Detector(Largic Design—Synthesizable)
3.1 GHz PLL
0.15um
0.13um
0.13um
0.13um
ITC
ITC
ITC
LEDA
b
LEDA
LEDA
LEDA
LEDA
b
0.15um
0.15um
LEDA
LEDA
LEDA
LEDA
0.15um
0.13um
0.13um
LEDA
Nurlogic
Nurlogic
Nurlogic
0.13um
Nurlogic
b
b
250-1650 MHz PLL
F-out: 100~167MHz
F-out: 66MHz,133MHz,266MHz
F-out: 78~700 MHz
0.13um
F-out: 80~333 MHz
23
Faraday
Faraday
Faraday
Faraday
GlobalCAD
0.35um/
0.25um/0.18um
0.13um
100-400 MHz PLL
400 MHz, 8 phase PLL
3 - 6 GHz PLL
2-50 Mhz PLL
Faraday
Faraday
Faraday
Faraday
FTDPL
b
b
50-200 MHz PLL
19.44-1244 MHz PLL
250-1650 MHz PLL
10-250 MHz PLL
Vendor
ETI
Faraday
Faraday
PLL
Part Number
Quadrature PLL
Video PLL 266 MHz
Fractional N Plls
Low refresh PLls
PLL_Expert
13PLL-150/174
13PLL-48
SXPLL-FS240
SXPLL-P800
TCI13HS400CGPLL
TCI13HS400DSPLL
Description
F-out: 107~333 MHz
F-out: 266 MHz
Bronze
Silver
Gold
0.13um
0.25um
0.18um
0.18um
0.18um
Frequency synthesizer: output frequency:
10 MHz - 650 MHz, Deskewing, programmable
feedback dividers
PLL, 150/174 MHz
PLL, 48 MHz
240 MHz Clock Generator PLL
0.13um-Q3/02
0.13um-Q3/02
0.35um
Vendor
Nurlogic
Nurlogic
Parthus
Parthus
Parthus
Sarnoff
Sarnoff
b
b
SliceX
SliceX
True Circuits
True Circuits
b
b
b
b
True
True
True
True
Circuits
Circuits
Circuits
Circuits
0.13um SP 160-800MHz Deskew PLL
0.15um HS 70-350MHz Clock Generator PLL
0.15um HS 70-350MHz Deskew PLL
b
b
b
b
True
True
True
True
Circuits
Circuits
Circuits
Circuits
TCI15HS700CGPLL
TCI15HS700DSPLL
TCI18G250CGPLL
TCI18G250DSPLL
0.15um
0.15um
0.18um
0.18um
HS
HS
GII
GII
140-700MHz Clock Generator PLL
140-700MHz Deskew PLL
50-250MHz Clock Generator PLL
50-250MHz Deskew PLL
b
b
b
b
True
True
True
True
Circuits
Circuits
Circuits
Circuits
TCI18G275CGPLL
TCI18G275DSPLL
TCI18G500CGPLL
TCI18G500DSPLL
0.18um
0.18um
0.18um
0.18um
G 55-275MHz Clock Generator PLL
G 55-275MHz Deskew PLL
GII 100-500MHz Clock Generator PLL
GII 100-500MHz Deskew PLL
b
b
b
b
True
True
True
True
Circuits
Circuits
Circuits
Circuits
TCI18G550CGPLL
TCI18G550DSPLL
TCI25G200CGPLL
TCI25G200DSPLL
0.18um
0.18um
0.25um
0.25um
G
G
G
G
b
b
b
b
True
True
True
True
Circuits
Circuits
Circuits
Circuits
TCI25G400CGPLL
TCI25G400DSPLL
0.25um G 80-400MHz Clock Generator PLL
0.25um G 80-400MHz Deskew PLL
b
b
True Circuits
True Circuits
TCI13HS800CGPLL
TCI13HS800DSPLL
TCI13SP400CGPLL
TCI13SP400DSPLL
TCI13SP800CGPLL
TCI13SP800DSPLL
TCI15HS350CGPLL
TCI15HS350DSPLL
Programmable 96-800MHz PLL
0.13um HS 80-400MHz Clock Generator PLL
0.13um HS 80-400MHz Deskew PLL
0.13um HS 160-800MHz Clock Generator PLL
0.13um
0.13um
0.13um
0.13um
HS
SP
SP
SP
160-800MHz Deskew PLL
80-400MHz Clock Generator PLL
80-400MHz Deskew PLL
160-800MHz Clock Generator PLL
110-550MHz Clock Generator PLL
110-550MHz Deskew PLL
40-200MHz Clock Generator PLL
40-200MHz Deskew PLL
24
0.25um
ADC
Part Number
ADC8011
ADC9011
1-bit ADC
LDACD20-18
LDADC10-13
LDADC20-13
LDADC24-18
LDDADC25-18
LDDADC29-18
13ADC10-50
SXAD0810M
SXAD1016M-0
SXAD1032M-0
Description
SAR ADC 10bit 100KSPS two channels VCC=3.3V
SAR ADC 8bit 100KSPS VCC=3.3V for core and 2.5V
for digital output interface
Maximum cover frequency 1 MHz with 20mV peak to
peak voltage level
10 bit, 100 Msps ADC
16 bit, 44KHz Sigma-Delta ADC
10 bit, 100 Msps Pipeline ADC
10 bit, 1 Msps ADC
Dual 10 bit,1 Msps ADC
6 bit, 44 Msps dual ADC
Bronze
Silver
Gold
0.35um
Faraday
0.25um
0.25um
b
GlobalCAD
LEDA
LEDA
LEDA
LEDA
b
b
0.18um
b
LEDA
LEDA
Sarnoff
SliceX
b
0.13um-Q3/02
0.35um
0.35um
0.35um
ADC 10 bits, 50 MHz
8-bit 10MSPS A/D Converter
10-bit 16MSPS A/D Converter
10-bit 32MSPS A/D Converter
Vendor
Faraday
SliceX
SliceX
DAC
Part Number
ETI-3008
ETI-3009
ETI-3010
ETI-3108
ETI-3109
ETI-3110
DAC8001
DAC8002
DAC8003
DAC8011
DAC9003
DAC9011
8-bit ADC
LDDAC11-18
LDDAC2-13
LDDAC3-13
LDDAC4-18
Description
8-bit Video DAC, 520MHz, triple video with sync
Bronze
9-bit Video DAC, 520MHz, triple video with sync
10-bit Video DAC, 520MHz, triple video with sync
8-bit Video DAC, 570MHz, triple video with sync
9-bit Video DAC, 570MHz, triple video with sync
10-bit Video DAC, 570MHz, triple video with sync
8bit 200MHz one channel VCC=3.3V
8bit 200MHz three channels VCC=3.3V
Current steering DAC 10bit 80MHz VCC=3.3V
R2R DAC 8bit 500KSPS one channel VCC=3.3V
Current steering DAC 10bit 80MHz one channel,
VCC=3.3V and 2.5V for digital input interface
R2R DAC 8bit 500KSPS one channel VCC=3.3V for
Silver
ETI
ETI
ETI
ETI
0.18um
0.18um
0.35um
0.35um
ETI
ETI
Faraday
Faraday
0.35um
0.35um
0.25um
Faraday
Faraday
Faraday
0.25um
Faraday
0.25um
b
0.18um
25
GlobalCAD
LEDA
LEDA
b
b
10 bit, 200 MHz DAC
Vendor
0.25um
0.25um
0.25um
0.18um
core and 2.5V for digital input interface
8-bit successive approximation (SAR) ADC. Operates
upto 1.5 MHz.
Features with analog comparator with sample-and-hold
and offset calibration
8 bit, 5 Mhz DAC
10 bit, 100 MHZ Current DAC
12 bit, 250 MHz Current DAC
Gold
LEDA
LEDA
DAC
Part Number
LDDDAC14-18
LDDDAC32-18
LDTDAC8-13
LDTDAC8-15
18DAC10
18DAC12
Bronze
b
Description
10 bit, 1 MHz dual DAC
8 bit, 44 MHz dual DAC
Triple 10 bit 400 MHz Video DAC
Silver
Gold
b
PWMSSDAC
Triple 10 bit, 400 MHzVideo DAC
10-bit DAC
12-bit DAC
24-Bit, Audio D/A Converter with Oversampling
13DAC12-200
SXDA10-0
Interpolation Filter
DAC 12 bits, 200 MHz
10-bit 90MSPS Current Steering DAC
Vendor
LEDA
LEDA
0.13um
0.15um
0.18um
0.18um
LEDA
LEDA
Macrotech
Macrotech
0.18um
NEL
0.13um-Q3/02
0.35um
Sarnoff
SliceX
ANALOG/MIXED-MODE
Description
1MHz ~ 20MHz
XTAL OSC
20MHz ~ 35MHz XTAL OSC
EOSC3
BGA001
BGC001
BGC002
35MHz ~ 50MHz XTAL OSC
VCC=3.3V VBG=1.23V
VCC=3.3V VBG=1.23V
VCC=1.2V VBG=0.615V
CMP9001
CMPTDI
OSC8002
OSC9001
0.25um 20MHz General Purpose Comparator
0.8V and 4.4V Voltage Comparator for Voltage Detector
Oscillator VCC=3.3V
Oscillator VCC=2.5V
POR8001
Power On Reset with detect voltage Vrr=2.3V
Vfr=2.1V VCC=3.3V
Power On Reset with detect voltage Vrr=1.9V
Vfr=1.6V VCC=2.5V
0.35um
Faraday
Faraday
Faraday
0.25um
Faraday
Power On Reset with detect voltage Vrr=1.8V
VCC=2.5V
Power On Reset with detect voltage Vrr=1.1V
Vfr=1.0V VCC=1.8V
0.25um
Faraday
0.18um
Faraday
POR9001
POR9002
PORA001
PORM3
REG8003H
REG9001H
REG9002H
Bronze
0.25um, 0.35um
Silver
Gold
Vendor
ETI
Part Number
EOSC1
EOSC2
0.13um
ETI
ETI
Faraday
Faraday
0.13um
0.25um
0.35um
Faraday
Faraday
Faraday
0.25um, 0.35um
0.25um, 0.35um
0.18um
Power On Reset with detect voltage Vrr=2.6V
VCC=3.3V
Regulator with driving capability 150mA VCC=5V
V33=3.3V and low standby current
Regulator with driving capability 70mA VCC=3.3V
V25=2.5V
Regulator with driving capability 150mA VCC=3.3V
V25=2.5V
26
0.35um
0.25um
0.35um
0.35um
Faraday
Faraday
0.35um
Faraday
0.25um
Faraday
ANALOG/MIXED-MODE
Part Number
REGA001H
Description
Regulator with driving capability 50mA VCC=3.3V
VDT8002
V18=1.8V
Regulator with driving capability 100mA VCC=3.3V
V18=1.8V
Voltage detector with Vdet=2.8V VCC=3.3V
VDT9001
LV
Voltage detector with Vdet=2.0V VCC=2.5V
Voltage level shifter
REGA002H
Bronze
Silver
0.35um
0.25um
0.15um
Gold
0.18um
Vendor
Faraday
0.18um
Faraday
0.25um,
Faraday
Faraday
GlobalCAD
0.18um
OSC10_50
Design to work with standard 10 MHz to 50 MHz real
OSC24
OSC32
time crystal
Design to work with standard 24 MHz real time crystal
Low power consumption (less than 40uA).Power down
mode and works with standard 32 KHz real time
crystal
Design to work with standard 48 MHz real time crystal
OSC48
Power Regulator Feed in 3.3V and regulated to 2.5V with maximum
current of 100 mA
ROSC
ITC_UM13A3924_OS
BGB2-18
LDBGB1-13
Relaxation Oscillator
Oscillator (10 to 30 MHz) — four pad locations (2 pwr)
3.3v, external R. Bandgap
Bandgap with internal resistor
LDBGB1-15
LDBGB2-15
LDBGB4-13
LDBGB5-13
Bandgap, 3.3v with internal resistor
2.5v, internal R. Bandgap
Internal Resistor Bandgap
Bandgap with internal resistor
LDCMP1-15
LDMUX1-15
LDOP1-15
LDOP4-15
P-channel Comparator, 12ns delay
2 input, 50 ohm Analog MUX
Opamp
1 MHz, 2.5V Opamp
LDOP6-15
LDPMC1-18
LDPMC2-18
LDVR3-18
1 MHz, 2.5v Opamp
3.3v PCM
1.8v PCM
Ext BG, x4 20 mA Voltage Regulator
LDXTAL1-15
LDXTAL3-18
LDXTAL4-18
POR3-18
27 MHz Crystal Oscillator
10-15 MHz Crystal Osc.
10-15 MHz Crystal Osc.
Power on reset
VR1-18
VR2-18
13AIOP
13BNDGP
Ext BG, 5 mA Voltage Regulator
Ext BG, 20 mA Voltage Regulator
Analog I/O Pad
Bandgap Reference
13PWRD
Power Detect
0.15um
0.13um
b
0.13um
0.15um
0.15um
b
b
0.15um
0.15um
0.15um
0.15um
b
b
b
b
0.15um
b
b
b
b
0.25um
GlobalCAD
0.25um
GlobalCAD
0.18um
GlobalCAD
0.25um
GlobalCAD
0.18um
GlobalCAD
ITC
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
b
0.13um-Q3/02
0.13um-Q3/02
0.13um-Q3/02
27
GlobalCAD
0.35um
Sarnoff
Sarnoff
Sarnoff
BUS INTERFACE
Part Number
FPCI
Description
PCI MASTER/SLAVE 33MHz
Bronze
FPCI66
PCI MASTER/SLAVE 66MHz
FUSB100
USB 1.1 controller with Bulk, Interrupt, ISO, and Control
transfer
G2262U
USB
PECL
SL100
SL200
Sl250
SL258
SL730
SL75
SL755
SL770e
1377
1378
1696
1698
1755
1761
1805
1807
1813
1992
1994
1997
2179
2387
2513
Gold
0.35um
0.25umQ3/02
0.25um
0.25um
0.25um
Faraday
Faraday
Faraday
Faraday
Faraday
0.18um
USB1.1
RS232 Compatible UART
Universal USB transceiver
Universal USB protocol engine
Vendor
Faraday
Faraday
0.35um
FZUSB200H90A USB2.0 Transceiver
USB1.1
USB90B1H
USB1.1
USB90B2H
USB1.1
USBA0A1H
ZUSB_S80A
G2250
G2261U
Silver
0.25um,
0.35um
Faraday
GlobalCAD
GlobalCAD
GlobalCAD
0.35um,
0.25um,
0.18um
GlobalCAD
0.35um
b
b
USB transceiver is fully support to Standard USB
Rev. 1.1
Low power consumption. Support full speed
(12 Mbs),low speed(1.5Mbs)and suspension mode
0.15um
This receiver is terminated to reflection noises in order to
provide better signal
USB 1.1 Device Controller
USB 2.0 Transceiver
0.25um,
0.18um
b
b
Innovative
Innovative
USB 2.0 Device Controller
USB - AHB Device Controller
1394a PHY
USB 1.1 Transceiver
b
b
b
b
Innovative
Innovative
Innovative
Innovative
1394a Link
1394a A/V Link with encryption
32 bit, 33MHz PCI
32 bit, 66MHz PCI
b
b
b
b
Innovative
inSilicon
inSilicon
inSilicon
64 bit, 33MHz PCI
64 bit, 66MHz PCI
IEEE 1394A Device Controller Link Core
IEEE-1394 CPHY Synthesizable Core - Digital Cable PHY
b
b
b
b
inSilicon
inSilicon
inSilicon
inSilicon
USB 1.1 Host Controller Synthesizable Core
b
USB 1.1 Device Controller Synthesizable Core (Function) b
USB 1.1 HUB Controller Synthesizable Core
b
IEEE 1394A AV Link Core (61883)
b
inSilicon
inSilicon
inSilicon
inSilicon
IEEE-1394 OHCI Link
PCI-X
USB 2.0 Device Controller
USB 2.0 PHY UTMI (Hard Macro)
b
b
b
inSilicon
inSilicon
inSilicon
inSilicon
Utopia Level III
b
0.18um
28
Innovative
inSilicon
BUS INTERFACE
Part Number
2530
2554
CION200T1225
LDCML1-13
LDCML2-13
LDDVI1-15
LDDVI-13
LDLVDS1-13
LDLVDS2-15 (Rx)
LDLVDS2-15 (Tx)
LDLVDS3-13 (Rx)
LDLVDS3-13 (Tx)
LDLVDS4-13
LDLVPECL1-13
LDLVTTL1-15
LDSSTL2CII-15
LDSSTL2CII3-13
LDTMDS1-13
LDTMDS1-15 (Tx)
LDTSC8-18
LDUSB1-13
LVDS4-15 (Rx)
LVDS4-15 (Tx)
LVTTL8IO100-15
LVTTLRX100-15
LVTTLTX100-15
M1284H
M16550A
M16550S
M16C450
M16X50
M82365SL
M8490
MCAN2.0
MI2C
MI2Cv2
MPCI32
MPCMCIA1
MUSBFDRC
MUSBFSFC
MUSBHSFC
MUSBLSFC
Bronze
Description
USB 2.0 Host Controller
Silver
0.18um
b
USB On-The-Go
Cardbus
200 MHz LVCMOS
CML 1.5 GHz
b
b
b
b
CML 2.5 GHz
6 Channel 1.65 GHz DVI (Tx)
Triple 1.65G DVI TX
LVDS 750 MHz
0.15um
0.13um
b
622-800 MHz LVTTL
622-800 MHz LVTTL
1.244 GHz LVDS
1.244 GHz LVDS
0.15um
0.15um
0.13um
0.13um
b
LVDS 622 GHz
LVPECL 750 MHz
8 mA Bidirectional LVTTL
400 Mhz SSTL
b
0.15um
b
b
SSTL, 2.5v, 167 MHz
TMDS 1.625 GHz
TMDS 250-1650 MHz
Touch Screen Controller
0.13um
0.15um
b
b
USB 1.1(12 MHz)
622 MHz LVDS
622 MHz LVDS
8 mA, 100 MHz bd LVTTL
0.15um
0.15um
0.15um
100 MHz Rx LVTTL
8 mA, 100 MHz Tx LVTTL
IEEE 1284 Host Parallel Port
Enhanced UART with FIFO
0.15um
0.15um
Enhanced UART with FIFO and Synchronous CPU I/F
UART
Enhanced UART with FIFO and IrDA
PCMCIA PC Host Interface
5380 Compatible SCSI Interface
CAN 2.0 Network Controller
I²C Bus Interface
I²C V2.0 Bus Interface
32Bit 33/66MHz PCI Peripheral Core
PCMCIA PC Card Interface
USB 2.0 High/Full Speed Function Controller (OTG)
USB 1.1 Full Speed Function Controller
USB 2.0 High/Full Speed Function Controller
USB 1.1 Low Speed Function Controller
29
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
Gold
Vendor
inSilicon
inSilicon
inSilicon
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
LEDA
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
BUS INTERFACE
Bronze
Part Number
Description
Hypertransport PHY Hypertransport PHY Interface Core
PCI 1366
PCI, 33MHz/66MHz
PCI 13X
PCI-X, 66MHz/133MHz
PCI 25
PCI, 33MHz/66MHz
BK-3103
UART - 16450/16550 compatible UART
BK-3105
UART lite
BK-3110
UART - Smart 16550 Compatible
BK-3211
BK-3220
BK-3401
BK-3712
BK-3713
BK3754
DW_PCI
DW_PCIX
DW_USB
M16450
M16550A
V6001
V6201
V8101
V9012P
Wipro1394A-1000
Wipro1394A-1010
Wipro1394A-1200
Wipro1394A-1400
Wipro1394A-2000
Wipro1394BLink
Wipro1394BPHY
WiproUSB1.1Dev
WiproUSB1.1Host
WiproUSB2.0Dev
Silver
0.13um-Q4/02
Gold
0.13um
0.13um
0.25um
SPI master core
Serial I2 C
IEEE 1284 parallel port controller
PCMCIA Host Controller
PCMCIA Client Interface
ISO7816 smart card interface
PCI 2.2 core
PCI-X core
USB 2.0 device controller
UART
b
b
Nurlogic
Nurlogic
Palmchip
Palmchip
b
b
b
b
Palmchip
Palmchip
Palmchip
Palmchip
b
b
b
Palmchip
Palmchip
Palmchip
Synopsys
0.25um
UART with FIFO
AMBA AHB-APB Bus Bridge
Configurable PCI-X Controller
AHB-Based Memory Controller
USB 1.1 Device Controller
1394.a Link
1394.a Link+PCI
1394.a Link+OHCI+PCI
b
b
b
b
Synopsys
Synopsys
Virtual IP Group
Virtual IP Group
b
b
b
b
Virtual
Virtual
Virtual
Virtual
0.35um
1394 A/V Link + 5C Content Protection
1394.a Digital PHY
1394.b Link
1394.b Digital PHY
USB 1.1 Device Controller Core
USB 1.1 Host Controller Core
USB 2.0 Device Controller Core
30
Vendor
Nurlogic
Nurlogic
b
b
b
Wipro
Wipro
Wipro
Wipro
b
b
b
b
Wipro
Wipro
Wipro
Wipro
b
b
Wipro
Wipro
IP
IP
IP
IP
Group
Group
Group
Group
MICROCONTROLLER AND MICROPROCESSOR
Part Number
ARCtangent
Description
Synthesizable 32-bit RISC/DSP core customizable instr
set, code compression, DSP
Turbo 186
Turbo 86
V186
V6502
“Turbocharged” 80186 microprocessor core
“Turbocharged” 8086 microprocessor core
“Classic 80186 microprocessor core
6502 microprocessor core
b
b
b
b
V8
V8086
VZ80
ARM1022E
V8 microRISC microprocessor core
“Classic” 8086 microprocessor core
Z80 Microporcessor Core
ARM1022E
b
b
b
ARM7TDMI
ARM7TDMI
ARM922T
ARM922T
ARM946E
ETM10
Embedded Trace Macrocell ARM10 cores
ETM7
ETM9
F8031
Embedded Trace Macrocell ARM7 cores
Embedded Trace Macrocell ARM9 cores
8-bit micro-controller with standard 12clk/machine
cycle128 bytes of on-chip Data RAM,two 16-bit timer/
FT8032
G1000
G2000
Silver
Gold
ARC International
ARC International
ARC
ARC
ARC
ARC
ARM
ARM
ARM
ARM
0.13um-Q3/02
0.13um-Q4/02
0.13um-Q3/02
0.35um
Faraday
0.35um
Faraday
0.18um, Faraday
0.25um,
8-bit micro-controller high speed 4clk/machine cycle
architecture 256 bytes of on-chip Data RAM,Three 16-bit
timer/countersTwo 16-bit dptr
Integrated 8-bit micro-controller core compatible with
0.35um
GlobalCAD
0.15um, 0.18um,
0.25um, 0.35um
0.15um, 0.25um 0.18um, GlobalCAD
0.35um,
0.5um
GlobalCAD
0.35um
8052 specification
Integrated 16/32-bit micro-controller with many peripherals
GC2000CA
31
International
International
International
International
ARC International
ARM
0.13HS-Q3/02
0.25um, ARM
0.13SP &
0.13LL-Q3/02 0.18um
0.13HS, Q3/02 0.18um ARM
counters
8-bit micro-controller with standard 12clk/machine
cycle256 bytes of on-chip Data RAM,Three 16-bit timer/
counters
8088/8086/80186 Compatible Microprocessor Core,
100MHz
GC2000CB
80186 Compatible Microcontroller, 100MHz
ITC_UM13A3950_RK OMNIcore — 32-bit RISC Processor
ITC_UM13A395A_RK OMNIcore — 32-bit RISC Processor with AMBA AHB
M8051
8-bit Microcontroller
M8051EW
Fast 8-bit Microcontroller with on-chip debug
Vendor
ARC International
0.13SP, Q3/02
0.15LL
0.18um-Q3/02,
0.13SP-Q4/02
ARM946E
F8032
Bronze
b
0.35um
0.13um-Q3/02
0.13um-Q3/02
b
b
GlobalCAD
ITC
ITC
Mentor
Mentor
MICROCONTROLLER AND MICROPROCESSOR
Part Number
M8051W
M8052
Description
Fast 8-bit Microcontroller
8-bit Microcontroller
20Kc
FM-6251
FM-6255
SH-4
High performance 64-bit Microprocessor core
1 inch Micro-Drive, Ultra Low Power Portable, Controller
1 inch Micro-Drive, Ultra Low Power Portable Controller
CPU Core, max. 300MHz
SH4-202
DW_8051
Xtensa
M8051TC
32-bit RISC-FPU Microprocessor Core, 266MHz
8051 microcontroller
32-bit Configurable RISC Micropro. Core
8-bit MCU
0.13um-Q3/02
Vendor
Mentor
Mentor
MIPS
0.13um-Q3/02
0.13um-Q3/02
Palmchip
Palmchip
SuperH
SuperH
Bronze
b
b
Silver
Gold
b
b
0.25um
0.18um
0.35um
Synopsys
Tensilica
Virtual IP Group
MICROPROCESSOR PERIPHERAL
Part Number
SBC-5
G2237
G2254
G2259
M146818
M8237A
M8254
M8255
M8259A
M85230
M85C30
Description
On-chip System Bus Controller
Bronze
Silver
b
0.35um
Programmable DMA Controller
Programmable Timer/Counter
Programmable Interrupt Controller
Real Time Clock
0.35um
0.35um
4 Channel DMA Controller
3 Channel Counter-Timer
Parallel Peripheral Interface
8 Channel Programmable Interrupt Controller
Enhanced Version of M85C30 Serial Comm.
Controller
Serial Communications Controller w/FIFOs
32
b
b
b
b
b
b
b
b
Gold
Vendor
3DSP
GlobalCAD
GlobalCAD
GlobalCAD
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
DSP
Part Number
SP-20
SP-3
SP-5
Description
1200 MIPS Digital Signal Processor
200 MIPS Digital Signal Processor
400 MIPS Digital Signal Processor
FD216
FD220
16-bit fixed point DSP
24-bit fixed point DSP
Bronze
Silver
Gold
b
0.25um
b
0.18um,
0.35um
Vendor
3DSP
3DSP
3DSP
Faraday
Faraday
0.25um,
0.35um
DSP
ITC_UM13A3970_DP
ITC_UM13A397A_DP
ZSP400
ZSP500
ZSP600
FFT
Integrated 32-bit CPU and DSP, up to 100 MHz 0.35um
0.25um
Real time MPEG2 decoder and encoder
RADcore — Configurable DSP Coprocessor
RADcore — Config. Coprocessor with AMBA AHB
16 bit Dual MAC DSP Processor
16 bit Dual MAC High Performance DSP
16 bit Quad MAC Media DSP
Fast Fourier Transform/Inverse FFT/Fast
GlobalCAD
0.13um-Q3/02
ITC
ITC
0.13um-Q3/02
0.18um
LSI
LSI
LSI
Mentor
Gold
Vendor
Faraday
Faraday
Faraday
b
b
b
Convolver
COMMUNICATIONS
Part Number
FEP110H90A
FMAC
LVDSR80H80A
U104A
U108A
U110A
2524
2284
2371
2452
LDMWISPI4P2
LDQSD1-13
LDQSD6-13
Description
100/10 Base Ethernet PHY VCC=2.5V
Ethernet 10/100 media access controller
Bronze
LVDS Receiver
LVDS Transmitter
Silver
0.25um
0.25um
0.35um
0.18umQ3/02
FTDPL
Tapeout
0.18um
0.18um
b
LVDS Receiver
DVI Receiver
10/100 Ethernet MAC core
Packet over Sonet Layer 3
SPI-4 level 1
10/100/1000 Ethernet MAC
System Packet Interface Level 4 (SPI-4) Phase 2:
Quad 3.1Gbps SerDes TRX
Quad 2.5/3.1/5.0 Gbps SerDes
10/100/1000 MAC 10/100/1000 Mbps Ethernet MAC
E1 Deframer
E1-DFRM
E1 Framing/Deframing Kit (Re-ordering Add/Drop)
E1-KIT-R
33
FTDPL
FTDPL
inSilicon
inSilicon
inSilicon
b
b
b
0.13um-Q3/02
0.13um
b
b
b
b
inSilicon
LEDA
LEDA
LEDA
Mentor
Mentor
Mentor
COMMUNICATIONS
Part Number
E1-KIT-S
HDLC-CORE
HDLC-FIFO
HDLCxN
PE_GMAC0
PE-MACMII
T1-DFRM
T1-E1-FRM
T1-KIT-R
T1-KIT-S
X50-RX
X50-TX
MystiPHY110
SerDes
SXPNA20-T1
Wipro802.11
Wipro802.11a
Wipro802.11b
Wipro8023-1000
Wipro8023-1010
WiproBthh/w
WiproGMAC
Description
E1 Framing/Deframing Kit (Selective Add/Drop)
Single Channel HDLC Core
Single Channel HDLC with FIFO
Bronze
b
b
b
Multi-Channel HDLC Controller
Gigabit Ethernet MAC
10/100 Mbps Dual-Speed Ethernet MAC
T1 Deframer
b
b
b
b
T1/E1 Framer
T1 Framing/Deframing Kit (Re-ordering Add/Drop)
T1 Framing/Deframing Kit (Selective Add/Drop)
X50 Multiplexing Receiver
b
b
b
b
X50 Multiplexing Transmitter
10/100 Mbps ETHERNET TX PHY
b
Silver
Mentor
Mentor
Mentor
Mentor
0.35um
HomePNA 2.0 Tranceiver
802.11 MAC
802.11a Baseband Controller Core
802.11b Baseband Controller Core
b
b
b
10/100 Mbps Ethernet MAC
10/100mbps Enthernet MAC+PCI
Bluetooth Hardware Baseband Controller
Gigabit Ethernet MAC
b
b
b
b
34
Vendor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
0.18um, 0.13umQ2/02
0.13um-Q4/02
Quad 3.318Gbps Transceiver Core
Gold
Mentor
Mentor
Mysticom
Nurlogic
SliceX
Wipro
Wipro
Wipro
Wipro
Wipro
Wipro
Wipro
CONSUMER
Part Number
FJPEG
2283
Description
JPEG encoder
JPEG CODEC
2429
2492
2517
2518
DES and Triple DES Encryption
AES Encryption Core
JVXtreme Java Accelerator CoProcessor
JPEG 2000 CODEC
DCT-8X8
G711-CMP
G711-EXP
INT-DEINT
8X8 Discrete Cosine Transform
G711 PCM Compressing Function
G711 PCM Expanding Function
Interleaver/Deinterleaver
PRSDEC
PRSENC
RSDEC
RSENC
Programmable Reed-Solomon Decoder
Programmable Reed-Solomon Encoder
Reed Solomon Decoder
Reed Solomon Encoder
TRELLIS
V42BIS
VC
VITERBI
Trellis Decoder
V.42bis Compression Engine
Voice Codec
Viterbi Encoder/Decoder
Bronze
Silver
Gold
0.35um
b
b
b
b
Vendor
Faraday
inSilicon
inSilicon
inSilicon
inSilicon
inSilicon
b
b
b
b
Mentor
Mentor
Mentor
Mentor
b
b
b
b
Mentor
Mentor
Mentor
Mentor
b
b
b
b
Mentor
Mentor
Mentor
Mentor
b
STORAGE
Part Number
M765A78
Description
Floppy Disk Controller
M82092IDE
M82371IDE
M82801IDE
MDDS78
IDE Controller, ATA-1
IDE Controller, ATA-4 (UDMA/33)
IDE Controller, ATA-5 (UDMA/66)
Digital Data Separator for Floppy/Tape
MFDC78
BK-3709-133
BK-3709-33/66/100
BK-3710-133
PC-AT Floppy Disk Controller
IDE Host Ultra ATA-133 w/o DMA
IDE Host Ultra ATA-33/66/100 w/o DMA
IDE Host Ultra ATA-133 with DMA
Bronze
b
b
b
b
b
b
b
b
b
b
BK-3710-33/66/100 IDE Host Ultra ATA-33/66/100 with DMA
35
Silver
Gold
Vendor
Mentor
Mentor
Mentor
Mentor
Mentor
Mentor
Palmchip
Palmchip
Palmchip
Palmchip
INTEGRATED PLATFORM
Part Number
A5001-EUI
DP-1800
DP-1845
Description
802.11
802.11 a/b/g Mac’s, 802.11 a/g Baseband Phy’s,
802.11 a/b/g dual mode Baseband Phy
Wireless IA platform - includes baseband
compatible with industry Standard Radio. Protocol
BlueStream
(Baseband)
BlueStream
(Radio)
GPS
InfoStream
MediaStream
DW_AMBA
Bronze
512-bit RSA Encryption Accelerator
Configurable Storage-Connectivity SoC Platform
Linux Supported Configurable Storage-Connectivity SoC Platform
Silver
0.25um
Gold
Vendor
b
b
AIL
Palmchip
Palmchip
b
Parthus
0.18um
Parthus
stack.
Wireless IA platform in RF CMOS process
0.18um
Parthus
Complete GPS solution for Cellular and Telematic
0.18um
Parthus
application- Baseband, Software and RF. Meets
911 reqt.
PDA platform -designed with ARM9 processorPLLs, multiple I/O’s, USB transceiver, touch
screen A/D
Single chip MP3 platform - includes DSP cores,
I2C slave, PLL, and DMA controller.A 6 chaneel
general purpose audio processor designed for
audio decoding, processing, speech recognition
and voice coding.
AMBA on-chip bus platform and peripherals
0.18um
Parthus
0.18um
Parthus
b
Synopsys
DESIGN-FOR-TEST
Part Number
MBISTmaker
Description
Built-In Self-Test, Diagnosis and Repair of
DW_membist
embedded memories
Memory BIST cores (RAM + ROM)
Bronze
b
36
Silver
Gold
0.18um
Vendor
Genesys Testware
Synopsys
EMBEDDED NON-VOLATILE MACRO
Part Number
EEPROM
EEPROM
EPROM
Flash
Description
18.34um2 cell,16K max size
Brone
9.82um 2 cell size,6.4K bit max size
3.24um 2 cell size,2M max size
2um2 cell size,2M max size
0.25um
Description
6 additional spec available on request
Bronze
Silver
Gold
0.35um
Vendor
UMC
0.5um
UMC
UMC
UMC/PMC
Gold
Vendor
0.35um
EMBEDDED SRAM MACRO
Part Number
1T SRAM standard macro
1T-SRAM
1T-SRAM-M
MoSys 1T-SRAM® Ultra-dense Memory
MoSys 1T-SRAM® Ultra-dense Memory for Mobile
applications
1T-SRAM-R
MoSys 1T-SRAM® Ultra-dense Memory with
Transparent Error Correction
M1T0D5HU18PE64E
M1T0D5LU15FE32E
M1T1HU18PE64E
1T-SRAM
1T-SRAM
1T-SRAM
1T-SRAM
M1T2D5LU15FE64E
0.5-Mbit 220Mhz 8KX64
0.5-Mbit 18Mhz 16KX32
1-Mbit 220Mhz 16KX64
2.5-Mbit 18Mhz 40KX64
6.4um 2 cell size,2Mbit max size,100 MHz,HS/sync.
15.8um 2 cell size,512 Kbit max size,100 MHZ,HS/
sync.
15.8um2 cell size,512 Kbit max
SRAM(6T)
size,Tacc=10ns,HS/async.
4.0um 2 cell size,2Mbit max size,100 MHz,HS/sync.
4.17um 2 cell size,1Mbit max size,120MHz,HS/sync
2.28um 2 cell size,2Mbit max size, 133MHz, HS/
sync
37
Silver
MOSYS
MOSYS
0.18um,
0.15um,
0.13um-Q2/02
0.18um,
MOSYS
0.15um,
0.13um-Q2/02
0.13um-Q2/02
0.18um,
0.15um,
0.18um,
0.15um,
MOSYS
Q3/02
Q3/02
Q3/02
Q3/02
MOSYS
MOSYS
MOSYS
0.35um
MOSYS
UMC
UMC
0.35um
UMC
0.25um
0.18um
0.15um
0.13um
UMC
UMC
UMC
EMBEDDED ARRAY
Part Number
VariCore
eASICore .13
eASICore .15
eASICore .18
eI/O .15
Description
High Efficient embedded FPGA core. Configuration
Vl8L4x4R-U, Vl8L4x2R-U, Vl8L2x2R-U, Vl8L4x4-U,
Vl8L4x2-U, Vl8L4x1-U, Vl8L2x2-U, Vl8L2x1-U
High density configurable logic core(60Kgate/mm2)
with FPGA-like Time-to-Market
Brone
Silver
Gold
0.18um
Vendor
Actel
b
eASIC
High density configurable logic core(45Kgate/mm2)
with FPGA-like Time-to-Market
High density configurable logic core(30Kgate/mm2)
with FPGA-like Time-to-Market
0.15um
eASIC
0.18um
eASIC
Single mask configurable I/O cell (can be configured
as INPUT, OUTPUT, BI-DIRECTIONAL, or SUPPLY)
0.15um
eASIC
MEMORY SUB-SYSTEM
Part Number
CG-7410
CG-7420
DW_memcntrl
Brone
b
Palmchip
DDR Shared Memory Processor ( 32/64 bit, 8 Channels, 400Mhz, ECC )
Memory controller core (DRAM, SRAM, FLASH, ROM)
b
Palmchip
b
Synopsys
38
Silver
Gold
Description
SDRAM Shared Memory Processor
( 32 bit, 8 Channels, 166Mhz, Flash, SRAM, SDRAM)
Vendor
R
Silicon Shuttle Program
form and will also offer special shuttles targeted at our
mixed-signal and RF CMOS processes. In June 2002, UMC
will subcontract the 0.25um logic Silicon Shuttle service
to Faraday and will begin offering mature shuttle processes
to better meet customer’s time-to-market and economical
prototyping demands.
Early silicon verification of your prototype designs is the
key to bringing your product to market ahead of the competition. However, running test silicon for today’s leading
edge technologies can be prohibitively expensive. UMC is
addressing these issues by enhancing its Silicon Shuttle
multi-project test wafer program for 2002. We have expanded the number of shuttle runs and technologies available and now run each shuttle on UMC’s hot-lot schedule
to greatly reduce cycle time. The 2002 Silicon Shuttle
program will introduce the unparalleled 0.13um L130 plat-
UMC’s Silicon Shuttle program will reduce your risk and
cost by verifying your advanced designs, prototypes, IPs
(digital/analog), cell libraries, and I/O’s in UMC silicon.
Silicon Shuttle Schedule for 2002
Jan
Process
8” wafer
M
Apr
G
M
May
M
G
Jun
Jul
M/*G
M
G
0.15um
0.13um
Mar
M
0.25um
0.18um
Feb
M
G
M
M
G
M
G
M
*G
M
G
M
G
M
Nov
M
G
G
G
M
G
M:Mixed-mode process with MMC/RFCMOS
0.25um, 1P5M, 2.5V/3.3V
0.18um, 1P6M, 1.8V/3.3V
0.13um, 1P8M, 1.2V/3.3V
*S: Special Shuttle
*G: Subcontract to Faraday
Starting from March 2002, the 0.13um Silicon Shuttle program will offer capability for the “Fusion” process, a L130 designer
option that enables High Speed and Low Leakage to be combined onto a single chip.
Customer database needs to be DRC-clean on the latest Calibre run-set.
Test-chip size is 5000umx5000um.
Customers must submit a completed GDS-II database, mask tooling form, and DRC report before the first business day of the
shuttle launch month. Please check with your sales representative for the exact dates.
For convenient application and prompt response for customers, UMC provide web-based on-line reservation and access to
Silicon Shuttle status.
For more information or to apply for the Silicon Shuttle program, please contact your UMC sales representative or e-mail
[email protected]
39
Dec
M/*G
G
0.15um
G:Generic (standard logic process)
0.25um, 1P5M, 2.5V/3.3V
0.18um, 1P6M, 1.8V/3.3V
0.15um, 1P7M, 1.5V/3.3V
0.13um, 1P8M, 1.2V/3.3V
90nm, 1P9M, 1.0V/2.5V
Oct
*S
90nm
12” wafer
Sep
G
G
G
Aug
M
IP Vendor Contact
Vendor
3DSP
Actel
AIL
ARC
ARM
Artisan
Dolphin Technology
eASIC
Enabling Technology
Faraday Technology
FTDPL
Genesys Testware
GlobalCAD
Infinite Technology
Innovative
inSilicon
Leda Systems
LSI Logic
MacroTech Research
Mentor Graphics
MIPS
Mosys
Mysticom
NEL
Nurlogic
Palmchip
Parthus
Sarnoff
Silicon Design Solutions
SliceX
SuperH
Synopsys
Tensilica
True Circuits
Virage Logic
Virtual IP Group
Virtual Silicon
Wipro Technologies
Website
www.3dsp.com
www.actel.com
Phone
949-435-0600
408-739-1010
email
[email protected]
[email protected]
www.ailabo.co.jp
www.arccores.com
www.arm.com
www.artisan.com
(81)3-3320-6251
408-437-3400
408-579-2200
408-734-5600
[email protected]
[email protected]
[email protected]
[email protected]
www.dolphin-ic.com
www.easic.com
www.enablingtechnology.com
www.faraday-usa.com
408-392-0012
408-264-7128
408-720-3310
408-935-0888
[email protected]
[email protected]
[email protected]
[email protected]
www.ftdpl.com.sg
www.genesystest.com
www.gcadinc.com
www.itc-usa.com
(65)744-9789
510-661-0791
408-588-9600
972-437-7800
[email protected]
[email protected]
[email protected]
[email protected]
www.isi96.com
www.insilicon.com
www.ledasystems.com
www.zsp.com
650-934-0170
408-894-1900
408-275-1416
408-433-6249
[email protected]
[email protected]
[email protected]
[email protected]
www.macrotechnic.com
www.mentor.com
www.mips.com
www.mosys.com
510-353-9666
408-451-5660
650-567-5000
408-731-1800
[email protected]
[email protected]
[email protected]
[email protected]
www.mysticom.com
www.nel.co.jp
www.nurlogic.com
www.palmchip.com
650-210-8080
(81)42-799-8537
858-455-7570
408-952-2000
[email protected]
[email protected]
[email protected]
[email protected]
www.parthus.com
www.sarnoff.com
www.siliconcompiler.com
www.slicex.com
408-514-2900
609-734-2000
408-586-9469
801-474-1447
[email protected]
[email protected]
[email protected]
[email protected]
www.superh.com
www.synopsys.com
www.tensilica.com
www.truecircuits.com
408-456-2034
650-584-5000
408-986-8000
650-691-2500
[email protected]
[email protected]
[email protected]
[email protected]
www.viragelogic.com
www.virtualipgroup.com
www.virtual-silicon.com
www.wipro.com
510-360-8000
408-733-3344
408-548-2700
408-249-6345
[email protected]
[email protected]
[email protected]
[email protected]
40
Location
Irvine, CA
Sunnyvale, CA
Tokyo, Japan
San Jose, CA
Los Gatos, CA
Sunnyvale, CA
San Jose, CA
San Jose, CA
Sunnyvale, CA
Santa Clara, CA
Singapore
Fremont, CA
Santa Clara, CA
Richardson, TX
Mountain View, CA
San Jose, CA
San Jose, CA
Milpitas, CA
Fremont, CA
San Jose, CA
Mountain View, CA
Sunnyvale, CA
Mountain View, CA
Kanagawa, Japan
San Diege, CA
San Jose, CA
San Jose, CA
Princeton, NJ
Milpitas, CA
Salt Lake City, UT
San Jose, CA
Mountain View, CA
Santa Clara, CA
Los Altos, CA
Fremont, CA
Sunnyvale, CA
Sunnyvale, CA
Santa Clara, CA