ATMEL ATC13

Features
• Comprehensive Library of Standard Logic and I/O Cells
• ATC13 Core and I/O Cells Designed to Operate with VDD = 1.2V ± 10% as Main Target
Operating Conditions
IO33 Pad Libraries Provide Interfaces to 3V Environment
Oscillators Provide Stable Clock Sources
Basic Analog Input/Output, Power, Ground and Multiplexer Cells Available
General-purpose Analog Cells Include Power Management Cells, Op Amps,
Comparators, ADCs and DACs, High-performance Analog Cells Can Be Developed on
Request
• Memory Cells Compiled to the Precise Requirements of the Design
• Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard-interface
and Application-specific Cells
•
•
•
•
Cell-based ASIC
ATC13
1. Description
The Atmel ATC13 Library is fabricated on a proprietary 0.13 micron, up to eight-layermetal CMOS process intended for use with a supply voltage of 1.2V ± 10%. Table 1-1
shows the range for which Atmel library cells have been characterized.
Table 1-1.
Summary
Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
DC Supply Voltage
Core and Standard I/Os
1.1
1.2
1.32
V
VDD3.3
DC Supply Voltage
3.3V Interface I/Os
3
3.3
3.6
V
VI
DC Input Voltage
0
VDD
V
VO
DC Output Voltage
0
VDD
V
TEMP
Operating Free Air
Temperature Range
-40
+85
°C
TSG
Storage Temperature
-60
+150
°C
Industrial
The Atmel cell libraries have been designed in order to be compatible with each other.
Simulation representations exist for three types of operating conditions. They correspond to the characterization conditions defined as follows:
• MIN conditions (industrial best case):
TJ = -40° C
VDD(cell) = 1.32V
Process = fast
• TYP conditions (industrial typical case):
TJ = +25° C
VDD(cell) = 1.2V
Process = typ
• MAX conditions (industrial worst case):
TJ = +100° C
VDD(cell) = 1.08V
Process = slow
6134AS–CASIC–08-Mar-05
Note: This is a summary document. A complete document
is not available at this time. For more information, please
contact your local Atmel sales office.
Delays to tristate are defined as delay to turn off (VGS < VT) of the driving devices.
Output pad drain current corresponds to the output current of the pad when the output
voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access
resistors (in and out of the die) are taken into account. In order to have accurate timing
estimates, all characterization has been run on electrical netlists extracted from the layout database.
2. Standard Cell Library, SClib
The Atmel Standard Cell Library, SClib, contains a comprehensive set of combinational
logic and storage cells. The SClib library includes cells which belong to the following
categories:
• Buffers and Gates
• Multiplexers
• Flip-flops
• Scan Flip-flops
• Latches
• Adders and Subtractors
2.1
Decoding the Cell Name
Table 2-1 shows the naming conventions for the cells in the SClib library. Each cell
name begins with either a two-, three-, or four-letter code that defines the type of cell.
This indicates the range of standard cells available.
Table 2-1.
Code
Description
Code
Description
AD
Adder
INVB
Balanced Inverter
AH
Half Adder
INVT
Inverting 3-State Buffer
AS
Adder/Subtractor
LA
D Latch
AN
AND Gate
MI
Inverting Multiplexer
AOI
AND-OR-Invert Gate
MX
Multiplexer
AON
AND-OR-AND-Invert Gates
ND
NAND Gate
AOR
AND-OR Gate
NR
NOR Gate
Bus Holder
OAI
OR-AND-Invert Gate
BUFB
Balanced Buffer
OAN
OR-AND-OR-Invert Gates
BUFF
Non-Inverting Buffer
BUFT
Non-Inverting 3-State Buffer
BH
CG
OR
ORA
OR Gate
OR-AND Gate
Carry Generator
SD
Multiplexed Scan D Flip-Flop
Clock Buffer
SE
Multiplexed Scan Enable D Flip-Flop
DE
D-Enabled Flip-Flop
SU
Subtractor
DF
D Flip-Flop
XN
Exclusive NOR Gate
Inverter
XR
Exclusive OR Gate
CLK2
INV0
2
Cell Codes
ATC13 Summary
6134AS–CASIC–08-Mar-05
ATC13 Summary
2.2
Cell Matrices
Table 2-2 and Table 2-3 show storage elements in the SClib library. Note that all storage
elements feature buffered clock inputs and buffered output.
Table 2-2.
Macro
Name
D Flip-Flops
Clear
•
Enabled
D Input
Single
Output
1 x Drive
2 x Drive
•
•
•
DFCRBx
•
•
•
DFCRQx
•
•
•
DFCRNx
•
•
•
DFNRBx
•
•
DFNRQx
•
•
•
•
•
•
•
•
•
•
•
•
DENRQx
•
•
•
•
DENRBx
•
•
•
DFBRBx
Set
DFPRBx
•
DEPRQx
•
•
DECRQx
Table 2-3.
Macro Name
•
•
Scan Flip-flops
Single
Output
Set
Clear
1xDrive
2xDrive
•
•
•
•
SDCRBx
•
•
•
SDCRNx
•
•
•
•
SDCRQx
•
•
•
•
SDNRBx
•
•
SDNRNx
•
•
•
SDNRQx
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SDBRBx
SDPRBx
•
•
SECRQx
SENRQx
SEPRQx
•
3
6134AS–CASIC–08-Mar-05
3. Input/Output Pad Cell Libraries, IO12lib and IO33lib
The Atmel Input/Output Cell Library IO12lib contains a comprehensive list of input, output, bi-directional and tristate cells. The ATC13 (1V) cell library includes a special set of
I/O cells, IO33lib, for interfacing with external 3.3V devices.
3.1
Voltage Levels
The IO12lib library is made up exclusively of low-voltage chip interface circuits powered
by a voltage level in the range of 1.1V to 1.32V. The library is compatible with SClib, 1.2volt standard cell library.
3.2
Power and Ground Pads
Designers are strongly encouraged to provide three kinds of power pairs for the IO12lib
library. These are “AC”, “DC” and core power pairs. AC power is used by the I/O to
switch its output from one state to the other. This switching generates noise in the AC
power buses on the chip. DC power is used by the I/O to maintain its output in a steady
state. The best noise performance is achieved when the DC power buses on the chip
are free of noise; you are encouraged to use separate power pairs for AC and DC power
to prevent most of the noise in the AC power buses from reaching the DC power buses.
You can use the same power pairs to supply both DC power to the I/Os and power to
the core without affecting noise performance.
Table 3-1.
VSS Power Pad Combinations
Core
Switching I/O
Quiet I/O
Vssi/gnd
VssAC
VssDC
Library Cell Name
Signal Name
pv12i00
VSS
pv12a00
VSS
•
pv12d00
VSS
•
pv12e00
VSS
•
pv12b00
VSS
•
pv12f00
VSS
pv12c00
VSS
Library Cell Name
Signal Name
pv12i12
VDD
pv12a12
VDD
•
pv12d12
VDD
•
pv12e12
VDD
•
pv12b12
VDD
•
pv12f12
VDD
pv12c12
VDD
•/ •
•
•
•/ •
•/ •
•
/•
Table 3-2.
VDD Power Pad Combinations
Core
Switching I/O
Quiet I/O
Vddi/vdd
VddAC
VddDC
•/ •
•
•
•/ •
•/ •
/•
4
•
ATC13 Summary
6134AS–CASIC–08-Mar-05
ATC13 Summary
3.3
Cell Matrices
Table 3-3.
CMOS Pads
CMOS Cell Name
3-state I/O
PC12B01
Drive Strength
Pad Sites Used
•
1x
1
PC12B02
•
2x
1
PC12B03
•
3x
1
PC12B04
•
4x
1
PC12B05
•
5x
1
3-state Output Only
PC12O01
•
1x
1
PC12O02
•
2x
1
PC12O03
•
3x
1
PC12O04
•
4x
1
PC12O05
•
5x
1
PC12T01
•
1x
1
PC12T02
•
2x
1
PC12T03
•
3x
1
PC12T04
•
4x
1
PC12T05
•
5x
1
3-state Output Only
Drive Strength
Pad Sites Used
Table 3-4.
TTL Pads
TTL Cell Name
3-state I/O
Output Only
PT12B01
•
2 mA
1
PT12B02
•
4 mA
1
PT12B03
•
8 mA
1
PT12O01
•
2 mA
1
PT12O02
•
4 mA
1
PT12O03
•
8 mA
1
PT12T01
•
2 mA
1
PT12T02
•
4 mA
1
PT12T03
•
8 mA
1
Table 3-5.
CMOS/TTL Input Only Pad
CMOS Cell Name
Input Levels
PC12D01
CMOS
PC12D11
CMOS
PC12D21
CMOS
Note:
Output Only
Schmitt Input
Level Shifter
Non-inverting
Inverting
•
1
•
•
Pad Sites Used
•
PC12D31
CMOS
•
•
All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device.
1
1
1
5
6134AS–CASIC–08-Mar-05
4. Basic Analog Cell Libraries, ANA12lib and ANA33lib
The Atmel basic analog library makes the following parts available:
• Multiplexer modules
– Multiplexers to minimize cross-talk (for use with high-impedance nodes).
– Multiplexers to minimize ON resistance.
• Analog input and output cells
• Analog power and ground cells
A special set of basic analog I/O cells, ANA33lib, is available for interfacing with external
3.3V devices.
5. General-purpose Analog Cell Library, GPlib
The General-purpose Analog Cell Library (GPlib) is composed of cells performing various analog functions.
Currently available are:
• Power Management Cells
• Op Amps
• Comparators
• ADCs
• DACs
• PLLs
Additional high-performance, complex analog cells can be developed according to specific customer requirements.
6
ATC13 Summary
6134AS–CASIC–08-Mar-05
ATC13 Summary
6. Oscillator Cell Library, Osc33lib
The Atmel Oscillator Library provides stable clock sources. It comprises five oscillators.
The Atmel two-pad oscillators are designed with the Pierce three-point oscillator
structure.
For the 32.768 kHz oscillator, the load capacitance must be between 6 pF and 12.5 pF.
For high-frequency oscillators, the load capacitance must be between 15 pF and 20 pF.
External capacitors must be added in order to obtain the correct load capacitance.
Clock output is high at off state (onosc = 0). The oscillators provide a bypass mode
(onosc = 0), clock = not (xin). Table 6-1 gives the available Osc33lib cells and their
major characteristics.
Table 6-1.
Oscillator Cells
Cell Name
Description
OSC33f33K
32.786 kHz crystal
OSC33f9M
4 - 9 MHz crystal oscillator
OSC33f16M
8 - 16 MHz crystal oscillator
OSC33f27M
10 - 27 MHz crystal oscillator
OSC33KLP
32.786 kHz uPower crystal oscillator (available in 1.2V)
7
6134AS–CASIC–08-Mar-05
7. Compiled CMOS Memories
The Atmel CMOS Memory Compiler Library enables users to compile memories for the
functions Single-port Synchronous RAM, Dual-port Synchronous RAM, Via Programmable Ultra-low-power (ULP) ROM and Two-port Synchronous Register File according to
their precise requirements. Memories compiled in this way can be instanced as often as
required in designs, alongside cells from other Atmel CBIC libraries.
7.1
Single-port Synchronous SRAM
Key features of the single-port synchronous SRAM are:
• High-density (HD) SRAM
• 400 MHz worst-case cycle time for 4 Kwords x 32 bits
• Zero quiescent current
• 3-state outputs
• Several aspect ratios for optimization of performance
• Separate data-in, data-out pins support a write-through feature
• Asynchronous write-through for testing interface shadow logic
• BIST interface
• Optional sub-word write capability
The single-port SRAM compiler is a high-density high-speed RAM compiler with quiescent current consumption equal to zero when the SRAM is not in a read or write mode.
The compiler is optimized for a power supply voltage range of 1.1V to 1.32V and can
operate at voltages as low as 0.9V. The SRAM instances can be built with several
aspect ratios for maximum area and performance optimization. Separate output (Q) and
input (D) pins allow a write-through cycle feature. An asynchronous write through mode
(AWT) allows testing of interface shadow logic. Built-in self-test (BIST) interface allows
for easy connection to most memBIST solutions. The special test modes allow externally bypassing read and write self-timed circuits and adjusting read and write margins.
The SRAM memory also includes a bit-write feature where selective write to each I/O
can be done. A maskable write enable signal is provided for each I/O for maximum
flexibility.
Table 7-1 gives the range of permitted single-port synchronous RAM configurations.
Table 7-1.
Parameter
Min
Max
Increment
Address Locations (words)
16
16K
4 x CM(1)
Word Size (Number of I/O bits)
2
256
1 bit
Total Bits in Core (Word Size x Address Locations)
32
512K
Note:
8
Configuration Range
1. CM = 4, 8, 16: Column Mux option
ATC13 Summary
6134AS–CASIC–08-Mar-05
ATC13 Summary
7.2
Dual-port Synchronous RAM
Key features of the dual-port synchronous RAM are:
• 300 MHz worst-case cycle time for 4 Kwords x 32 bits
• Zero quiescent current
• 3-state outputs
• Several aspect ratios for optimization of performance
• Separate data-in, data-out pins support a write-through feature
• Asynchronous write-through for testing interface shadow logic
• BIST interface
• Optional sub-word write capability
The dual-port synchronous RAM compiler is a high-density high-speed RAM compiler
with quiescent current consumption equal to zero when the RAM is not in a read or write
mode. The compiler is optimized for a power supply voltage range of 1.1V to 1.32V and
can operate at voltages as low as 0.9V. The DPRAM instances can be built with several
aspect ratios for maximum area and performance optimization. Separate output (Q) and
input (D) pins allow a write-through cycle feature. An asynchronous write-through mode
(AWT) allows testing of interface shadow logic through scan. Built-in self-test (BIST)
interface allows for easy connection to most memBIST solutions. The special test
modes allow externally bypassing read and write self-timed circuits and adjusting read
and write margins. The DPRAM compiler also includes a bit-write feature where selective write to each I/O can be done. A maskable write enable signal is provided for each
I/O for maximum flexibility.
Table 7-2 gives the range of permitted dual-port synchronous RAM configurations.
Table 7-2.
Parameter
Min
Max
Increment
Address Locations (words)
32
16K
4 x CM(1)
Word Size (Number of I/O bits)
2
256
1 bit
Total Bits in Core (Word Size x Address Locations)
64
512K
Note:
7.3
Configuration Range
1. CM = 4, 8, 16: Column Mux option
Via Programmable Ultra-low-power ROM
Key features of the via programmable ROM are:
• 1-port high-density low-power synchronous via-2 programmable ROM
• 76 MHz worst-case cycle time for 8K words x 8 bits
• Zero quiescent current
• 3-state outputs
• Several aspect ratios for optimization of performance
• Programming support
The via programmable ROM compiler is a high-density low-power synchronous ROM
compiler. The quiescent current consumption is zero when the ROM is not enabled. The
compiler is optimized for a power supply voltage range of 1.1V to 1.32V. The ROM
instances can be built with several aspect ratios for maximum area and performance
9
6134AS–CASIC–08-Mar-05
optimization. Built-in self-test (BIST) interface allows for easy connection to most memBIST solutions. The special test modes allow externally bypassing read self-timed
circuits and adjusting read margins. Within limits, the user has flexibility in specifying the
logical size of the ROM, including word size, number of address locations and column
mux.
Table 7-3 gives the range of permitted via programmable ROM configurations.
Table 7-3.
Configuration Range
Parameter
Min
Max
Increment
Address Locations (words)
256
64K
16 x CM(1)
4
64
2 bits
512
1M
Word Size (Number of I/O bits)
Total Bits in Core (Word Size x Address Locations)
Note:
7.4
1. CM = 16, 32, 64: Column Mux option
Two-port Synchronous Register File
Key features of the two-port synchronous register file are:
• 2-Port (1R, 1W) high-speed/low-power Register File
• 600 MHz worst-case cycle time for 32 words x 32 bits
• Zero quiescent current
• 3-state outputs
• Several aspect ratios for optimization of performance
• Separate data-in, data-out pins
• Optional sub-word write capability
The two-port synchronous register file compiler is a 2-port (one for write, one for read)
memory. This is a high-speed/low-power synchronous register file compiler. The quiescent current consumption is zero when all Register File inputs (including CLKA and
CLKB) are stable. The compiler is optimized for a power supply voltage range of 1.1V to
1.32V and can operate at voltages as low as 1.0V. The Register File instances can be
built with several aspect ratios for maximum area and performance optimization. Separate clocks (CLKA, CLKB), output (QB), and input (DA) pins allow independent read and
write cycles. Built-in self-test BIST interface allows for easy connection to most memBIST solutions. The memory also also includes a bit-write feature where selective write
to each I/O can be done. A maskable write enable signal is provided for each I/O for
maximum flexibility. Within limits, the user has flexibility in specifying the logical size of
the Register File, including word size, number of address locations and column mux.
Table 7-4 gives the range of permitted two-port synchronous register file configurations.
Table 7-4.
Configuration Range
Parameter
Min
Max
Increment
Address Locations (words)
8
1024
1 x CM(1)
Word Size (Number of I/O bits)
2
256
1 bit
Total Bits in Core (Word Size x Address Locations)
16
16K
Notes:
10
1. CM = 1, 2, 4: Column Mux option
ATC13 Summary
6134AS–CASIC–08-Mar-05
ATC13 Summary
8. Revision History
Table 8-1.
Revision History
Doc. Rev.
Date
Comments
6134AS
08-Mar-05
First issue.
Change Request Ref.
11
6134AS–CASIC–08-Mar-05
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