TESDC24V Taiwan Semiconductor Small Signal Product Bi-directional TVS Diode Array FEATURES - Meet IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact) 6 3 - Meet IEC61000-4-4 (EFT) rating. 40A (5/50ns) 5 - Protects one Bi-directional I/O line - Working Voltage : 24V 4 3 - Pb free version, RoHS compliant, and Halogn free MECHANICAL DATA SOD-323 - Case: SOD-323 small outline plastic package - High temperature soldering guaranteed: 260°C/10s - Weight: 48±5 mg (approximately) - Terminal : Matte tin plated, lead free, solderable per MIL-STD-202, method 208 guaranteed - Mounting position : Any APPLICATION - Cell Phone Handsets and Accessories - Notebooks, Desktops, and Servers - Keypads, Side Keys - Portable Instrumentation - Microprocessor Based Equipment - Peripherals MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS (TA=25℃ unless otherwise noted) PARAMETER IEC61000-4-2 ESD Voltage SYMBOL Air model Contact Model JESD22-A114-B ESD Voltage Per Human Body Model ESD Voltage VALUE ± 15 ±8 VESD (Note 1) PPP (Note 2) Junction Temperature Storage Temperature Range kV - Machine Model Peak Pulse Power UNIT 500 W TJ 150 o TSTG -55 ~ 150 o C C Note 1: Devide stressed with ten repetitive ESD pulses, per channel(I/O to GND) PARAMETER SYMBOL VALUE MIN MAX VRWM (Note 1) Reverse Stand-Off Voltage 24 V µA Reverse Breakdown Voltage IR = 1 mA V(BR) Reverse Leakage Current VR = 24 V IR 1 IPP = 5 A VC (Note 2) 40 Clamping Voltage Junction Capacitance IPP = 17 A VR = 0 V , f = 1.0 MHz 26.7 CJ UNIT V 52 50 (Typ.) V pF Note 1: Other voltages available upon request Note 2: Non-repetitive currect pulse 8/20μs exponential decay waveform according to IEC61000-4-5 Note 3: Per channel(I/O to GND unless otherwise specified) Document Number: DS_S1405025 Version: E14 TESDC24V Taiwan Semiconductor Small Signal Product RATINGS AND CHARACTERISTICS CURVES (TA=25℃ unless otherwise noted) Fig. 1 Admissible Power Dissipation Curve Fig. 2 Pulse Waveform 120 110 100 90 80 80 70 Percent of IPP Power Rating (%) 100 60 40 60 50 40 td = Ipp / 2 30 20 20 10 0 0 20 40 60 80 100 120 140 160 0 180 0 5 15 20 25 30 Fig. 4 Typical Junction Capacitance Fig. 3 Clamping Voltage VS. Peak Pulse Current 50 Normalized Capacitance (pF) 60 50 40 Clamping Voltage (V) 10 Time (us) Ambient Temperature (oC) 30 20 Waveform parameters: tr = 8 µs , td = 20 µs 10 40 30 20 10 f = 1.0 MHz 0 0 0 0 2 4 6 8 10 1 2 3 4 5 Reverse Voltage (V) Peak Pulse Current (A) Fig. 5 Non-Repetitive Peak Pulse Powe VS. Pulse Time Peak Pulse Power Ppp (KW) 10 1 0.1 0.01 0.1 1.0 10.0 100.0 1000.0 Pulse Duration (us) Document Number: DS_S1405025 Version: E14 TESDC24V Taiwan Semiconductor Small Signal Product ORDERING INFORMATION PART NO. MANUFACTURE PACKING CODE (Note 1) CODE RR TESDC24V GREEN COMPOUND PACKAGE PACKING MARKING SOD-323 3K / 7" Reel 2H CODE G Note 1: Indicator of manufacturing site for manufacture special control, if empty means no special control requirement EXAMPLE PREFERRED P/N PART NO. TESDC24V RRG TESDC24V TESDC24V-E0 RRG TESDC24V Document Number: DS_S1405025 MANUFACTURE CODE E0 PACKING CODE GREEN COMPOUND DESCRIPTION RR CODE G Green compound RR G Green compound Version: E14 TESDC24V Taiwan Semiconductor Small Signal Product DIMENSIONS B DIM. C A D E H Unit (mm) Min G Min Max A 1.15 1.40 0.045 0.055 B 2.30 2.70 0.091 0.106 C 0.25 0.45 0.010 0.018 D 1.60 1.80 0.063 0.071 E 0.80 1.00 0.031 0.039 F 0.05 0.17 0.002 0.007 0.475 REF G F Max Unit (inch) H - 0.10 0.19 REF - 0.004 SUGGESTED PAD LAYOUT Unit (mm) Unit (inch) Typ. Typ. A 0.63 0.025 B 0.83 0.033 C 1.60 0.063 D 2.85 0.112 DIM. APPLICATION INFROMATION - Designed to protect one data, I/O, or power supply line - Designed to protect sensitive electronics from damage or latch-up due to ESD - Designed to replace multilayer varistors (MLVs) in portable applications - Features large cross-sectional area junctions for conducting high transient currents - Offers superior electrical characteristics such as lower clamping voltage and no device degradation when compared to MLVs - The combination of small size and high ESD surge capability makes them ideal for use in portable applications CIRCUIT BOARD LAYOUT RECOMMENDATIONS Good circuit board layout is critical for the suppression of ESD induced transients - Place the ESD Protection Diode near the input terminals or connectors to restrict transient coupling - Minimize the path length between the ESD Protection Diode and the protected line - Minimize all conductive loops including power and ground loops - The ESD transient return path to ground should be kept as short as possible - Never run critical signals near board edges - Use ground planes whenever possible Document Number: DS_S1405025 Version: E14 TESDC24V Taiwan Semiconductor Small Signal Product Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC's terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or seling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale. Document Number: DS_S1405025 Version: E14