DS8867A 03

®
RT8867A
Advanced 4/3-Phase PWM Controller for CPU Core Power
General Description
Features
The RT8867A is an advanced 4/3-phase synchronous buck
controller with 3 integrated MOSFET drivers. It integrates
an 8-bit DAC that supports Intel VR11.x CPUs power
application.
z
12V Power Supply Voltage
z
4/3-Phase Power Conversion
Integrated 3 MOSFET Drivers with Internal
Bootstrap Diode
Dynamic Phase Control Capability
8-bit DAC Supports Intel VR11.x CPUs
Lossless RDS(ON) Current Sensing for Current Balance
Adjustable Frequency : 50kHz to 1MHz
Adjustable Over Current Protection
Adjustable Soft-Start
VR_RDY, VR_HOT and VR_SHDN Indications
Small 48-Lead WQFN Package
RoHS Compliant and Halogen Free
The IC adopts state-of-the-art dynamic phase control
capability by PS1/2/3 pins and achieves high efficiency
over a wide load range. It uses lossless RDS(ON) current
sensing to achieve phase current balance. Other features
include adjustable operating frequency, adjustable softstart, short circuit protection, adjustable over current
protection, over voltage protection, under voltage
protection, power good indication, VR_HOT indication and
VR_SHDN indication.
The RT8867A is available in a small footprint with WQFN48L 6x6 package.
Ordering Information
z
z
z
z
z
z
z
z
z
z
Applications
z
z
z
Desktop CPU Core Power
Middle/High End Graphic Cards
Low Voltage, High Current DC/ DC Converters
RT8867A
Package Type
QW : WQFN-48L 6x6 (W-Type)
(Exposed Pad-Option 1)
Pin Configurations
(TOP VIEW)
VR_RDY
VRSEL
FBRTN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
BOOT1
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Note :
48 47 46 45 44 43 42 41 40 39 38 37
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT8867AZQW : Product Number
RT8867A
ZQW
YMDNN
YMDNN : Date Code
PS2
SS
EN
DAC
EAP
FB
COMP
CSP
CSN
IMAX
PS3/VR_SHDN
PS1
1
36
2
35
3
34
4
33
5
32
6
7
31
GND
30
8
29
9
28
49
10
27
11
26
12
25
UGATE1
PHASE1
LGATE1
VCC12A
BOOT2
UGATE2
PHASE2
LGATE2
VCC12B
LGATE3
PHASE3
UGATE3
13 14 15 16 17 18 19 20 21 22 23 24
ISEN4
ISEN3
ISEN2
ISEN1
RT
VCC5
TB
VOUT
TM
VR_HOT
PWM4
BOOT3
Richtek products are :
WQFN-48L 6x6
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8867A-03 July 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
www.richtek.com
2
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
C32
C31
C28
Q7
Q8
VIN
4.5V to 13.2V
R36
C27
PH3
C22
R39
C21
CSN+ PH4
R42
L4
CSN+
R42
L3
C19
R19
C25
R34
PWM
GND
VCC
R29
12V
TM
BOOT3
VR_HOT
PWM4
19
TB
17 RT
23
13 ISEN4
26 PHASE3
27
LGATE3
14 ISEN3
25 UGATE3
24
22
3 EN
8 CSP
1 PS2
9 CSN
11 PS3/
VR_SHDN
12 PS1
21
GND
R6
R4
R15
R16
C16
C5
C13
R10
C10
R8
C15
C9
R9
R7
C4
C2
49 (Exposed Pad)
VCC12B 28
VCC12A 33
FBRTN 46
SS 2
COMP 7
VOUT 20
FB 6
ISEN2 15
PHASE2 30
LGATE2 29
BOOT2 32
UGATE2 31
R5
R3
R2
C1
VVR_RDY
VTT
R35
38 to 45
47
VRSEL
VR_RDY 48
VID[7:0]
EAP 5
PHASE1 35
34
LGATE1
16
ISEN1
DAC 4
BOOT1 37
UGATE1 36
RT8867A
10
18 VCC5
IMAX
R1
C26
RRT
C24
R25
C18
RPS2
C17
RPS1
NTC2
C23
R27
C20
R24
LGATE
RT9619
PHASE
UGATE
BOOT
R28
R17
C5
VCC_SNS
VVR_HOT
VTT
R21
CSN+
R23
NTC1
R20
Chip Enable
R26
R33
R32
R31
R30
R22
Q9
VIN
4.5V to 13.2V
PH4
PH3
PH2
PH1
VVR_SHDN
VSHDN
R18
VCC5
R11
12V
C11 R12
Q4
Q3
VIN
4.5V to 13.2V
Q2
Q1
VIN
4.5V to 13.2V
C8
R37
C14
C33
C6
C7
L2
L1
R38
C3
C12
CSN+
R41
CSN+
R40
C30
C29
R13
VCC_SNS
LOAD
VSS_SNS
R14
C34
VCORE
RT8867A
Typical Application Circuit
is a registered trademark of Richtek Technology Corporation.
DS8867A-03 July 2014
RT8867A
Table 1. VR11.1 VID Code Table
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0
0
0
0
0
0
0
0
OFF
0
0
1
0
0
0
1
1
1.39375
0
0
0
0
0
0
0
1
OFF
0
0
1
0
0
1
0
0
1.38750
0
0
0
0
0
0
1
0
1.60000
0
0
1
0
0
1
0
1
1.38125
0
0
0
0
0
0
1
1
1.59375
0
0
1
0
0
1
1
0
1.37500
0
0
0
0
0
1
0
0
1.58750
0
0
1
0
0
1
1
1
1.36875
0
0
0
0
0
1
0
1
1.58125
0
0
1
0
1
0
0
0
1.36250
0
0
0
0
0
1
1
0
1.57500
0
0
1
0
1
0
0
1
1.35625
0
0
0
0
0
1
1
1
1.56875
0
0
1
0
1
0
1
0
1.35000
0
0
0
0
1
0
0
0
1.56250
0
0
1
0
1
0
1
1
1.34375
0
0
0
0
1
0
0
1
1.55625
0
0
1
0
1
1
0
0
1.33750
0
0
0
0
1
0
1
0
1.55000
0
0
1
0
1
1
0
1
1.33125
0
0
0
0
1
0
1
1
1.54375
0
0
1
0
1
1
1
0
1.32500
0
0
0
0
1
1
0
0
1.53750
0
0
1
0
1
1
1
1
1.31875
0
0
0
0
1
1
0
1
1.53125
0
0
1
1
0
0
0
0
1.31250
0
0
0
0
1
1
1
0
1.52500
0
0
1
1
0
0
0
1
1.30625
0
0
0
0
1
1
1
1
1.51875
0
0
1
1
0
0
1
0
1.30000
0
0
0
1
0
0
0
0
1.51250
0
0
1
1
0
0
1
1
1.29375
0
0
0
1
0
0
0
1
1.50625
0
0
1
1
0
1
0
0
1.28750
0
0
0
1
0
0
1
0
1.50000
0
0
1
1
0
1
0
1
1.28125
0
0
0
1
0
0
1
1
1.49375
0
0
1
1
0
1
1
0
1.27500
0
0
0
1
0
1
0
0
1.48750
0
0
1
1
0
1
1
1
1.26875
0
0
0
1
0
1
0
1
1.48125
0
0
1
1
1
0
0
0
1.26250
0
0
0
1
0
1
1
0
1.47500
0
0
1
1
1
0
0
1
1.25625
0
0
0
1
0
1
1
1
1.46875
0
0
1
1
1
0
1
0
1.25000
0
0
0
1
1
0
0
0
1.46250
0
0
1
1
1
0
1
1
1.24375
0
0
0
1
1
0
0
1
1.45625
0
0
1
1
1
1
0
0
1.23750
0
0
0
1
1
0
1
0
1.45000
0
0
1
1
1
1
0
1
1.23125
0
0
0
1
1
0
1
1
1.44375
0
0
1
1
1
1
1
0
1.22500
0
0
0
1
1
1
0
0
1.43750
0
0
1
1
1
1
1
1
1.21875
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
0
0
0
1.21250
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
0
0
0
1
1.20625
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
0
0
1
0
1.20000
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
0
0
1
1
1.19375
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
0
1
0
0
1.18750
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
0
1
0
1
1.18125
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8867A-03 July 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8867A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0
1
0
0
0
1
1
0
1.17500
0
1
1
0
1
0
1
0
0.95000
0
1
0
0
0
1
1
1
1.16875
0
1
1
0
1
0
1
1
0.94375
0
1
0
0
1
0
0
0
1.16250
0
1
1
0
1
1
0
0
0.93750
0
1
0
0
1
0
0
1
1.15625
0
1
1
0
1
1
0
1
0.93125
0
1
0
0
1
0
1
0
1.15000
0
1
1
0
1
1
1
0
0.92500
0
1
0
0
1
0
1
1
1.14375
0
1
1
0
1
1
1
1
0.91875
0
1
0
0
1
1
0
0
1.13750
0
1
1
1
0
0
0
0
0.91250
0
1
0
0
1
1
0
1
1.13125
0
1
1
1
0
0
0
1
0.90625
0
1
0
0
1
1
1
0
1.12500
0
1
1
1
0
0
1
0
0.90000
0
1
0
0
1
1
1
1
1.11875
0
1
1
1
0
0
1
1
0.89375
0
1
0
1
0
0
0
0
1.11250
0
1
1
1
0
1
0
0
0.88750
0
1
0
1
0
0
0
1
1.10625
0
1
1
1
0
1
0
1
0.88125
0
1
0
1
0
0
1
0
1.10000
0
1
1
1
0
1
1
0
0.87500
0
1
0
1
0
0
1
1
1.09375
0
1
1
1
0
1
1
1
0.86875
0
1
0
1
0
1
0
0
1.08750
0
1
1
1
1
0
0
0
0.86250
0
1
0
1
0
1
0
1
1.08125
0
1
1
1
1
0
0
1
0.85625
0
1
0
1
0
1
1
0
1.07500
0
1
1
1
1
0
1
0
0.85000
0
1
0
1
0
1
1
1
1.06875
0
1
1
1
1
0
1
1
0.84375
0
1
0
1
1
0
0
0
1.06250
0
1
1
1
1
1
0
0
0.83750
0
1
0
1
1
0
0
1
1.05625
0
1
1
1
1
1
0
1
0.83125
0
1
0
1
1
0
1
0
1.05000
0
1
1
1
1
1
1
0
0.82500
0
1
0
1
1
0
1
1
1.04375
0
1
1
1
1
1
1
1
0.81875
0
1
0
1
1
1
0
0
1.03750
1
0
0
0
0
0
0
0
0.81250
0
1
0
1
1
1
0
1
1.03125
1
0
0
0
0
0
0
1
0.80625
0
1
0
1
1
1
1
0
1.02500
1
0
0
0
0
0
1
0
0.80000
0
1
0
1
1
1
1
1
1.01875
1
0
0
0
0
0
1
1
0.79375
0
1
1
0
0
0
0
0
1.01250
1
0
0
0
0
1
0
0
0.78750
0
1
1
0
0
0
0
1
1.00625
1
0
0
0
0
1
0
1
0.78125
0
1
1
0
0
0
1
0
1.00000
1
0
0
0
0
1
1
0
0.77500
0
1
1
0
0
0
1
1
0.99375
1
0
0
0
0
1
1
1
0.76875
0
1
1
0
0
1
0
0
0.98750
1
0
0
0
1
0
0
0
0.76250
0
1
1
0
0
1
0
1
0.98125
1
0
0
0
1
0
0
1
0.75625
0
1
1
0
0
1
1
0
0.97500
1
0
0
0
1
0
1
0
0.75000
0
1
1
0
0
1
1
1
0.96875
1
0
0
0
1
0
1
1
0.74375
0
1
1
0
1
0
0
0
0.96250
1
0
0
0
1
1
0
0
0.73750
0
1
1
0
1
0
0
1
0.95625
1
0
0
0
1
1
0
1
0.73125
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
4
is a registered trademark of Richtek Technology Corporation.
DS8867A-03 July 2014
RT8867A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
1
0
0
0
1
1
1
0
0.72500
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
1
1
1
0.71875
1
1
1
1
1
1
1
0
OFF
1
0
0
1
0
0
0
0
0.71250
1
1
1
1
1
1
1
1
OFF
1
0
0
1
0
0
0
1
0.70625
1
0
0
1
0
0
1
0
0.70000
1
0
0
1
0
0
1
1
0.69375
1
0
0
1
0
1
0
0
0.68750
1
0
0
1
0
1
0
1
0.68125
1
0
0
1
0
1
1
0
0.67500
1
0
0
1
0
1
1
1
0.66875
1
0
0
1
1
0
0
0
0.66250
1
0
0
1
1
0
0
1
0.65625
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
1
1
0
0
0.63750
1
0
0
1
1
1
0
1
0.63125
1
0
0
1
1
1
1
0
0.62500
1
0
0
1
1
1
1
1
0.61875
1
0
1
0
0
0
0
0
0.61250
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
1
0
1
0
0
0
1
1
0.59375
1
0
1
0
0
1
0
0
0.58750
1
0
1
0
0
1
0
1
0.58125
1
0
1
0
0
1
1
0
0.57500
1
0
1
0
0
1
1
1
0.56875
1
0
1
0
1
0
0
0
0.56250
1
0
1
0
1
0
0
1
0.55625
1
0
1
0
1
0
1
0
0.55000
1
0
1
0
1
0
1
1
0.54375
1
0
1
0
1
1
0
0
0.53750
1
0
1
0
1
1
0
1
0.53125
1
0
1
0
1
1
1
0
0.52500
1
0
1
0
1
1
1
1
0.51875
1
0
1
1
0
0
0
0
0.51250
1
0
1
1
0
0
0
1
0.50625
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8867A-03 July 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8867A
Functional Pin Description
Pin No.
Pin Name
1
PS2
2
SS
3
EN
4
DAC
5
EAP
6
FB
7
COMP
Pin Function
Dynamic Phase Control Threshold Input 2. Connect this pin to GND by a
resistor to set dynamic phase control threshold.
Soft-Start Ramp Slope Set Pin. Connect this pin to FBRTN by a capacitor
to adjust soft-start slew rate.
Chip Enable Pin. Pull this pin higher than 0.8V to enable the PWM
controller.
DAC Output Pin. Connect a resistor from this pin to EAP pin for setting
the load line slope.
Non-inverting Input of Error-Amplifier Pin. Connect a resistor from this pin
to DAC pin to set the load line slope.
Inverting Input of Error Amplifier Pin.
Compensation Pin. Output of error amplifier and input of PWM
comparator.
Input of Current Sensing Amplifier. The sensed current is for droop
control and over current protection.
Output Current Indication. Connect a resistor from this pin to GND to set
the over current protection threshold.
8, 9
CSP, CSN
10
IMAX
11
PS3/VR_SHDN
Multi Function Pin. Dynamic phase control threshold input 3 & VR_SHDN
indication. Connect this pin to a resistive voltage divider to set synamic
phase control threshold.
12
PS1
Dynamic Phase Control Threshold Input 1. Connect this pin to GND by a
resistor to set dynamic phase control threshold.
ISN4, ISN3, ISN2,
ISN1
Phase Current Sense Pins for Phase 4, Phase 3, Phase 2 and Phase 1.
Per phase current signal is sensed via the voltage across low side
MOSFETs R DS(ON) for current balance.
17
RT
Switching Frequency Set Pin. Connect this pin to GND by a resistor to
adjust switching frequency.
18
VCC5
19
TB
20
VOUT
21
TM
22
VR_HOT
23
PWM4
PWM Output for Phase 4.
24, 32, 37
BOOT3, BOOT2,
BOOT1
Bootstrap Power Pins for Phase 3, Phase 2 and Phase 1. This pin
powers the high side MOSFETs drivers. Connect this pin to the junction
of the bootstrap capacitor with the cathode of the bootstrap diode.
25, 31, 36
UGATE3,
UGATE2,
UGATE1
Upper Gate Drivers for Phase 3, Phase 2 and Phase 1. This pin drives
the gate of the high side MOSFETs.
13, 14, 15, 16
Internal 5V Regulator Output.
Transient Boost Pin. This pin along with the VOUT pin sets the transient
boost function.
Positive Voltage Sensing Pin. This pin is the positive node of the
differential voltage sensing and along with TB pin sets the transient boost
function.
Thermal Monitoring Input Pin. Connect a resistive voltage divider with
NTC to detect temperature.
Thermal Monitoring Output Pin. Connect a resistor to VTT for VR_HOT
signal assertion.
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is a registered trademark of Richtek Technology Corporation.
DS8867A-03 July 2014
RT8867A
Pin No.
26, 30, 35
27, 29, 34
Pin Name
Pin Function
PHASE3,
PHASE2,
PHASE1
LGATE3,
LGATE2, LGATE1
Switch Nodes of High Side Driver 3, Driver2 and Driver1. Connect this
pin to high side MOSFETs sources together with the low side MOSFETs
drains and inductor.
Lower Gate Drivers for Phase 3, Phase 2 and Phase 1. This pin drives
the gate of low side MOSFETs.
28
VCC12B
33
VCC12A
38 to 45
VID7 to VID0
46
FBRTN
47
VRSEL
48
VR_RDY
49
(Exposed pad)
GND
Supply Input Pin. This pin supplies current for phase 2 and phase 3 gate
drivers.
Supply Input Pin. This pin supplies current for phase 1 gate driver and
control circuits.
Voltage Identification Input for DAC.
Return Ground Pin. This pin is negative node of the differential remote
voltage sensing.
Load Line Adjustment Enable Pin. Connect this pin to VTT to disable load
line adjustment function or connect this pin to GND to enable load line
adjustment function.
VR Ready Indication.
The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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7
RT8867A
SS
VR_RDY
DAC
COMP
SoftStart
Table Generator
EAP
FB
+
EA
VEAP +
390mV
POR
PWM1
+
-
VCC12A
VCC5
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
EN
FBRTN
Function Block Diagram
5V
Regulator
BOOT1
UGATE1
MOSFET
Driver
OVP
+
Load Line
Adjustment
CSN
-
CSP
VOUT
+
1.2V
PHASE2
LGATE2
- ISEN3
PWM3
+
S/H
Current
Balance
- ISEN2
BOOT3
UGATE3
MOSFET
Driver
12k
PHASE3
LGATE3
12k
PWM4
+
PWM4
-
GND
S/H
- ISEN1
S/H
+
-
Modulator
Waveform
Generator
RT
PS1
PS2
PS3/VR_SHDN
VDC
VCC12B
-
+
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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8
12k
12k
S/H
+
ISEN1
MOSFET
Driver
IX
- ISEN4
+
ISEN2
BOOT2
UGATE2
Transient
Response
Enhancement
+
ISEN3
-
PWM2
+
-
TB
ISEN4
OCP
Thermal
Monitor
VR_HOT
VRSEL
UVP
+
TM
IMAX
4 x IX
-
PHASE1
LGATE1
12k
+
VEAP 300mV
12k
is a registered trademark of Richtek Technology Corporation.
DS8867A-03 July 2014
RT8867A
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
z
(Note 1)
Supply Input Voltage (VCC12A, VCC12B) ------------------------------------------------------ −0.3V to 15V
BOOTx to GND
DC --------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 20ns ---------------------------------------------------------------------------------------------------- −0.3V to 42V
PHASEx to GND
DC --------------------------------------------------------------------------------------------------------- −2V to 15V
< 20ns ---------------------------------------------------------------------------------------------------- −5V to 30V
UGATEx to GND --------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- (VPHASE − 5V) to (VBOOT + 5V)
LGATEx to GND --------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- (GND − 5V) to (VCC + 5V)
Power Dissipation, PD @ TA = 25°C
WQFN−48L 6x6 ---------------------------------------------------------------------------------------- 2.857W
Package Thermal Resistance (Note 2)
WQFN−48L 6x6, θJA ---------------------------------------------------------------------------------- 35°C/W
WQFN−48L 6x6, θJC ---------------------------------------------------------------------------------- 6°C/W
Junction Temperature --------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------- 260°C
Storage Temperature Range ------------------------------------------------------------------------ −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) -------------------------------------------------------------------------- 2kV
Recommended Operating Conditions
z
z
z
(Note 4)
Supply Input Voltage (VCC12A, VCC12B) ------------------------------------------------------ 10.8V to 13.2V
Junction Temperature Range ------------------------------------------------------------------------ −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------ −40°C to 85°C
Electrical Characteristics
(VCC12x = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
6
--
mA
Supply Input
Supply Current
ICC12
VCC5 Supply Voltage
VCC5
ILOAD = 10mA
4.9
5
5.1
V
VCC5 Output Sourcing
Soft-Start Current
IVCC5
ISS1
VR_RDY = Low
10
68
-80
-92
mA
μA
VID Change Current
ISS2
VR_RDY = High
135
160
185
μA
9
10
11
μA
VR_HOT Threshold Level
41
43
48
%VCC5
VR_HOT Hysteresis
--
7
--
%VCC5
VR_SHDN Threshold Level
30
32
34
%VCC5
Transient Boost Sinking
Current
Thermal Management
ITB
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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9
RT8867A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Power On Reset
VCC12 Rising Threshold
VCC12RTH
VCC12 Rising
9.2
9.6
10
V
VCC12 Hysteresis
VCC12HYS
VCC12 Falling
--
0.9
--
V
VCC5 Rising Threshold
VCC5RTH
VCC5 Rising
4.4
4.6
4.8
V
VCC5 Hysteresis
VCC5HYS
VCC5 Falling
--
0.4
--
V
0.8
--
--
--
--
0.4
270
300
330
kHz
50
--
1000
kHz
3.5
4
4.5
V
Enable Control
EN Input Threshold
Voltage
Logic-High VIH
Logic-Low
VIL
V
Oscillator
Switching Frequency
f OSC
RRT = 24kΩ, for 4 Phase Operation
Adjustable Frequency Range
Ramp Amplitude
(Note 5)
Maximum Duty
RT Pin Voltage
3 Phase Operation
(Note 5)
61
66
71
4 Phase Operation
(Note 5)
70
75
80
1.55
1.6
1.65
V
1V to 1.6V
−0.5
--
0.5
%
0.8V to 1V
−8
--
8
mV
−10
--
10
mV
0.8
--
--
--
--
0.4
VRT
%
Reference Voltage and DAC
DAC Accuracy
0.5V to 0.8V
DAC Input Threshold
Voltage (VID0 to
VID7, VRSEL)
Logic-High VIH
Logic-Low
VIL
V
Error Amplifier
DC Gain
ADC
No Load
--
80
--
dB
Gain Bandwidth
GBW
CLOAD = 10pF
--
10
--
MHz
Slew Rate
SR
CLOAD = 10pF
10
--
--
V/μs
Output Voltage Range
VCOMP
0.5
--
3.6
V
Maximum Current
I EA_SLEW
300
--
--
μA
Maximum Current
I GMMAX
100
--
--
μA
Input Offset Voltage
VOSCS
−1
0
1
mV
Current Sense
IMAX Current Mirror Accuracy
IMAX / IAVG, 4 Phase Operation
368
400
432
%
Droop Current Mirror Accuracy
IDRP / I AVG, 4 Phase Operation
368
400
432
%
--
2
4
Ω
--
1
2
Ω
--
2
4
Ω
--
0.8
1.6
Ω
Gate Driver
UGATE Drive Source
RUGATEsr
UGATE Drive Sink
RUGATEsk
LGATE Drive Source
RLGATEsr
BOOT − PHASE = 8V
250mA Source Current
BOOT − PHASE = 8V
250mA Sink Current
VLGATE = 8V
LGATE Drive Sink
RLGATEsk
250mA Sink Current
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is a registered trademark of Richtek Technology Corporation.
DS8867A-03 July 2014
RT8867A
Parameter
Protection
Total Current Protection
Threshold
Over Voltage Threshold
Under Voltage Threshold
Over Temperature
Protection Threshold
Over Temperature
Protection Hysteresis
Output Pin Capability
VR_HOT Sinking
Capability
VR_RDY Sinking
Capability
VR_SHDN Sinking
Capability
Symbol
Test Conditions
VIMAX
Typ
Max
Unit
1.1
1.2
1.3
V
390
430
mV
−300 −250
mV
145
150
175
°C
--
20
--
°C
VOVP
VFB − VEAP
350
VUVP
VFB − VEAP
−380
(Note 5)
VVR_HOT
I VR_HOT = 4mA
--
0.05
0.2
V
VVR_RDY
I VR_RDY = 4mA
--
0.05
0.2
V
--
0.05
0.2
V
9.2
10
10.8
μA
VVR_SHDN I VR_SHDN = 4mA
PS1/PS2 Sourcing Current IPS1, I PS2
Reduce Operating Phase
Number Threshold
Hysteresis
Min
VPS1_hys
2 Phase Operating Reduce to 1 Phase
--
30
--
%VPS1
VPS2_hys
3 Phase Operating Reduce to 2 Phase
--
20
--
%VPS2
VPS3_hys
4 Phase Operating Reduce to 3 Phase
--
15
--
% VPS3/5
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by Design.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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11
RT8867A
Typical Operating Characteristics
Power Off from EN
Power On from EN
VOUT
(1V/Div)
VOUT
(1V/Div)
EN
(1V/Div)
VR_RDY
(2V/Div)
EN
(1V/Div)
VR_RDY
(2V/Div)
UGATE1
(20V/Div)
VID = 1.4V, ILOAD = 5A
UGATE1
(20V/Div)
Time (1ms/Div)
Time (400μs/Div)
Dynamic VID Up
Dynamic VID Down
VOUT
(500mV/Div)
VOUT
(500mV/Div)
VID1
(1V/Div)
VID1
(1V/Div)
VID from 1.4V down to 0.8V, ILOAD = 85A
Time (100μs/Div)
Time (100μs/Div)
Load Transient Response
Load Transient Response
VOUT
(40mV/Div)
VOUT
(40mV/Div)
VID from 0.8V up to 1.4V, ILOAD = 85A
I LOAD
1.3V
100A
I LOAD
35A
VID = 1.4V, fLOAD = 200Hz, ILOAD = 35A to 100A
Time (100μs/Div)
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12
VID = 1.4V, ILOAD = 5A
1.3V
100A
35A
VID = 1.4V, fLOAD = 200Hz, ILOAD = 100A to 35A
Time (100μs/Div)
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DS8867A-03 July 2014
RT8867A
Over Current Protection
Over Voltage Protection
VOUT
(1V/Div)
VR_RDY
(1V/Div)
FB
(1V/Div)
UGATE1
(20V/Div)
VR_RDY
(1V/Div)
UGATE1
(20V/Div)
I LOAD
(100A/Div)
LGATE1
(10V/Div)
Time (100μs/Div)
Time (40μs/Div)
Thermal Monitoring
Current Monitor Output Voltage (V)1
Current Monitor Output Voltage vs. Load Current
1.0
0.8
TM
(2V/Div)
0.6
VR_HOT
(1V/Div)
0.4
0.2
TM from 2V sweep to 5V, ILOAD = 0A
0.0
0
20
40
60
80
100
Time (400μs/Div)
Load Current (A)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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13
RT8867A
Application Information
The RT8867A is an advanced 4/3 phase synchronous buck
controller with 3 integrated MOSFET drivers. It integrates
an 8-bit DAC that supports Intel VR11.x VID table.
Supply Voltage and POR
+
9.6V
CMP
-
POR
VCC5
+
4.6V
CMP
POR : Power On Reset
-
Figure 1. Circuit for Power Ready Detection
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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14
The switching frequency of the RT8867A is set by an
external resistor connected from the RT pin to GND. The
frequency follows the graph in Figure 2.
Switching Frequency (kHz)1
1200
There are three supply voltage pins built in the RT8867A :
VCC12A/VCC12B and VCC5. VCC12A/VCC12B are
power input pins that receive an external 12V voltage for
the embedded driver logic operation. VCC5 is a power
output pin which is the output of an internal 5V LDO
regulator. The 5V LDO regulator regulates VCC12A to
generate a 5V voltage source for internal gate logic and
external circuit biasing, e.g., OCP biasing. Since the VCC5
voltage is regulated, the variation of VCC5 (2%) will be
much smaller than Platform ATX 5V (5% to 7%). The
maximum supply current of VCC5 is 10mA, which is
designed only for controller circuit biasing. The
recommended configuration of the RT8867A supply
voltages is as follows: Platform ATX 12V to the VCC12A/
VCC12B pins, and decoupling capacitors on the VCC12A/
VCC12B and VCC5 pins (minimum 0.1μF). The
initialization of the RT8867A requires all the voltage on
VCC12A/VCC12B and VCC5 to be ready. Since VCC5 is
regulated internally from VCC12A, the VCC5 voltage will
be ready (>4.6V) after VCC12A reaches about 7V, so there
is no power sequence problem between VCC12A/VCC12B
and VCC5. After VCC5 > 4.6V and VCC12A/VCC12B >
9.6V, the internal Power-On-Reset (POR) signal goes high.
This POR signal indicates the power supply voltages are
all ready. When POR = high and EN = high, the RT8867A
initiates soft-start sequence. When POR = low, the
RT8867A will try to turn off both high side and low side
MOSFETs to prevent catastrophic failure.
VCC12A/
VCC12B
Switching Frequency
1000
800
600
400
200
0
0
20
40
60
80
RRT (k Ω)
Figure 2. Switching Frequency vs. RRT Resistance
Soft-Start
The VOUT soft-start slew rate is set by a capacitor from
the SS pin to FBRTN. Before power on reset (POR =
low), the SS pin is held at GND. After power on reset
(POR = high, EN = high) and an extra delay of 1600μs
(T1), the controller initiates ramping up. VOUT will always
trace VEAP during normal operation of the RT8867A, where
VEAP is the positive input of the error amplifier, which can
be described as VEAP = VDAC − VDROOP. (The definition of
VDROOP will be described later in the Load Line section).
The first ramping up duration of VOUT (T2) ramps VOUT to
VBOOT.
After VOUT ramps to VBOOT, the RT8867A stays in this
state for 800μs (T3), waiting for a valid VID code sent by
the CPU. After receiving the valid VID code, VOUT continues
ramping up or down to the voltage specified by VID code.
After VOUT ramps to VEAP = VDAC − VDROOP, the RT8867A
stays in this state for 1600μs (T5) and then asserts
VR_RDY = high. The ramping slew rate of T2 and T4 is
controlled by the external capacitor connected to SS pin.
The voltage of the SS pin will always be VEAP + 0.7V,
where the mentioned 0.7V is the typical turn-on threshold
of an internal power switch. Before VR_RDY = high, the
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DS8867A-03 July 2014
RT8867A
slew rate of VEAP is limited to 80μA/CSS. When VR_RDY
= high, the slew rate of VEAP is limited to 160μA/CSS,
which is 2 times faster than the soft-start slew rate for
dynamic VID feature. The soft-start waveform is shown in
Figure 4.
C2
C3
R3
C1
R2
R1
VOUT
FB
COMP
Soft-Start Current (ISS)
is Limited and Variant
Soft-Start
Circuit
EA
+
DAC
EAP
(Error AMP Positive Input)
ISS
CSS
IX
(Output Current Sensed Signal)
DAC
Figure 3. Circuit for Soft-Start and Voltage Control Loop
VCC12
4.6V
9.6V
VEN
SS
VOUT
VBOOT
VR_RDY
T1
T2
T3
T4
T5
Figure 4. Soft-Start Waveforms
T1 is the delay time from power on reset state to the
beginning of VOUT rising. T2 is the soft-start time from
VOUT = 0 to VOUT = VBOOT. T3 is the dwelling time for VOUT
= VBOOT. T4 is the soft-start time form VOUT = VBOOT to
VOUT = VDAC.
T5 is the VR_RDY delay time.
T1 = 1600μs + 0.7V x CSS /80μA.
T2 = VBOOT x CSS/80μA.
T3 ≈ 800μs.
T4 ≈ |VDAC − VBOOT| x CSS/80μA.
T5 ≈ 1600μs.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8867A-03 July 2014
The RT8867A can accept VID input changing while the
controller is running. This allows the output voltage (VOUT)
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID On-The-Fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, VOUT should follow VDAC which is a staircase
waveform, but in real application, the bandwidth of the
converter is finite while the staircase waveform needs
infinite bandwidth to follow. Thus, undesired VOUT overshoot
(when VDAC changes up) or undershoot (when VDAC
changes down) is often observed in this type of design.
However, for the RT8867A, as mentioned before in the
soft-start section, VDAC slew rate is limited by ISS2/CSS
EAP
RDROOP
VCC5
Dynamic VID
when VR_RDY = high. This slew rate limiter works as a
low-pass filter of VDAC and makes the bandwidth of VDAC
waveform finite. By smoothening the VDAC staircase
waveform, VOUT will no longer overshoot or undershoot.
On the other hand, CSS will increase the settling time of
VOUT during VID OTF. In most cases, a 5nF to 30nF
ceramic capacitor will be suitable for CSS.
Output Voltage Differential Sensing
The RT8867A uses a high gain low offset error amplifier
for differential sensing. The CPU voltage is sensed between
the FB and FBRTN pins. A resistor (RFB) connects FB pin
with the positive remote sense pin of the CPU (VCC_SNS),
while the FBRTN pin connects directly to the negative
remote sense pin of the CPU (VSS_SNS). The error amplifier
compares VEAP (= VDAC − VDROOP) with the VFB to regulate
the output voltage.
Transient Boost
In steady state, the voltage of VOUT is controlled to be
very close to VEAP, however a load step transient from
light load to heavy load could cause VOUT to be lower than
VEAP by several tens of mV. In conventional buck converter
design (without non-linear control) for CPU VR application,
due to limited control bandwidth, it is hard for the VR to
prevent VOUT undershoot during quick load transient from
light load to heavy load. Hence, the RT8867A builds in a
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15
RT8867A
Figure 6 is the current sense circuit.
L
L
DCR
RS
CS
-
Transient
Boost
…
(Current Sense
Amplifier)
CSA
CSP
+
-
CSN
Load Line
Adjustment
VOUT
TB
DCR
IOUT
VCORE
COUT
RL
RS
Sensitivity of the transient boost can be adjusted by varying
the values of CFB and RFB. Smaller RFB and/or larger CFB
will make transient boost easier to be triggered. Figure 5
shows the circuit and typical waveforms.
RTB
L
PH2
VOUT − VTB = 10μA x RTB.
VOUT
…
PH1
DCR
…
PHn
…
state-of-the-art transient boost function which detects load
transient by monitoring VOUT. If VOUT suddenly drops below
“VTB” the transient boost signal rises up and the RT8867A
turns on all high side MOSFETs and turns off all low side
MOSFETs. The voltage difference “VOUT − VTB” is set by
following equation :
RS
IX
RX
NTC
RCSN
Figure 6. Circuit for Current Sensing
+
CTB
10µA
Figure 5. (a) Transient Boost Circuit
IOUT
VOUT
Transient
Boost
Figure 5. (b) Typical Waveforms
Output Current Sensing
The RT8867A provides a low input offset Current Sense
Amplifier (CSA) to monitor the output current. The output
current of CSA (IX) is used for load line control, dynamic
phase control and over current protection. In this average
inductor current sensing topology, RS and CS must be set
according to the equation below :
Requ = R X //RNTC
L = RS × CS
DCR
R
N+ S
Requ
Where the constant N is a set maximum operation phase
number, not affected by the dynamic phase control
machine. Then, the output current of CSA will follow the
equation below :
IX =
IOUT × DCR
N × RCSN
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16
Load Line
The RT8867A utilizes inductor DCR current sense
technique for load line control function. The sensed output
current is proportionally mirrored from the IX signal to the
RDROOP resistor to establish the voltage of VDROOP. VDROOP
subtracted from VDAC generates VEAP. The voltage control
loop is shown in Figure 3. Because IX is a PTC (Positive
Temperature Coefficient) current, an NTC (Negative
Temperature Coefficient) resistor is needed to connect in
parallel with the capacitor CS. If the NTC resistor is properly
selected to compensate the temperature coefficient of IX,
the VDROOP voltage will be proportional to IOUT without
temperature effect. In the RT8867A, the positive input of
error amplifier is VEAP and VOUT will follow “VDAC −
VDROOP”. Thus, the output voltage which decreases
linearly with IOUT is obtained. The load line is defined as :
LL(Load Line) =
ΔVOUT ΔVDROOP DCR × RDROOP × 4
=
=
ΔIOUT
ΔIOUT
N × RCSN
Basically, the resistance of RDROOP sets the resistance of
the load line. The temperature coefficient of RDROOP
compensates the temperature effect of the load line.
Connecting VRSEL pin to GND enables load line
adjustment function. When load line adjustment function
is enabled, the current IX is decreased by 10mV/RCSN.
Note that the minimum output current sensing range is
also reduced by 10mV/RCSN when load line adjustment
function is enabled.
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RT8867A
Current Balance
VCC5
The RT8867A sensed per phase current signal ISENx via
the voltages on the low side MOSFETs switch on
resistance (RDS(ON)) for current balance as shown in Figure
7, in which ISENx is defined as :
ISENx =
VR_SHDN
VSHDN
PS3/
VR_SHDN
IPHASEx × RDSON + VDC
RSENx
PS2
VDC
UGATEx
PHASEx
RISENx
LGATEx
Figure 7. Circuit for Current Balance
Dynamic
Phase
Control
10µA
-
VIMAX
+
Figure 8. Circuit for Dynamic Phase Control and VR
Shutdown
Table 2. Dynamic Phase Control
LX
ILX
+
PS1
VIMAX
ISENx
-
VIMAX
VIN
ISENx
+
10µA
In Figure 7, the phase current sense signals ISENx are
used to raise or lower the internal sawtooth waveforms
(RAMP [1] to RAMP [n]) which are compared with error
amplifier output (COMP) to generate a PWM signal. The
raised sawtooth waveform will decrease the PWM duty of
the corresponding phase current and the lowered sawtooth
waveform will increase the PWM duty of the corresponding
phase current. Eventually, current flowing through each
phase will be balanced.
-
-
VVR_SHDN
Where VDC is the offset voltage for the current balance
circuit.
+
/5
VIMAX
VPS1 < 0.8V, VPS2 < 0.1V
VIMAX = Don’t Care
VPS1 > 0.8V, VPS2 > 0.1V,
VIMAX = Don’t Care
Phase Number
Max
Max
4 Phase
3 Phase
Forced 1 Forced 1
(1)
(1)
Forced 4 Forced 3
(1, 2, 3, 4) (1, 2, 3)
> VPS1
> VPS2
V
> PS3
5
4
(1, 2, 3, 4)
3
(1, 2, 3)
> VPS1
> VPS2
V
< PS3
5
3
(1, 2, 3)
3
(1, 2, 3)
> VPS1
< VPS2
V
< PS3
5
2
(1, 3)
2
(1, 3)
< VPS1
< VPS2
V
< PS3
5
1
(1)
1
(1)
Dynamic Phase Control Capability
The RT8867A has the ability to automatically control its
phase number according to the total load current. Connect
a resistive voltage divider to PS3 pin to define the 3-4
phase transition threshold, VPS3. Connect a resistor to
ground at PS2 pin to set the 2-3 phase transition threshold,
VPS2. Connect a resistor to ground at PS1 pin to set the
1-2 phase transition threshold, VPS1.
The voltage at IMAX pin (VIMAX) represents total current
information, and the RT8867A will compare VIMAX with VPS1,
VPS2 and VPS3 / 5 to determine the number of operating
phases. Figure 8 shows the typical connections of PS1,
PS2 and PS3 pins for setting the dynamic phase control
thresholds.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8867A-03 July 2014
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RT8867A
After setting the voltages at the PS1 to PS3 pins, the
RT8867A will continuously compare VIMAX and VPS1 to VPS3
after POR. Once the VIMAX enters each voltage state
mentioned in Table 2, the RT8867A will automatically
change its operation phase number. See Table 2 for the
dynamic phase control mechanism. For Example, If VPS1
= 0.3V, VPS2 = 0.5V, VPS3 = 4V, the RT8867A will operate
in 4-phase operation when VIMAX = 0.9V, and 2 phase
operation when VIMAX = 0.4V. There are two states
mentioned in Table 2 that the RT8867A will be forced not
to change its operating phase number, and the VIMAX voltage
is meaningless for dynamic phase control circuit under
these conditions.
Over Current Protection (OCP)
When VIMAX is higher than 1.2V, the over current protection
is triggered with 100μs delay to prevent false trigger, and
the short circuit OCP level is designed at 1.6V with 10μs
delay. The controller will turn off all high side / low side
MOSFETs to protect CPU. Note that, the OCP level does
not change according to different operating phase numbers.
Over Voltage Protection (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once VFB exceeds “VEAP + 390mV”, OVP
is triggered and latched. The RT8867A will turn on low
side MOSFET and turn off high side MOSFET to protect
CPU.
Typically, the ESR zero of output capacitor will tend to
stabilize the effect of output LC double poles. Hence, the
position of the output capacitor ESR zero in frequency
domain may influence the design of voltage loop
compensation. Figure 9 shows a typical control loop using
type-III compensator. Below is the compensator design
procedure.
VIN
OSC
Driver
PWM
Comparator
ΔVOSC
L
-
VOUT
Driver
+
COUT
ESR
ZFB
COMP
EA
+
ZIN
REF
ZFB
C2
C1
ZIN
C3
R2
VOUT
R3
R1
COMP
FB
EA
+
REF
Figure 9. Compensation Circuit
Under Voltage Protection (UVP)
1) Modulator Characteristic
The under-voltage protection monitors the output voltage
via the FB pin. Once VFB is lower than “VEAP − 300mV”,
UVP is triggered and latched. The RT8867A will turn off
all high side / low side MOSFETs to protect CPU.
The modulator consists of the PWM comparator and power
stage. The PWM comparator compares the error amplifier
output (COMP) with oscillator (OSC) sawtooth wave to
provide a Pulse-Width Modulated (PWM) gate-driving
signal. The PWM wave is smoothed out by the output
filter, LOUT and COUT. The output voltage (VOUT) is sensed
and fed to the inverting input of the error amplifier. The
modulator transfer function is the small-signal transfer
function of VOUT/VCOMP (output voltage over the error
amplifier output). This transfer function is dominated by a
DC gain, a double pole, and an ESR zero as shown in
Figure 10. The DC gain of the modulator is the input
voltage (VIN) divided by the peak-to-peak oscillator voltage
VOSC. The output LC filter introduces a double pole, 40dB/
Loop Compensation
The RT8867A is a voltage mode controller and requires
external compensation. To compensate a typical voltage
mode buck converter, there are two ordinary compensation
schemes, commonly known as type-II compensator and
type-III compensator. The choice of using type-II or typeIII compensator lies with the platform designers, and the
main concern deals with the position of the capacitor ESR
zero and mid-frequency to high frequency gain boost.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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18
is a registered trademark of Richtek Technology Corporation.
DS8867A-03 July 2014
RT8867A
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 degrees. The resonant
frequency of the LC filter is expressed as:
1
fLC =
2π × LOUT × COUT
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires the output
capacitor to have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor is
expressed as the following equation :
1
fESR =
2π × COUT × ESR
fP2
fP3
Gain
fZ1 fZ2
Compensation Gain
1
C1
C2 × R2
×
2π ×
C1+ C2
Generally, fZ1 and fZ2 are designed to cancel the double
pole of the modulator. Usually, place fZ1 at a fraction of
fLC, and place fZ2 at fLC. fP2 is usually placed at fESR to
cancel the ESR zero, and fP3 is placed below the switching
frequency to cancel high frequency noise.
fP3 =
For a given bandwidth, R2, fZ1, fZ2, fP2, fP3, then
1
2π × R2 × fZ1
Gvd@BW
C3 =
2π × fC × R2
1
R1 =
2π × fZ2 × C3
1
R3 =
2π × fP2 × C3
1
C2 =
2π × fP3 × C1× R2 − 1
C1 =
where Gvd@BW is open loop gain at cross over frequency.
0
Closed Loop Gain
LOG
Thermal Monitoring (VR_HOT&VR_SHDN)
Open Loop Gain
LOG
fLC
fESR
fC
Frequency
Figure 10. Bode Plot of Loop Gain
2) Design of the Compensator
A well-designed compensator regulates the output voltage
to the reference voltage VREF with fast transient response
and good stability. In order to achieve fast transient
response and accurate output regulation, an adequate
compensator design is necessary. The goal of the
compensation network is to provide adequate phase
margin (usually greater than 45°) and the highest bandwidth
(0dB crossing frequency, f C ) possible. It is also
recommended to manipulate the loop frequency response
such that its gain crosses over 0dB at a slope of −20dB/
dec. According to Figure 10, the location of poles and
zeros are :
1
fZ1 =
2π × R2 × C1
1
fZ2 =
2π × (R1 + R3 ) × C3
fP1 = 0
fP2 =
1
2π × C3 × R3
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8867A-03 July 2014
The RT8867A provides thermal monitoring function via
sensing the TM pin voltage, and which can set 2 thresholds
to indicate ambient temperatures through the voltage
divider R1 and RNTC. The voltage of TM is typically set to
be higher than 0.5 x VCC5 when ambient temperature is
lower than VR_HOT & VR_SHDN assertion target.
However, when ambient temperature rises, TM voltage will
fall, and the VR_HOT signal will be set to high if TM voltage
drops below 0.43 x VCC5. Furthermore, if the temperature
continues to rise and the TM voltage is lower than 0.32 x
VCC5, the controller will pull the VR_SHDN signal to low.
Accordingly, VR_HOT will be reset when TM voltage rises
above 0.5 x VCC5, but the VR_SHDN signal will not
recover to high once thermal shutdown occurs.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
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RT8867A
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8867A, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For WQFN48L 6x6 packages, the thermal resistance, θJA, is 35°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (35°C/W) = 2.857W for
WQFN-48L 6x6 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. For the RT8867A package, the derating
curve in Figure 11 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Maximum Power Dissipation (W)
3.2
Four-Layer PCB
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 11. Derating Curve for RT8867A Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
20
DS8867A-03 July 2014
RT8867A
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
5.950
6.050
0.234
0.238
Option 1
4.250
4.350
0.167
0.171
Option 2
4.350
4.450
0.171
0.175
5.950
6.050
0.234
0.238
Option 1
4.250
4.350
0.167
0.171
Option 2
4.350
4.450
0.171
0.175
D2
E
E2
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 48L QFN 6x6 Package
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8867A-03 July 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
21
RT8867A
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
22
DS8867A-03 July 2014