® RT8167A Dual Single-Phase PWM Controller for CPU Core/GFX Power Supply General Description Features The RT8167A is a dual single-phase synchronous Buck PWM controller with integrated gate drivers, compliant with Intel VR12/IMVP7 specification. A serial VID (SVID) interface is built-in in the RT8167A to communicate with Intel VR12/IMVP7 compliant CPU. The integrated differential remote output voltage sensing function and built-in high accuracy DAC achieve accurate output voltage regulation. z The RT8167A supports VR12/ IMVP7 compatible power management states and VID on-the-fly function. The RT8167A operates in two power management states including DEM in PS2 and Forced-CCM in PS1/PS0. Richtek's proprietary G-NAVPTM (Green Native AVP) makes AVP (Active Voltage Positioning) design easier and more robust. By utilizing the G-NAVPTM topology, DEM and CCM efficiency can be improved. z z z z z z z z z z z z The RT8167A integrates high accuracy ADC for platform setting functions, such as no-load offset or over current level. Individual VR ready output signals are provided for both CORE VR and GFX VR. The IC also features complete fault protection functions, including over voltage, under voltage, negative voltage, over current and under voltage lockout. The RT8167A is available in a WQFN-48L 6x6 small foot print package. z z z z Applications z z z Marking Information G-NAVPTM (Green Native Active Voltage Positioning) Topology Dual Output Controller with Two Built-in Gate Drivers Serial VID Interface 0.5% DAC Accuracy Differential Remote Output Voltage Sensing Built-in ADC for Platform Programming Diode Emulation Mode (DEM) at Light Load Condition Droop Enable/Disable Fast Transient Response VR12/IMVP7 Compatible Power Management States VR Ready Indicator Thermal Throttling Indicator Current Monitor Output Switching Frequency up to 1MHz per Phase Protection : OVP, UVP, NVP, OCP, UVLO Small 48-Lead WQFN Package RoHS Compliant and Halogen Free VR12 / IMVP7 Intel CPU Core Supply AVP Step-down Converter Notebook/ Netbook/ Desktop Computer CPU Core Supply RT8167AGQW : Product Number RT8167A GQW YMDNN YMDNN : Date Code Ordering Information RT8167A Package Type QW : WQFN-48L 6x6 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 Suitable for use in SnPb or Pb-free soldering processes. is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 ® RT8167A Pin Configurations TONSET BOOT UGATE PHASE LGATE PVCC LGATEA PHASEA UGATEA BOOTA EN TONSETA (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 ISEN1P ISEN1N COMP FB RGND IMON IMONFB DRPEN OFS OFSA GFXPS2 VCC 1 36 2 35 3 34 4 33 5 32 6 31 GND 7 30 8 29 9 28 49 10 11 27 26 12 25 ISENAP ISENAN COMPA FBA RGNDA IMONA IMONFBA VCLK VDIO ALERT DRPENA VRA_READY SETINIA SETINI TMPMAX ICCMAX ICCMAXA TSEN OCSET TSENA OCSETA IBIAS VRHOT VR_READY 13 14 15 16 17 18 19 20 21 22 23 24 WQFN-48L 6x6 Functional Pin Description Pin No. Pin Name Pin Function 1 ISEN1P Positive Current Sense Input of CORE VR 2 ISEN1N Negative Current Sense Input of CORE VR 3 COMP CORE VR Compensation. This pin is the output node of the error amplifier. 4 FB CORE VR Feedback. This is the negative input node of the error amplifier. 5 RGND Return Ground for CORE VR. This pin is the negative input for differential remote voltage sensing. 6 IMON Current Monitor Output of CORE VR. The output voltage V IMON of this pin is proportional to the output current. For digital output current reporting, detailed VIMON is generated by built-in ADC. 7 IMONFB This pin is used to externally set the current monitor output gain of CORE VR. Connect this pin with one resistor R IMONFB to CORE VCC_SENSE while IMON pin is connected to ground with another resistor, RIMON. The current monitor output gain can be set by the ratio of these two resistors. 8 DRPEN Droop Enable Mode Setting of CORE VR. An internal 80μA current source is connected to the DRPEN pin and flows out of this pin for 10μs. Connect this pin to VCC to enable droop function. Connect this pin to GND to disable droop function. 9 OFS Output Voltage No-Load Offset Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage V OFS for offset setting. Connect this pin to GND for no offset setting. 10 OFSA Output Voltage No-Load Offset Setting of GFX VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage V OFSA for offset setting. Connect this pin to GND for no offset setting. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 2 ® RT8167A Pin No. Pin Name Pin Function 11 GFXPS2 Forced DEM Enable Setting of GFX VR. Connect to V CC for forced-DEM setting and connect to GND for following SVID power state command. 12 VCC 5V Power Supply Input of Controller. Bypass this pin to GND with a 1μF or greater ceramic capacitor. 13 SETINIA Initial Startup Voltage VINI_GFX Setting of GFX VR. Connect to a resistive voltage divider from V CC to GND to set the pin voltage VSETINIA for GFX VR initial startup voltage VINI_GFX setting. Connect this pin to GND for 0V VINI_GFX setting. 14 SETINI Initial Startup Voltage VINI_CORE Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage VSETINI for CORE VR initial startup voltage VINI_CORE setting. Connect this pin to GND for 0V V INI_CORE setting. 15 TMPMAX Maximum Temperature Setting of CORE VR. Connect to a resistive voltage divider from V CC to GND to set the pin voltage V TMPMAX for TMPMAX setting. 16 ICCMAX Maximum Current Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage VICCMAX for ICCMAX setting. 17 ICCMAXA Maximum Current Setting of GFX VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage VICCMAXA for ICCMAXA setting. 18 TSEN Thermal Monitor Sense Pin of CORE VR. 19 OCSET 20 TSENA 21 OCSETA 22 IBIAS 23 VRHOT Thermal Monitor Output (Active Low). Connect a pull high resistor from VRHOT pin to 1.05V. 24 VR_READY Voltage Ready Indicator of CORE VR. Connect a pull high resistor from VR_READY pin to 1.05V. 25 VRA_READY Voltage Ready Indicator GFX VR. Connect a pull high resistor from VRA_READY pin to 1.05V. 26 DRPENA Droop Enable Mode Setting of GFX VR. An internal 80μA current source is connected to DRPENA pin and flows out of this pin for 10μs. Connect this pin to VCC to enable droop function. Connect this pin to GND to disable droop function. 27 ALERT SVID Alert Pin (Active Low). Connect a 75Ω resistor from ALERT pin to 1.05V. 28 VDIO 29 VCLK 30 IMONFBA 31 IMONA Over Current Protection Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage VOCSET from 0 to 3.3V for CORE VR over current protection threshold. Thermal Monitor Sense Pin of GFX VR. Over Current Protection Setting of GFX VR. Connect to a resistive voltage divider from VCC to GND to adjust the pin voltage VOCSETA from 0 to 3.3V for GFX VR over current protection threshold. Internal bias current setting. Connect a 53.6kΩ resistor from IBIAS pin to GND. Controller and CPU Data Transmission Interface. Connecting a 64.9Ω resistor between VDIO pin to 1.05V. Synchronous Clock from the CPU. Connect a 64.9Ω resistor from VCLK pin to 1.05V. This pin is used to externally set the current monitor output gain of GFX VR. Connect this pin with one resistor RIMONFBA to GFX VCC_SENSE while IMON pin is connected to ground with another resistor RIMONA. The current monitor output gain can be set by the ratio of these two resistors. Current Monitor Output of GFX VR. The output voltage VIMONA of this pin is proportional to the output current. For digital output current reporting, detailed VIMONA is generated by built-in ADC. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8167A Pin No. Pin Name Pin Function 32 RGNDA Return Ground for GFX VR. This pin is the negative input for differential remote voltage sensing. 33 FBA GFX VR Feedback. This is the negative input node of the error amplifier. 34 COMPA GFX VR Compensation. This pin is the output node of the error amplifier. 35 ISENAN Negative Current Sense Input of GFX VR. 36 ISENAP Positive Current Sense Input of GFX VR. 37 TONSETA On-Time Setting of GFX VR. Connect this pin to VIN with one resistor. 38 EN Chip Enable (Active High). 39 BOOTA Bootstrap Flying Capacitor Connection for GFX VR. This pin powers the high side MOSFET drivers. Connect this pin to PHASEA with an external ceramic capacitor. 40 UGATEA High Side MOSFET Floating Gate Driver Output for GFX VR. Connect this pin to the gate of high side MOSFET. 41 PHASEA 42 LGATEA 43 PVCC 44 LGATE 45 PHASE 46 UGATE 47 BOOT Bootstrap Flying Capacitor Connection for CORE VR. This pin powers the high side MOSFET drivers. Connect this pin to PHASE with an external ceramic capacitor. 48 TONSET On-Time Setting of CORE VR. Connect this pin to VIN with one resistor. GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 49 (Exposed pad) Switching Node Connection for GFX VR. PHASEA is also the zero cross detect input for GFX VR. Connect this pin to the high side MOSFET sources together with the low side MOSFET drains and the inductor. Synchronous-Rectifier Gate Driver Output of GFX VR. Connect this pin to the gate of low side MOSFET. 5V Power Supply of Driver. Bypass this pin to GND with a 1μF or greater ceramic capacitor. Synchronous-Rectifier Gate Driver Output of CORE VR. Connect this pin to the gate of low side MOSFET. Switching Node Connection for CORE VR. PHASE is the internal lower supply rail for the UGATE. PHASE is also the zero cross detect input for CORE VR. Connect this pin to the high side MOSFET sources together with the low side MOSFET drains and the inductor. High Side MOSFET Floating Gate Driver Output for CORE VR. Connect this pin to the gate of high side MOSFET. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A Typical Application Circuit R1 2.2 5V RT8167A VCC TONSET 48 12 R3 5.1 VIN 5V to 25V C2 0.1µF VCC C1 1µF BOOT 47 R4 0 Q1 C4 10µF UGATE 46 VCCP R6 130 R7 130 R8 150 R9 10k R10 10k R5 0 R11 75 29 28 27 25 24 23 VCLK VDIO ALERT VRA_READY VR_READY VRHOT PHASE VCLK VDIO ALERT VRA_READY VR_READY VRHOT 44 LGATE 43 PVCC 26 8 21 19 13 14 R12 Optional 0 5V IMONFB FB C6 330µF /9m RNTC1 4.7k R14 3.9k R16 2.4k R15 4.7k 2 C9 Optional R23 10k 7 4 Optional C11 R24 0 C10 Optional Optional C12 CORE VCC_ SENSE COMP 3 5 RGND 6 IMON R28 R29 R30 R31 R32 R33 NC NC 10k 10k NC NC C26 330µF /9m C7 ISEN1P 1 ISEN1N DRPENA DRPEN OCSETA OCSET SETINIA SETINI DCR 7.6m R13 C8 1µF VCORE L1 1µH Q2 C5 0.068µF C25 R17 R18 R19 R20 R21 R22 10k 10k 27k 8.7k 10k 10k C3 0.1µF 45 Optional VCC DRPENA DRPEN OCSETA OCSET SETINIA SETINI R2 130k VCORE R27 100 R26 10k R25 71k CORE VSS_SENSE IMON C13 0.1µF VCC R34 100 R35 620k R36 39k TONSETA 37 TMPMAX ICCMAX ICCMAXA OFSA OFS GFXPS2 R37 R38 R39 R40 R41 R42 51k 150k 100k NC NC NC 15 16 17 10 9 11 TMPMAX ICCMAX ICCMAXA OFSA OFS GFXPS2 BOTTA 39 R43 R44 VIN 5V to 25 C14 0.1µF R45 0 Q3 R46 0 PHASEA C15 0.1µF 41 LGATEA 42 R53 Optional VCC RNTC T1 10k ß = 3380 R71 750 R62 1k R59 12k C17 ISENAN TSENA 18 TSEN 22 IBIAS R64 53.6k COMPA RGNDA EN 38 EN IMONA Optional C22 R60 10k R61 0 C21 Optional Optional C23 GFX VCC_SENSE 34 32 R65 42k IMONA C24 0.1µF VGFX R67 100 R66 10k 31 GND 49 (Exposed Pad) C19 330µF /15m R56 1k 35 IMONFBA 30 33 FBA C27 330µF /15m R57 1.2k C20 Optional 20 RNTCA 1k R55 11k C18 0.1µF RNTCTA 10k ß = 3380 R72 750 R63 1k DCR 14.6m R54 ISENAP 36 VGFX L2 2µH Q4 0 R47 R48 R49 R50 R51 R52 0 10k 33k 5.1k 1.6k 0 R58 12k C16 10µF UGATEA 40 R69 180k GFX VSS_SENSE R68 100 R70 1.8M Figure 1. Dual Output Application Circuit Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8167A RT8167A VCC R1 2.2 5V 12 TONSET 48 VCC C1 1µF R2 130k R3 5.1 BOOT VCCP 47 R4 0 Q1 UGATE 46 R6 130 R7 130 R8 150 R9 10k R5 0 R10 75 29 28 27 24 23 VCLK VDIO ALERT VR_READY VRHOT PHASE VCLK VDIO ALERT VR_READY VRHOT R17 R18 8.7k 10k R27 NC DCR 7.6m R12 5V C5 0.068µF C7 RNTC1 4.7k C26 330µF /9m C6 330µF /9m 2 R15 2.4k R14 4.7k C9 Optional 8 DRPEN 19 OCSET 14 SETINI DRPEN OCSET SETINI VCORE R13 3.9k C25 ISEN1N L1 1µH Optional Q2 44 R11 0 LGATE 43 PVCC C8 1µF ISEN1P 1 R16 10k C4 10µF C3 0.1µF 45 Optional VCC VIN 5V to 25 C2 0.1µF R28 R29 10k NC R20 0 R19 10k 7 IMONFB FB 4 C10 Optional Optional Optional CORE VCC_SENSE COMP RGND VCC R30 51k R31 150k IMON R32 NC 3 5 C11 C12 R21 71k R22 10k 6 IMON C13 0.1µF 15 TMPMAX 16 ICCMAX 9 OFS TMPMAX ICCMAX OFS TONSETA BOOTA R33 33k R34 5.1k R35 0 VCC R36 12k NTCT1 10k ß = 3380 18 R39 750 R37 1k 22 TSEN IBIAS R38 53.6k EN 38 37 39 UGATEA 40 41 PHASEA 42 LGATEA 25 VRA_READY 10 OFSA 17 ICCMAXA 11 GFXPS2 21 OCSETA 26 DRPENA 36 ISENAP IMONFBA 30 33 FBA 34 COMPA 31 IMONA 35 ISENAN 20 TSENA 32 RGNDA 13 SETINIA EN VCORE R23 100 R24 620k CORE VSS_SENSE R26 100k R25 39k GND Floating Floating Floating Floating GND GND VCC GND VCC GND VCC VCC Floating Floating GND VCC VCC GND GND GND 49 (Exposed Pad) Figure 2. Single Output Application Circuit Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A OFSA VREFA OFS Control FBA - + - Offset Cancellation + GFX 0LL VCS /5 + 10 - ISENAN VR_READY VRA_READY VRHOT CORE VR Protection Signal CORE VR VID/OFS Control GFX VR Protection Signal Droop Enabler DRPENA GFX VR CCRCOT PWM Generator TONSETA GM COMPA ISENAP GFXPS2 GND GFX 0LL EN ERROR AMP + Slew Rate Control VCC EN ICCMAXA CORE VR Slew Rate control GFX VR Slew Rate control CORE VR Operation Mode GFX VR Slew Rate control Control & Protection Logic GFX VR VID/OFS Control DAC ICCMAX ADC SVID XCVR GFX VR VID/OFS control RGNDA TSEN TSENA MUX GFX VR Operation Mode VREFA GFX 0LL EN GFX 0LL VCS SETINI SETINIA TMPMAX ALERT VDIO VCLK UVLO GFX VR Current Monitor CORE 0LL VCS VREF CORE 0LL EN CORE VR Current Monitor IMONFBA IMONA IMON IMONFB Function Block Diagram GFX 0LL EN X4.8 VREFA PWM CMP BOOTA GFX VR OCP Current Sense AMP UGATEA GFX VR Protection Signal OCSETA PHASEA Driver logic control PVCC GFX VR OV/UV/NV OFS DAC CORE VR Slew Rate control OFS Control VREF Slew Rate Control ERROR AMP + - FB CORE 0LL EN GM + - Offset Cancellation + RGND COMP CORE 0LL VCS ISEN1P ISEN1N LGATEA GFX VR Operation Mode CORE VR VID/OFS Control + 10 - /5 VREF Droop Enabler DRPEN CORE VR CCRCOT PWM Generator TONSET PWM CMP CORE 0LL EN X4.8 Current Sense AMP BOOT CORE VR OCP UGATE CORE VR Protection Signal OCSET PHASE Driver logic control PVDD CORE VR OV/UV/NV IBIAS 2.14V Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 CORE VR Operation Mode LGATE is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8167A Table 1. IMVP7/VR12 Compliant VID Table VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 VDAC Voltage 0 0 0 0 0 0 0 0 0 0 0.000 0 0 0 0 0 0 0 1 0 1 0.250 0 0 0 0 0 0 1 0 0 2 0.255 0 0 0 0 0 0 1 1 0 3 0.260 0 0 0 0 0 1 0 0 0 4 0.265 0 0 0 0 0 1 0 1 0 5 0.270 0 0 0 0 0 1 1 0 0 6 0.275 0 0 0 0 0 1 1 1 0 7 0.280 0 0 0 0 1 0 0 0 0 8 0.285 0 0 0 0 1 0 0 1 0 9 0.290 0 0 0 0 1 0 1 0 0 A 0.295 0 0 0 0 1 0 1 1 0 B 0.300 0 0 0 0 1 1 0 0 0 C 0.305 0 0 0 0 1 1 0 1 0 D 0.310 0 0 0 0 1 1 1 0 0 E 0.315 0 0 0 0 1 1 1 1 0 F 0.320 0 0 0 1 0 0 0 0 1 0 0.325 0 0 0 1 0 0 0 1 1 1 0.330 0 0 0 1 0 0 1 0 1 2 0.335 0 0 0 1 0 0 1 1 1 3 0.340 0 0 0 1 0 1 0 0 1 4 0.345 0 0 0 1 0 1 0 1 1 5 0.350 0 0 0 1 0 1 1 0 1 6 0.355 0 0 0 1 0 1 1 1 1 7 0.360 0 0 0 1 1 0 0 0 1 8 0.365 0 0 0 1 1 0 0 1 1 9 0.370 0 0 0 1 1 0 1 0 1 A 0.375 0 0 0 1 1 0 1 1 1 B 0.380 0 0 0 1 1 1 0 0 1 C 0.385 0 0 0 1 1 1 0 1 1 D 0.390 0 0 0 1 1 1 1 0 1 E 0.395 0 0 0 1 1 1 1 1 1 F 0.400 0 0 1 0 0 0 0 0 2 0 0.405 0 0 1 0 0 0 0 1 2 1 0.410 0 0 1 0 0 0 1 0 2 2 0.415 Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 0 1 0 0 0 1 1 2 3 0.420 0 0 1 0 0 1 0 0 2 4 0.425 0 0 1 0 0 1 0 1 2 5 0.430 0 0 1 0 0 1 1 0 2 6 0.435 0 0 1 0 0 1 1 1 2 7 0.440 0 0 1 0 1 0 0 0 2 8 0.445 0 0 1 0 1 0 0 1 2 9 0.450 0 0 1 0 1 0 1 0 2 A 0.455 0 0 1 0 1 0 1 1 2 B 0.460 0 0 1 0 1 1 0 0 2 C 0.465 0 0 1 0 1 1 0 1 2 D 0.470 0 0 1 0 1 1 1 0 2 E 0.475 0 0 1 0 1 1 1 1 2 F 0.480 0 0 1 1 0 0 0 0 3 0 0.485 0 0 1 1 0 0 0 1 3 1 0.490 0 0 1 1 0 0 1 0 3 2 0.495 0 0 1 1 0 0 1 1 3 3 0.500 0 0 1 1 0 1 0 0 3 4 0.505 0 0 1 1 0 1 0 1 3 5 0.510 0 0 1 1 0 1 1 0 3 6 0.515 0 0 1 1 0 1 1 1 3 7 0.520 0 0 1 1 1 0 0 0 3 8 0.525 0 0 1 1 1 0 0 1 3 9 0.530 0 0 1 1 1 0 1 0 3 A 0.535 0 0 1 1 1 0 1 1 3 B 0.540 0 0 1 1 1 1 0 0 3 C 0.545 0 0 1 1 1 1 0 1 3 D 0.550 0 0 1 1 1 1 1 0 3 E 0.555 0 0 1 1 1 1 1 1 3 F 0.560 0 1 0 0 0 0 0 0 4 0 0.565 0 1 0 0 0 0 0 1 4 1 0.570 0 1 0 0 0 0 1 0 4 2 0.575 0 1 0 0 0 0 1 1 4 3 0.580 0 1 0 0 0 1 0 0 4 4 0.585 0 1 0 0 0 1 0 1 4 5 0.590 Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8167A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 1 0 0 0 1 1 0 4 6 0.595 0 1 0 0 0 1 1 1 4 7 0.600 0 1 0 0 1 0 0 0 4 8 0.605 0 1 0 0 1 0 0 1 4 9 0.610 0 1 0 0 1 0 1 0 4 A 0.615 0 1 0 0 1 0 1 1 4 B 0.620 0 1 0 0 1 1 0 0 4 C 0.625 0 1 0 0 1 1 0 1 4 D 0.630 0 1 0 0 1 1 1 0 4 E 0.635 0 1 0 0 1 1 1 1 4 F 0.640 0 1 0 1 0 0 0 0 5 0 0.645 0 1 0 1 0 0 0 1 5 1 0.650 0 1 0 1 0 0 1 0 5 2 0.655 0 1 0 1 0 0 1 1 5 3 0.660 0 1 0 1 0 1 0 0 5 4 0.665 0 1 0 1 0 1 0 1 5 5 0.670 0 1 0 1 0 1 1 0 5 6 0.675 0 1 0 1 0 1 1 1 5 7 0.680 0 1 0 1 1 0 0 0 5 8 0.685 0 1 0 1 1 0 0 1 5 9 0.690 0 1 0 1 1 0 1 0 5 A 0.695 0 1 0 1 1 0 1 1 5 B 0.700 0 1 0 1 1 1 0 0 5 C 0.705 0 1 0 1 1 1 0 1 5 D 0.710 0 1 0 1 1 1 1 0 5 E 0.715 0 1 0 1 1 1 1 1 5 F 0.720 0 1 1 0 0 0 0 0 6 0 0.725 0 1 1 0 0 0 0 1 6 1 0.730 0 1 1 0 0 0 1 0 6 2 0.735 0 1 1 0 0 0 1 1 6 3 0.740 0 1 1 0 0 1 0 0 6 4 0.745 0 1 1 0 0 1 0 1 6 5 0.750 0 1 1 0 0 1 1 0 6 6 0.755 0 1 1 0 0 1 1 1 6 7 0.760 0 1 1 0 1 0 0 0 6 8 0.765 0 1 1 0 1 0 0 1 6 9 0.770 Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 1 1 0 1 0 1 0 6 A 0.775 0 1 1 0 1 0 1 1 6 B 0.780 0 1 1 0 1 1 0 0 6 C 0.785 0 1 1 0 1 1 0 1 6 D 0.790 0 1 1 0 1 1 1 0 6 E 0.795 0 1 1 0 1 1 1 1 6 F 0.800 0 1 1 1 0 0 0 0 7 0 0.805 0 1 1 1 0 0 0 1 7 1 0.810 0 1 1 1 0 0 1 0 7 2 0.815 0 1 1 1 0 0 1 1 7 3 0.820 0 1 1 1 0 1 0 0 7 4 0.825 0 1 1 1 0 1 0 1 7 5 0.830 0 1 1 1 0 1 1 0 7 6 0.835 0 1 1 1 0 1 1 1 7 7 0.840 0 1 1 1 1 0 0 0 7 8 0.845 0 1 1 1 1 0 0 1 7 9 0.850 0 1 1 1 1 0 1 0 7 A 0.855 0 1 1 1 1 0 1 1 7 B 0.860 0 1 1 1 1 1 0 0 7 C 0.865 0 1 1 1 1 1 0 1 7 D 0.870 0 1 1 1 1 1 1 0 7 E 0.875 0 1 1 1 1 1 1 1 7 F 0.880 1 0 0 0 0 0 0 0 8 0 0.885 1 0 0 0 0 0 0 1 8 1 0.890 1 0 0 0 0 0 1 0 8 2 0.895 1 0 0 0 0 0 1 1 8 3 0.900 1 0 0 0 0 1 0 0 8 4 0.905 1 0 0 0 0 1 0 1 8 5 0.910 1 0 0 0 0 1 1 0 8 6 0.915 1 0 0 0 0 1 1 1 8 7 0.920 1 0 0 0 1 0 0 0 8 8 0.925 1 0 0 0 1 0 0 1 8 9 0.930 1 0 0 0 1 0 1 0 8 A 0.935 1 0 0 0 1 0 1 1 8 B 0.940 1 0 0 0 1 1 0 0 8 C 0.945 1 0 0 0 1 1 0 1 8 D 0.950 Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT8167A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 0 0 0 1 1 1 0 8 E 0.955 1 0 0 0 1 1 1 1 8 F 0.960 1 0 0 1 0 0 0 0 9 0 0.965 1 0 0 1 0 0 0 1 9 1 0.970 1 0 0 1 0 0 1 0 9 2 0.975 1 0 0 1 0 0 1 1 9 3 0.980 1 0 0 1 0 1 0 0 9 4 0.985 1 0 0 1 0 1 0 1 9 5 0.990 1 0 0 1 0 1 1 0 9 6 0.995 1 0 0 1 0 1 1 1 9 7 1.000 1 0 0 1 1 0 0 0 9 8 1.005 1 0 0 1 1 0 0 1 9 9 1.010 1 0 0 1 1 0 1 0 9 A 1.015 1 0 0 1 1 0 1 1 9 B 1.020 1 0 0 1 1 1 0 0 9 C 1.025 1 0 0 1 1 1 0 1 9 D 1.030 1 0 0 1 1 1 1 0 9 E 1.035 1 0 0 1 1 1 1 1 9 F 1.040 1 0 1 0 0 0 0 0 A 0 1.045 1 0 1 0 0 0 0 1 A 1 1.050 1 0 1 0 0 0 1 0 A 2 1.055 1 0 1 0 0 0 1 1 A 3 1.060 1 0 1 0 0 1 0 0 A 4 1.065 1 0 1 0 0 1 0 1 A 5 1.070 1 0 1 0 0 1 1 0 A 6 1.075 1 0 1 0 0 1 1 1 A 7 1.080 1 0 1 0 1 0 0 0 A 8 1.085 1 0 1 0 1 0 0 1 A 9 1.090 1 0 1 0 1 0 1 0 A A 1.095 1 0 1 0 1 0 1 1 A B 1.100 1 0 1 0 1 1 0 0 A C 1.105 1 0 1 0 1 1 0 1 A D 1.110 1 0 1 0 1 1 1 0 A E 1.115 1 0 1 0 1 1 1 1 A F 1.120 1 0 1 1 0 0 0 0 B 0 1.125 1 0 1 1 0 0 0 1 B 1 1.130 Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 0 1 1 0 0 1 0 B 2 1.135 1 0 1 1 0 0 1 1 B 3 1.140 1 0 1 1 0 1 0 0 B 4 1.145 1 0 1 1 0 1 0 1 B 5 1.150 1 0 1 1 0 1 1 0 B 6 1.155 1 0 1 1 0 1 1 1 B 7 1.160 1 0 1 1 1 0 0 0 B 8 1.165 1 0 1 1 1 0 0 1 B 9 1.170 1 0 1 1 1 0 1 0 B A 1.175 1 0 1 1 1 0 1 1 B B 1.180 1 0 1 1 1 1 0 0 B C 1.185 1 0 1 1 1 1 0 1 B D 1.190 1 0 1 1 1 1 1 0 B E 1.195 1 0 1 1 1 1 1 1 B F 1.200 1 1 0 0 0 0 0 0 C 0 1.205 1 1 0 0 0 0 0 1 C 1 1.210 1 1 0 0 0 0 1 0 C 2 1.215 1 1 0 0 0 0 1 1 C 3 1.220 1 1 0 0 0 1 0 0 C 4 1.225 1 1 0 0 0 1 0 1 C 5 1.230 1 1 0 0 0 1 1 0 C 6 1.235 1 1 0 0 0 1 1 1 C 7 1.240 1 1 0 0 1 0 0 0 C 8 1.245 1 1 0 0 1 0 0 1 C 9 1.250 1 1 0 0 1 0 1 0 C A 1.255 1 1 0 0 1 0 1 1 C B 1.260 1 1 0 0 1 1 0 0 C C 1.265 1 1 0 0 1 1 0 1 C D 1.270 1 1 0 0 1 1 1 0 C E 1.275 1 1 0 0 1 1 1 1 C F 1.280 1 1 0 1 0 0 0 0 D 0 1.285 1 1 0 1 0 0 0 1 D 1 1.290 1 1 0 1 0 0 1 0 D 2 1.295 1 1 0 1 0 0 1 1 D 3 1.300 1 1 0 1 0 1 0 0 D 4 1.305 1 1 0 1 0 1 0 1 D 5 1.310 Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT8167A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 1 0 1 0 1 1 0 D 6 1.315 1 1 0 1 0 1 1 1 D 7 1.320 1 1 0 1 1 0 0 0 D 8 1.325 1 1 0 1 1 0 0 1 D 9 1.330 1 1 0 1 1 0 1 0 D A 1.335 1 1 0 1 1 0 1 1 D B 1.340 1 1 0 1 1 1 0 0 D C 1.345 1 1 0 1 1 1 0 1 D D 1.350 1 1 0 1 1 1 1 0 D E 1.355 1 1 0 1 1 1 1 1 D F 1.360 1 1 1 0 0 0 0 0 E 0 1.365 1 1 1 0 0 0 0 1 E 1 1.370 1 1 1 0 0 0 1 0 E 2 1.375 1 1 1 0 0 0 1 1 E 3 1.380 1 1 1 0 0 1 0 0 E 4 1.385 1 1 1 0 0 1 0 1 E 5 1.390 1 1 1 0 0 1 1 0 E 6 1.395 1 1 1 0 0 1 1 1 E 7 1.400 1 1 1 0 1 0 0 0 E 8 1.405 1 1 1 0 1 0 0 1 E 9 1.410 1 1 1 0 1 0 1 0 E A 1.415 1 1 1 0 1 0 1 1 E B 1.420 1 1 1 0 1 1 0 0 E C 1.425 1 1 1 0 1 1 0 1 E D 1.430 1 1 1 0 1 1 1 0 E E 1.435 1 1 1 0 1 1 1 1 E F 1.440 1 1 1 1 0 0 0 0 F 0 1.445 1 1 1 1 0 0 0 1 F 1 1.450 1 1 1 1 0 0 1 0 F 2 1.455 1 1 1 1 0 0 1 1 F 3 1.460 1 1 1 1 0 1 0 0 F 4 1.465 1 1 1 1 0 1 0 1 F 5 1.470 1 1 1 1 0 1 1 0 F 6 1.475 1 1 1 1 0 1 1 1 F 7 1.480 1 1 1 1 1 0 0 0 F 8 1.485 Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 1 1 1 1 0 0 1 F 9 1.490 1 1 1 1 1 0 1 0 F A 1.495 1 1 1 1 1 0 1 1 F B 1.500 1 1 1 1 1 1 0 0 F C 1.505 1 1 1 1 1 1 0 1 F D 1.510 1 1 1 1 1 1 1 0 F E 1.515 1 1 1 1 1 1 1 1 F F 1.520 Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT8167A Absolute Maximum Ratings (Note 1) VCC to GND ----------------------------------------------------------------------------------------------PVCC to GND --------------------------------------------------------------------------------------------z RGNDx to GND ------------------------------------------------------------------------------------------z TONSETx to GND ---------------------------------------------------------------------------------------z Others ------------------------------------------------------------------------------------------------------z BOOTx to PHASEx -------------------------------------------------------------------------------------z PHASEx to GND DC -----------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------z UGATEx to PHASEx DC -----------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------z LGATEx to GND DC -----------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C z z z z z z z WQFN−48L 6x6 ------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN−48L 6x6, θJA ------------------------------------------------------------------------------------WQFN−48L 6x6, θJC ------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------- Recommended Operating Conditions z z z z z −0.3V to 6.5V −0.3V to 6.5V −0.3V to 0.3V −0.3V to 28V −0.3V to (VCC + 0.3V) −0.3V to 6.5V −0.3V to 28V −8V to 32V −0.3V to (BOOTx − PHASEx) −5V to 7.5V −0.3V to (PVCC − 0.3V) −2.5V to 7.5V 2.857W 35°C/W 6°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Voltage of Controller, VCC -------------------------------------------------------------------- 4.5V to 5.5V Supply Voltage of Gate Driver, VPVCC ---------------------------------------------------------------- 4.5V to 5.5V Battery Input Voltage, VIN ------------------------------------------------------------------------------ 5V to 25V Junction Temperature Range --------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Supply Input Input Voltage Range Supply Current (VCC + PVCC) Supply Current (TONSETx) Symbol Test Conditions Min Typ Max Unit VCC/VPVCC VIN VEN = 1.05V, Not Switching Battery Input Voltage 4.5 5 5 -- 5.5 25 V V IVCC + IPVCC VEN = 1.05V, Not Switching -- 12 20 mA I TONSETx VFB =1V, VIN = 12V, RTON = 100kΩ -- 110 -- μA Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Current (PVCC + VCC) IVCC_SHDN + IPVCC_SHDN VEN = 0V -- -- 5 μA Shutdown Current (TONSETx) ITONSETx_SHDN VEN = 0V -- -- 5 μA TONSETx Voltage VTONSETx IRTON = 80μA, VFBx = 1V 0.95 1.075 1.2 0V On-Time tON IRTON = 80μA, VFBx = 1V 315 350 385 ns VFBx = 1.1V 25 -- 280 μA -- 350 -- ns -- 80 -- μA 4.5 -- -- TON Setting TONSETx Input Current IRTON Range Minimum Off-Time T OFF_MIN Droop Enable / Disable DRPENx Internal IDRPENx Current Source Droop Enable Threshold VDRPENx Droop Disable Threshold GFX VR Forced DEM GFXPS2x Enable Threshold GFXPS2x Disable Threshold VDRPENx EN goes high within 10μs Detect VDRPENx, EN goes high within 10μs Detect VDRPENx, EN goes high within 10μs V -- -- 2 VGFXPS 4.3 -- -- V VGFXPS -- -- 0.7 V VIDSVID Setting = 1.000V~1.520V OFSSVID Setting = 0V −0.5 0 0.5 %VID VIDSVID Setting = 0.800V~1.000V OFSSVID Setting = 0V −5 0 5 VIDSVID Setting = 0.500V~0.800V OFSSVID Setting = 0V −8 0 8 VIDSVID Setting = 0.250V~0.500V OFSSVID Setting = 0V −8 0 8 VIDSVID Setting = 1.100V OFSSVID Setting = −0.640V~0.635V −10 0 10 References and System Output Voltage DAC Accuracy (PS0/PS1) VFBx VINI_CORE = 0V, VINI_GFX = 0V SETINIx Voltage External OFSx Voltage VSETINIx VOFSx 0 0.3125 0.5125 VINI_CORE = 0.9V, VINI_GFX = 0.9V 0.7375 0.9375 1.1375 VINI_CORE = 1V, VINI_GFX = 1V 1.3625 1.5625 1.7625 VINI_CORE = 1.1V, VINI_GFX = 1.1V 2.6125 -- 5 Offset = 100mV 68 72 -- Offset = 50mV 52 56 60 Offset = −50mV 36 40 44 Offset = −100mV 20 24 28 No Offset Voltage 0 8 12 1 -- -- Impedance of OFSx Pin ROFSx Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 mV V %VCC MΩ is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT8167A Parameter Symbol Min Typ Max Unit 2.09 2.14 2.19 V SetVID Slow 2.5 3.125 3.75 SetVID Fast 10 12.5 15 70 80 -- dB -- 10 -- MHz -- 5 -- V/μs 0.5 -- 3.6 V -- 250 -- μA RFBx 1 -- -- MΩ VOFS_CSA −1 -- 1 mV Impedance of Neg. Input RISENxN 1 -- -- MΩ Impedance of Pos. Input 1 -- -- MΩ −50 -- 100 mV IBIAS Pin Voltage VIBIAS Dynamic VID Slew Rate SRDVID Test Conditions R IBIAS = 53.6kΩ mV/μs Error Amplifier DC Gain ADC R L = 47kΩ (Note5) Gain-Bandwidth Product GBW Slew Rate SRCOMP Output Voltage Range MAX Source/Sink Current Impedance of FBx VCOMP C LOAD = 5pF (Note5) C LOAD = 10pF (Gain = −4, RLOAD_COMP = 47kΩ, VCOMPx = 0.5V to 3V) R L = 47kΩ I COMP VCOMP = 2V Current Sense Amplifier Input Offset Voltage Current Sense Differential Input Range Current Sense DC Gain (Loop) VISEN Linearity RISENxP VCSDIx VFBx = 1.1V, VCSDIx = VISENxP − VISENxN AI VFBx = 1.1V, −30mV < VCSDIx < 50mV -- 10 -- V/V VISEN_ACC VDAC = 1.1V − 30mV < VISEN_IN < 50mV −1 -- 1 % -- 1.6 -- V -- 1.6 -- V 0 -- 3.3 V 3.3V / 255 = 12.94mV -- 12.94 -- mV VIMONx = 388.3mV, DIOUT [7 : 0] = 30 27 30 33 Decimal VIMONx = 776.5mV, DIOUT [7 : 0] = 60 57 60 63 Decimal VIMONx = 1164.7mV, DIOUT [7 : 0] = 90 87 90 93 Decimal -- 1600 -- μs Digital Current Monitor Current Monitor Output = 1V, VISENxN = 0.9V, V VIMONx_ENLL FBx Voltage (Droop Enabled) VRIMONFBx = 10k, RIMONx = 160k VCSDIx = VISENxP − VISENxN = 100mV Current Monitor Output VIMONx_DISLL VFBx = 1V, VRIMONFBx = 10k, Voltage (Droop Disabled) R IMONx = 80k IMON Voltage Range VIMON Digital IMON LSB Digital Code of IMON Update Period of Digital Current Monitor CDIMON t IMON Gate Driver Upper Driver Source RUGATEx_sr VBOOTx − VPHASEx = 5V VBOOTx − VUGATEx = 0.1V -- 1 -- Ω Upper Driver Sink RUGATEx_sk VUGATEx = 0.1V -- 1 -- Ω Lower Driver Source RLGATEx_sr PVCC = 5V, PVCC − VLGATEx = 0.1V -- 1 -- Ω Lower Driver Sink RLGATEx_sk VLGATEx = 0.1V -- 0.5 -- Ω Internal Boot Charging Switch On-Resistance RBOOTx PVCC to BOOTx -- 30 -- Ω Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A Parameter Zero Current Detection Threshold Protection Under Voltage Lock-out Threshold Under Voltage Lock-out Hysteresis Over Voltage Protection Threshold Under Voltage Protection Threshold Negative Voltage Protection Threshold Current Sense Gain for Over Current Protection Symbol Test Conditions Min Typ Max Unit -- 10 -- mV 4.04 4.24 -- V -- 100 -- mV 100 150 200 mV −350 −300 −250 mV −100 −50 -- mV -- 48 -- V/V With respect to 1V, 70% 0.7 -- -- V With respect to 1V, 30% -- -- 0.3 V −1 -- 1 μA VZCD_TH VZCD_TH = GND − VPHASEx VUVLO VCC Falling edge ΔVUVLO VOVP VUVP Respect to VOUT_MAXSVID, with 1μs filter time VUVP = VISENxN − VREFx, 0.8V < VREFx <1.52V, with 3μs filter time VNVP VNVP = VISENxN − GND AOC VOCSET = 2.4V VISENxP − VISENxN = 50mV Logic Inputs EN Input Logic-High VIH Threshold Logic-Low VIL Voltage Leakage Current of EN VIH With respect to Intel Spec. 0.65 -- -- V VIL With respect to Intel Spec. -- -- 0.45 V −1 -- 1 μA -- -- 0.4 V VRx_READY Low Voltage VVRx_READY IVRx_READY_ SINK = 4mA -- -- 0.4 V VRx_READY Delay VCLK,VDIO Input Threshold Voltage Leakage Current of VCLK, VDIO ALERT ALERT Low Voltage I LEAK_IN VALERT IALERT_ SINK = 4mA VR Ready t VRx_READY VISENxN = VBOOT to VVRx_READY high 70 100 160 μs VVRHOT IVRHOT_SINK = 40mA -- 0.4 -- V −1 -- 1 μA Thermal Throttling VRHOT Output Voltage High Impedance Output ALERT, VRx_READY, VRHOT I LEAK_OUT Temperature Zone TSEN Threshold for Tmp_Zone [7] transition 100°C -- 1.8725 -- V TSEN Threshold for Tmp_Zone [6] transition 97°C -- 1.8175 -- V 94°C -- 1.7625 -- V TSEN Threshold for Tmp_Zone [4] transition 91°C -- 1.7075 -- V TSEN Threshold for Tmp_Zone [3] transition 88°C -- 1.6525 -- V TSEN Threshold for Tmp_Zone [5] transition VTSENx Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT8167A Parameter Symbol TSEN Threshold for Tmp_Zone [2] transition TSEN Threshold for Tmp_Zone [1] transition TSEN Threshold for Tmp_Zone [0] transition VTSENx Update Period tTSEN Test Conditions Min Typ Max Unit 85°C -- 1.5975 -- V 82°C -- 1.5425 -- V 75°C -- 1.4875 -- V -- 1600 -- μs -- -- 400 μs ADC Latency Digital Code of ICCMAX Digital Code of ICCMAXA Digital Code of TMPMAX tLAT CICCMAX1 VICCMAX = 0.637V 29 32 35 decimal CICCMAX2 VICCMAX = 1.2642V 61 64 67 decimal CICCMAX3 VICCMAX = 2.5186V 125 128 131 decimal CICCMAXA1 VICCMAXA = 0.1666V 5 8 11 decimal CICCMAXA2 VICCMAXA = 0.3234V 13 16 19 decimal CICCMAXA3 VICCMAXA = 0.637V 29 32 35 decimal CTMPMAX1 VTMPMAX = 1.6758V 82 85 88 decimal CTMPMAX2 VTMPMAX = 1.9698V 97 100 103 decimal CTMPMAX3 VTMPMAX = 2.4598V 122 125 128 decimal Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A Typical Operating Characteristics CORE VR Power Off from EN CORE VR Power On from EN V CORE (500mV/Div) EN (2V/Div) VR_READY (2V/Div) V CORE (500mV/Div) EN (2V/Div) VR_READY (2V/Div) UGATE (20V/Div) UGATE (20V/Div) Boot VID = 1V Boot VID = 1V Time (100μs/Div) Time (100μs/Div) CORE VR OCP CORE VR OVP and NVP V CORE (1V/Div) V CORE (1V/Div) I LOAD (10A/Div) LGATE (10V/Div) VR_READY (1V/Div) VR_READY (1V/Div) UGATE (20V/Div) UGATE (20V/Div) VID = 1.1V VID = 1.1V Time (100μs/Div) Time (40μs/Div) CORE VR Dynamic VID Up CORE VR Dynamic VID Down V CORE (500mV/Div) V CORE (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) 0.7V to 1.2V, Slew Rate = Slow, ILOAD = 4A Time (40μs/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 ALERT (2V/Div) 1.2V to 0.7V, Slew Rate = Slow, ILOAD = 4A Time (40μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT8167A CORE VR Dynamic VID Down CORE VR Dynamic VID Up V CORE (500mV/Div) V CORE (500mV/Div) VCLK (2V/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VDIO (2V/Div) ALERT (2V/Div) 0.7V to 1.2V, Slew Rate = Fast, ILOAD = 4A 1.2V to 0.7V, Slew Rate = Fast, ILOAD = 4A Time (10μs/Div) Time (10μs/Div) CORE VR Load Transient CORE VR Load Transient V CORE (20mV/Div) V CORE (20mV/Div) 8 I LOAD (A/Div) 1 8 I LOAD (A/Div) 1 VID = 1.1V, ILOAD = 1A to 8A, Slew Time = 150ns VID = 1.1V, ILOAD = 8A to 1A, Slew Time = 150ns Time (100μs/Div) Time (100μs/Div) CORE VR Mode Transition CORE VR Mode Transition V CORE (20mV/Div) V CORE (20mV/Div) VCLK (1V/Div) LGATE (10V/Div) VCLK (1V/Div) LGATE (10V/Div) UGATE (20V/Div) UGATE (20V/Div) VID = 1.1V, PS0 to PS2, ILOAD = 0.2A VID = 1.1V, PS2 to PS0, ILOAD = 0.2A Time (100μs/Div) Time (100μs/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A CORE VR Thermal Monitoring CORE VR VREF vs. Temperature 1.10 1.08 1.9 1.06 TSEN (V/Div) 1.04 VREF (V) 1.7 1.02 1.00 0.98 0.96 0.94 VRHOT (500mV/Div) TSEN Sweep from 1.7V to 1.9V 0.92 0.90 Time (10ms/Div) -50 -25 0 25 50 75 100 125 Temperature (°C) GFX VR Power On from EN GFX VR Power Off from EN VGFX (500mV/Div) EN (2V/Div) VRA_READY (2V/Div) VGFX (500mV/Div) EN (2V/Div) VRA_READY (2V/Div) UGATEA (20V/Div) UGATEA (20V/Div) Boot VID = 1V Boot VID = 1V Time (100μs/Div) Time (100μs/Div) GFX VR OCP GFX VR OVP and NVP VGFX (1V/Div) VGFX (1V/Div) I LOAD (5A/Div) VRA_READY (1V/Div) LGATEA (10V/Div) VRA_READY (1V/Div) UGATEA (20V/Div) UGATEA (20V/Div) VID = 1.1V Time (100μs/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 Time (40μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT8167A GFX VR Dynamic VID GFX VR Dynamic VID VGFX (500mV/Div) VGFX (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) 0.7V to 1.2V, Slew Rate = Slow, ILOAD = 1.25A 1.2V to 0.7V, Slew Rate = Slow, ILOAD = 1.25A Time (40μs/Div) Time (40μs/Div) GFX VR Dynamic VID GFX VR Dynamic VID VGFX (500mV/Div) VGFX (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) ALERT (2V/Div) 0.7V to 1.2V, Slew Rate = Fast, ILOAD = 1.25A 1.2V to 0.7V, Slew Rate = Fast, ILOAD = 1.25A Time (10μs/Div) Time (10μs/Div) GFX VR Load Transient GFX VR Load Transient VGFX (20mV/Div) VGFX (20mV/Div) I LOAD 4 (A/Div) 1 I LOAD 4 (A/Div) 1 VID = 1.1V, ILOAD = 1A to 4A, Slew Time = 150ns Time (100μs/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 VID = 1.1V, ILOAD = 4A to 1A, Slew Time = 150ns Time (100μs/Div) is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A GFX VR Mode Transition GFX VR Mode Transition VGFX (20mV/Div) VGFX (20mV/Div) VCLK (1V/Div) VCLK (1V/Div) LGATEA (10V/Div) LGATEA (10V/Div) UGATEA (20V/Div) UGATEA (20V/Div) VID = 1.1V, PS0 to PS2, ILOAD = 0.1A VID = 1.1V, PS2 to PS0, ILOAD = 0.1A Time (100μs/Div) Time (100μs/Div) GFX VR Thermal Monitoring GFX VR VREF vs. Temperature 1.10 1.08 1.9 TSENA (V/Div) 1.06 1.04 VREF (V) 1.7 1.02 1.00 0.98 0.96 0.94 VRHOT (500mV/Div) TSENA Sweep from 1.7V to 1.9V 0.92 0.90 Time (10ms/Div) -50 -25 0 25 50 75 100 125 Temperature (°C) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT8167A Application Information The RT8167A is a VR12/IMVP7 compliant, dual singlephase synchronous Buck PWM controller for the CPU CORE VR and GFX VR. The gate drivers are embedded to facilitate PCB design and reduce the total BOM cost. A serial VID (SVID) interface is built-in in the RT8167A to communicate with Intel VR12/IMVP7 compliant CPU. The RT8167A adopts G-NAVPTM (Green Native AVP), which is Richtek's proprietary topology derived from finite DC gain compensator, making it an easy setting PWM controller to meet AVP requirements. The load line can be easily programmed by setting the DC gain of the error amplifier. The RT8167A has fast transient response due to the G-NAVPTM commanding variable switching frequency. G-NAVPTM topology also represents a high efficiency system with green power concept. With G-NAVP TM topology, the RT8167A becomes a green power controller with high efficiency under heavy load, light load, and very light load conditions. The RT8167A supports mode transition function between CCM and DEM. These different operating states allow the overall power system to have low power loss. By utilizing the G-NAVPTM topology, the operating frequency of RT8167A varies with output voltage, load and VIN to further enhance the efficiency even in CCM. The built-in high accuracy DAC converts the SVID code ranging from 0.25V to 1.52V with 5mV per step. The differential remote output voltage sense and high accuracy DAC allow the system to have high output voltage accuracy. The RT8167A supports VR12/IMVP7 compatible power Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 26 management states and VID on-the-fly function. The power management states include DEM in PS2/PS3 and ForcedCCM in PS1/PS0. The VID on-the-fly function has three different slew rates : Fast, Slow and Decay. The RT8167A integrates a high accuracy ADC for platform setting functions, such as no-load offset and over current level. The controller supports both DCR and sense-resistor current sensing. The RT8167A provides VR ready output signals of both CORE VR and GFX VR. It also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and under voltage lockout. The RT8167A is available in a WQFN48L 6x6 small foot print package. Design Tool To help users reduce efforts and errors caused by manual calculations, a user-friendly design tool is now available on request. This design tool calculates all necessary design parameters by entering user's requirements. Please contact Richtek's representatives for details. Serial VID (SVID) Interface SVID is a three-wire serial synchronous interface defined by Intel. The three wire bus includes VDIO, VCLK and ALERT signals. The master (Intel's VR12/IMVP7 CPU) initiates and terminates SVID transactions and drives the VDIO, VCLK, and ALERT during a transaction. The slave (RT8167A) receives the SVID transactions and acts accordingly. is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A Standard Serial VID Command Master Payload Slave Payload Contents Contents Code Commands 00h not supported N/A N/A 01h SetVID_Fast VID code N/A 02h SetVID_Slow VID code N/A 03h SetVID_Decay VID code N/A 04h SetPS Byte indicating power states N/A Set power state 05h SetRegADR Pointer of registers in data table N/A Set the pointer of the data register 06h SetReg DAT New data register content N/A Write the contents to the data register 07h GetReg Pointer of registers in data table Specified Register Contents Slave returns the contents of the specified register as the payload 08h 1Fh not supported N/A N/A N/A Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 Description N/A Set new target VID code, VR jumps to new VID target with controlled default “fast” slew rate 12.5mV/μs. Set new target VID code, VR jumps to new VID target with controlled default “slow” slew rate 3.125mV/μs. Set new target VID code, VR jumps to new VID target, but does not control the slew rate. The output voltage decays at a rate proportional to the load current is a registered trademark of Richtek Technology Corporation. www.richtek.com 27 RT8167A Index 00h 01h 02h 05h Register Name Vendor ID Product ID Product Revision Protocol ID 06h VR_Capability 10h Status_1 11h Status-2 Temperature Zone 12h Data and Configuration Register Description Vendor ID, default 1Eh. Product ID. Product Revision. SVID Protocol ID. Bit mapped register, identifies the SVID VR capabilities and which of the optional telemetry register are supported. Data register containing the status of VR. Access RO, Vendor RO, Vendor RO, Vendor RO, Vendor Default 1Eh 65h 01h 01h RO, Vendor 81h R-M, W-PWM 00h Data register containing the status of transmission. Data register showing temperature zone that have been entered. Data register showing direct ADC conversion of averaged output current. R-M, W-PWM 00h R-M, W-PWM 00h R-M, W-PWM 00h The register contains a copy of the status_2. R-M, W-PWM 00h RO, Platform -- RO, Platform -- RO 0Ah RO 02h RW, Master BFh RW, Master 00h 15h Output_Current 1Ch Status_2_lastread 21h ICC_Max 22h Temp_Max 24h SR-Fast 25h SR-Slow 30h VOUT_Max 31h VID Setting Data register containing the maximum ICC of platform supports. Binary format in Amp, IE 64h = 100A. Data register containing the temperature max the platform supports. Binary format in °C, IE 64h = 100°C Only for CORE VR Data register containing the capability of fast slew rate the platform can sustains. Binary format in mV/μs, IE 0Ah = 10mV/μs. Data register containing the capability of slow slew rate. Binary format in mV/μs IE 02h = 2.5mV/μs. The register is programmed by the master and sets the maximum VID. Data register containing currently programmed VID. 32h Power State Register containing the current programmed power state. RW, Master 00h 33h Offset Set offset in VID steps. RW, Master 00h 34h Multi VR Config RW, Master 00h 35h Pointer RW, Master 30h Bit mapped data register which configures multiple VRs behavior on the same bus. Scratch pad register for temporary storage of the SetRegADR pointer register. Notes : RO = Read Only RW = Read/Write R-M = Read by Master W-PWM = Write by PWM only Vendor = hard coded by VR vendor Platform = programmed by platform Master = programmed by the master PWM = programmed by the VR control IC Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 28 is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A Power Ready Detection and Power On Reset (POR) VCC + VUVLO EN + VENTH POR Chip EN - Figure 3. Power Ready Detection and Power On Reset (POR) Precise Reference Current Generation The RT8167A includes extensive analog circuits inside the controller. These analog circuits need very precise reference voltage/current to drive these analog devices. The RT8167A will auto-generate a 2.14V voltage source at IBIAS pin, and a 53.6kΩ resistor is required to be connected between IBIAS and analog ground. Through this connection, the RT8167A generates a 40μA current from IBIAS pin to analog ground and this 40μA current will be mirrored inside the RT8167A for internal use. Other types of connection or other values of resistance applied at the IBIAS pin may cause failure of the RT8167A's analog circuits. Thus a 53.6kΩ resistor is the only recommended component to be connected to the IBIAS pin. The resistance accuracy of this resistor is recommended to be at least 1%. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 Current Mirror 2.14V + - During start-up, the RT8167A detects the voltage on the voltage input pins : VCC and EN. When VCC > VUVLO, the RT8167A will recognize the power state of system to be ready (POR = high) and wait for enable command at EN pin. After POR = high and EN > VENTH, the RT8167A will enter start-up sequence for both CORE VR and GFX VR. If the voltage on any voltage pin drops below POR threshold (POR = low), the RT8167A will enter power down sequence and all the functions will be disabled. SVID will be invalid within 300μs after chip becomes enabled. All the protection latches (OVP, OCP, UVP, OTP) will be cleared only after POR = low. EN = low will not clear these latches. + - IBIAS 53.6k Figure 4. IBIAS Setting ICCMAX, ICCMAXA and TMPMAX The RT8167A provides ICCMAX, ICCMAXA and TMPMAX pins for platform users to set the maximum level of output current or VR temperature: ICCMAX for CORE VR maximum current, ICCMAXA for GFX VR maximum current, and TMPMAX for CORE VR maximum temperature. To set ICCMAX, ICCMAXA and TMPMAX, platform designers should use resistive voltage dividers on these three pins. The current of the divider should be several milli-Amps to avoid noise effect. The three items share the same algorithms : the ADC divides 5V into 255 levels. Therefore, LSB = 5/255 = 19.6mV, which means 19.6mV applied to ICCMAX pin equals to 1A setting. For example, if a platform designer wants to set TMPMAX to 120°C, the voltage applied to TMPMAX should be 120 x 19.6mV = 2.352V. The ADC circuit inside these three pins will decode the voltage applied and store the maximum current/ temperature setting into ICC_MAX and Temp_Max registers. The ADC monitors and decodes the voltage at these three pins only after EN = high. If EN = low, the RT8167A will not take any action even when the VR output current or temperature exceeds its maximum setting at these ADC pins. The maximum level settings at these ADC pins are different from over current protection or over temperature protection. That means, these maximum level setting pins are only for platform users to define their system operating conditions and these messages will only be utilized by the CPU. is a registered trademark of Richtek Technology Corporation. www.richtek.com 29 RT8167A V CC VINI_CORE and VINI_GFX Setting The initial start up voltage (VINI_CORE, VINI_GFX) of the RT8167A can be set by platform users through SETINI and SETINIA pins. Voltage divider circuit is recommended to be applied to SETINI and SETINIA pins. The VINI_CORE/ VINI_GFX relate to SETINI/SETINIA pin voltage setting as shown in Figure 6. Recommended voltage setting at SETINI and SETINIA pins are also shown in Figure 6. ICCMAX A/D Converter ICCMAXA TMPMAX Figure 5. ADC Pins Setting VCC (5V) VINI_CORE = 1.1V VINI_GFX = 1.1V VINI_CORE V INI_GFX Recommended SETINI/SETINIA Pin Voltage 1.1V 5 x VCC≒3.125V or VCC 8 3 x VCC≒1.875V 8 3 x VCC≒0.9375V 16 1/2 VCC VINI_CORE = 1V VINI_GFX = 1V VINI_CORE = 0.9V VINI_GFX = 0.9V VINI_CORE = 0V VINI_GFX = 0V 1/4 VCC 1V 0.9V 1/8 VCC 0V 1 x VCC≒0.3125V or GND 16 GND Figure 6. SETINI and SETINIA Pin Voltage Setting Start Up Sequence The RT8167A utilizes internal soft-start sequence which strictly follows Intel VR12/IMVP7 start up sequence specifications. After POR = high and EN = high, a 300μs delay is needed for the controller to determine whether all the power inputs are ready for entering start up sequence. If pin voltage of SETINI/SETINIA is zero, the output voltage of CORE/GFX VR is programmed to stay at 0V. If pin voltage of SETINI/SETINIA is not zero, VR output voltage will ramp up to initial boot voltage (VINI_CORE, VINI_GFX) after both POR = high and EN = high. After the output voltage of CORE/GFX VR reaches target initial boot voltage, the controller will keep the output voltage at the initial boot voltage and wait for the next SVID commands. After the RT8167A receives valid VID code (typically SetVID_Slow command), the output voltage will ramp up/down to the target voltage with specified slew rate. After the output Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 30 voltage reaches the target voltage, the RT8167A will send out VR_READY signal to indicate the power state of the RT8167A is ready. The VR_READY circuit is an opendrain structure so a pull-up resistor is recommended for connecting to a voltage source. Power Down Sequence Similar to the start up sequence, the RT8167A also utilizes a soft shutdown mechanism during turn-off. After POR = low, the internal reference voltage (positive terminal of compensation EA) starts ramping down with 3.125mV/μs slew rate, and output voltage will follow the reference voltage to 0V. After output voltage drops below 0.2V, the RT8167A shuts down and all functions are disabled. The VR_READY will be pulled down immediately after POR = low. is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A VCC POR EN EN Chip (Internal Signal) SVID Valid XX xx 300µs 0.2V VCORE CORE VR Operation Mode Off VGFX GFX VR Operation Mode CCM SVID defined Off CCM 0.2V Off CCM SVID defined Off CCM 100µs VR_READY VRA_READY 100µs Figure 7 (a). Power sequence for RT8167A (VINI_CORE = VINI_GFX = 0V) VCC POR EN EN Chip (Internal Signal) SVID 300µs xx Valid XX 250µs VINI_CORE 0.2V VCORE CORE VR Operation Mode Off CCM SVID defined Off CCM 100µs VR_READY 50µs VINI_GFX VGFX GFX VR Operation Mode 0.2V Off CCM SVID defined CCM Off 100µs VRA_READY Figure 7 (b). Power sequence for RT8167A (VINI_CORE ≠ 0, VINI_GFX ≠ 0V) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 31 RT8167A Disable GFX VR : Before EN = High GFX VR enable or disable is determined by the internal circuitry that monitors the ISENAN voltage during start up. Before EN = high, GFX VR detects whether the voltage of ISENAN is higher than “VCC − 1V” to disable GFX VR. The unused driver pins can be connected to GND or left floating. GFX VR Forced-DEM Function Enable : After VRA_Ready = High Similar to the valley current mode control with finite compensator gain, the high side MOSFET on-time is determined by the CCRCOT PWM generator. When load current increases, VCS increases, the steady state COMP voltage also increases which makes the output voltage decrease, thus achieving AVP. Droop Function Enable The GFX VR's forced-DEM function can be enabled or disabled with GFXPS2 pin. The RT8167A detects the voltage of GFXPS2 for forced-DEM function. If the voltage at GFXPS2 pin is higher than 4.3V, the GFX VR operates in forced-DEM. If this voltage is lower than 0.7V, the GFX VR follows SVID power state command. The CORE/GFX VR's droop function can be enabled or disabled with DRPEN/DRPENA pin. After EN = high within 10μs, the RT8167A will source 80μA current from DRPEN/ DRPENA pin to the external resistor to determine the voltage level. If the voltage at DRPEN/DRPENA pin is lower than 3.5V, then the VR will operate in droop-disabled mode. If the voltage is higher than 4V, then the VR will operate in droop-enabled mode. Loop Control Droop Setting (with Temperature Compensation) Both CORE and GFX VR adopt Richtek's proprietary GNAVPTM topology. G-NAVPTM is based on the finite-gain valley current mode with CCRCOT (Constant Current Ripple Constant On Time) topology. The output voltage, VCORE or VGFX, will decrease with increasing output load current. The control loop consists of PWM modulator with power stage, current sense amplifier and error amplifier as shown in Figure 8. It's very easy to achieve the Active Voltage Positioning (AVP) by properly setting the error amplifier gain due to the native droop characteristics. The target is to have VIN High Side MOSFET UGATEx GFX/CORE VR CCRCOT PWM Generator Driver Logic Control L PHASEx VOUT (VCORE/VGFX) RC LGATEx Low Side MOSFET RX CX C (1) Then solving the switching condition VCOMPx = VCSx in Figure 8 yields the desired error amplifier gain as A V = R2 = R1 AI × RSENSE RDROOP (2) where AI is the internal current sense amplifier gain and RSENSE is the current sense resistance. If no external sense resistor is present, the DCR of the inductor will act as RSENSE. RDROOP is the resistive slope value of the converter output and is the desired static output impedance. - + CMP VOUT = VREFx − ILOAD x RDROOP VCSx + Ai - V OUT ISENxP A V2 > A V1 ISENxN CByp C2 C1 COMPx R2 R1 CORE/GFX VR VCC_SENSE A V2 FBx A V1 + - EA + RGNDx CORE/GFX VR VSS_SENSE VREFx 0 Load Current Figure 9. Error Amplifier Gain (AV) Influence on VOUT Figure 8. Simplified Schematic for Droop and Remote Sense in CCM Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 32 Accuracy is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A Since the DCR of inductor is temperature dependent, it affects the output accuracy in high temperature conditions. Temperature compensation is recommended for the lossless inductor DCR current sense method. Figure 10 shows a simple but effective way of compensating the temperature variations of the sense resistor using an NTC thermistor placed in the feedback path. C2 COMPx R1b FBx + EA + R2 C1 RGNDx R1a NTC coefficient with RSENSE. Hence A V, HOT RSENSE, HOT = A V, COLD RSENSE, COLD (3) From (2), we can have Av at any temperature (T) as R2 A V, T = R1a / /RNTC, T + R1b where AV, 25°C is the error amplifier gain at room temperature obtained from (2). R1b can be obtained by substituting (7) to (3), R1b = RSENSE, HOT × (R1a // RNTC, HOT ) − (R1a // RNTC, COLD ) RSENSE, COLD ) ( )} (4) (5) where RNTC, 25 is the thermistor's nominal resistance at room temperature, β (beta) is the thermistor's material constant in Kelvins, and T is the thermistor's actual temperature in Celsius. The DCR value at different temperatures can be calculated using the equation below : DCRT = DCR25 x [1+0.00393 x (T-25)] (6) where 0.00393 is the temperature coefficient of copper. For a given NTC thermistor, solving (4) at room temperature (25°C) yields Copyright © 2012 Richtek Technology Corporation. All rights reserved. (8) Optimized compensation of the CORE VR allows for best possible load step response of the regulator's output. A type-I compensator with one pole and one zero is adequate for a proper compensation. Figure 10 shows the compensation circuit. It was previously mentioned that to determine the resistive feedback components of error amplifier gain, C1 and C2 must be calculated for the compensation. The target is to achieve constant resistive output impedance over the widest possible frequency range. The pole frequency of the compensator must be set to compensate the output capacitor ESR zero : fP = The standard formula for the resistance of NTC thermistor as a function of temperature is given by : 1 β⎡ − 1 ⎤ 298 ⎦⎥ ⎣⎢ T+273 (7) Loop Compensation VSS_SENSE Usually, R1a is set to equal RNTC (25°C), while R1b is selected to linearize the NTC's temperature characteristic. For a given NTC, the design would be to obtain R1b and R2 and then C1 and C2. According to (2), to compensate the temperature variations of the sense resistor, the error amplifier gain (AV) should have the same temperature DS8167A-00 January 2012 x (R1b + R1a // RNTC, 25) VCC_SENSE Figure 10. Loop Setting with Temperature Compensation {( 25 RSENSE, HOT ⎞ ⎛ ⎜1 − R ⎟ SENSE, COLD ⎠ ⎝ VREFx RNTC, T = RNTC, 25 e R2 = AV, 1 2 × π × C × RC (9) where C is the capacitance of the output capacitor and RC is the ESR of the output capacitor. C2 can be calculated as follows : C × RC (10) C2 = R2 The zero of compensator has to be placed at half of the switching frequency to filter the switching-related noise. Such that, 1 C1 = (11) R1b + R1a // R ( NTC, 25°C ) × π × fSW TON Setting High frequency operation optimizes the application by trading off efficiency due to higher switching losses with smaller component size. This may be acceptable in ultraportable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low frequency operation offers the best overall efficiency at is a registered trademark of Richtek Technology Corporation. www.richtek.com 33 RT8167A the expense of component size and board space. Figure 11 shows the on-time setting circuit. Connect a resistor (RTONSETx) between VIN and TONSETx to set the on-time of UGATEx : -12 28 × 10 × RTONSETx (12) tONx (VREFx < 1.2V) = VIN − VREFx where tONx is the UGATEx turn on period, VIN is the input voltage of converter, and VREFx is the internal reference voltage. When VREFx is larger than 1.2V, the equivalent switching frequency may be over the maximum design range, making it unacceptable. Therefore, the VR implements a pseudoconstant-frequency technology to avoid this disadvantage of CCRCOT topology. When VREFx is larger than 1.2V, the on-time equation will be modified to : tONx (VREFx ≥ 1.2V) = 23.33 × 10 -12 × RTONSETx × VREFx VIN − VREFx For better efficiency of the given load range, the maximum switching frequency is suggested to be : 1 fS(MAX) (kHz) = × tON − tHS−Delay VREFx(MAX) + ILOAD(MAX) × ⎡⎣RON _ LS−FET + DCR − RDROOP ⎤⎦ VIN(MAX) + ILOAD(MAX) × ⎡⎣RON _ LS−FET − RON _ HS−FET ⎤⎦ (14) where fS(MAX) is the maximum switching frequency, tHSDelay is the turn on delay of high side MOSFET, VREFx(MAX) is the maximum application DAC voltage of application, V IN(MAX) is the maximum application input voltage, ILOAD(MAX) is the maximum load of application, RON_LS-FET is the low side MOSFET RDS(ON), RON_HS-FET is the high side MOSFET RDS(ON), DCRL is the inductor DCR, and RDROOP is the load line setting. www.richtek.com 34 TONSETx RTONSETx R1 VIN C1 VREFx On-Time Figure 11. On-Time Setting with RC Filter Differential Remote Sense Setting The CORE/GFX VR includes differential, remote-sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts. The CPU contains on-die sense pins CORE/ GFX VCC_SENSE and VSS_SENSE. Connect RGNDx to CORE/ GFX VSS_SENSE. Connect FBx to CORE/GFX VCC_SENSE with a resistor to build the negative input path of the error amplifier. The precision voltage reference VREFx is referred to RGND for accurate remote sensing. (13) On-time translates roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in external high side MOSFET. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only in CCM during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, PHASEx goes high earlier than normal, extending the on-time by a period equal to the high side MOSFET rising dead time. Copyright © 2012 Richtek Technology Corporation. All rights reserved. GFX/CORE VR CCRCOT PWM Generator Current Sense Setting The current sense topology of the CORE/GFX VR is continuous inductor current sensing. Therefore, the controller can be less noise sensitive. Low offset amplifiers are used for loop control and over current detection. The internal current sense amplifier gain (AI) is fixed to be 10. The ISENxP and ISENxN denote the positive and negative input of the current sense amplifier. Users can either use a current sense resistor or the inductor's DCR for current sensing. Using inductor's DCR allows higher efficiency as shown in Figure 12. To let L = R ×C (15) X X DCR then the transient performance will be optimum. For example, choose L = 0.36μH with 1mΩ DCR and CX = 100nF, to yields for RX : 0.36μH RX = = 3.6kΩ (16) 1mΩ × 100nF VOUT (VCORE/VGFX) PHASEx L RX VCSx AI + - DCR CX ISENxP ISENxN CByp Figure 12. Lossless Inductor Sensing is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A Considering the inductance tolerance, the resistor RX has to be tuned on board by examining the transient voltage. If the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, RX is too small. Vice versa, if the resistance is too large the output voltage transient will only have a small initial dip and the recovery will be too fast, causing a ring-back. Using current-sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. Considering the equivalent inductance (LESL) of the current sense resistor, a RC filter is recommended. The RC filter calculation method is similar to the above-mentioned inductor DCR sensing method. No-Load Offset The RT8167A provides a no-load offset function which has four-level offsets of output voltage for the CORE/GFX VR. The no-load offset function is implemented through the OFSx pin. A voltage divider circuit is recommended to be applied to OFSx pins. The output offset voltage relation to the OFSx pin voltage setting is shown in Figure 13. Recommended voltage setting at OFS and OFSA pins are also shown in Figure 13. After receiving SetPS command, the CORE/GFX VR will immediately change to the new operation state. When VR receives SetPS command of PS2 operation mode, the VR operates as a DEM controller. If VR receives dynamic VID change command (SetVID), VR will automatically enter PS0 operation mode. After output voltage reaches target voltage, VR will stay at PS0 state and ignore former SetPS command. Only by re-sending SetPS command after SetVID command will VR be forced into PS2 operation state again. Thermal Monitoring and Temperature Reporting CORE/GFX VR provides thermal monitoring function via sensing TSEN pin voltage. Through the voltage divider resistors R1, R2, R3 and RNTC, the voltage of TSEN will be proportional to VR temperature. When VR temperature rises, the TSENx voltage also rises. The ADC circuit of VR monitors the voltage variation at TSENx pin from 1.47V to 1.89V with 55mV resolution, and this voltage is decoded into digital format and stored into the Temperature Zone register. VCC VCC (5V) Offset Voltage =100mV 0.64 VCC Offset Voltage = 50mV 0.48 VCC Offset Voltage = -50mV 0.32 VCC Offset Voltage = -100mV 0.16 VCC R1 Offset Voltage 100mV Recommended OFS/OFSA Pin Voltage 0.8 x VCC≒4V or VCC 50mV 0.56 x VCC≒2.8V −50mV 0.4 x VCC≒2V −100mV 0.24 x VCC≒1.2V 0mV GND Offset Voltage = 0mV GND Figure 13. OFS and OFSA Pins Voltage Setting Operation Mode Transition The RT8167A supports operation mode transition function in CORE/GFX VR for the SetPS command of Intel's VR12/ IMVP7 CPU. The default operation mode of the RT8167A's CORE/GFX VR is PS0, which is CCM operation. The other operation mode is PS2 (DEM operation). Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 RNTC R2 TSENx R3 Figure 14. Thermal Monitoring Circuit To meet Intel's VR12/IMVP7 specification, platform users have to set the TSEN voltage to meet the temperature variation of VR from 75% to 100% VR max temperature. For example, if the VR max temperature is 100°C, platform users have to set the TSEN voltage to be 1.4875V when VR temperature reaches 75°C and 1.8725V when VR temperature reaches 100°C. Detailed voltage setting versus temperature variation is shown in Table 2. Thermometer code is implemented in the Temperature Zone register. is a registered trademark of Richtek Technology Corporation. www.richtek.com 35 RT8167A TSEN Pin Voltage 1.855 ≤ VTSEN 1.800 ≤ VTSEN ≤ 1.835 1.745 ≤ VTSEN ≤ 1.780 1.690 ≤ VTSEN ≤ 1.725 1.635 ≤ VTSEN ≤ 1.670 1.580 ≤ VTSEN ≤ 1.615 1.525 ≤ VTSEN ≤ 1.560 1.470 ≤ VTSEN ≤ 1.505 VTSEN < 1.470 Temperature_Zone Register Content 1111_1111 0111_1111 0011_1111 0001_1111 0000_1111 0000_0111 0000_0011 0000_0001 0000_0000 The RT8167A supports two temperature reporting, VRHOT(hardware reporting) and ALERT(software reporting), to fulfill VR12/IMVP7 specification. VRHOT is an open-drain structure which sends out active-low VRHOT signals. When TSEN voltage rises above 1.855V (100% of VR temperature), the VRHOT signal will be set to low. When TSEN voltage drops below 1.8V (97% of VR temperature), the VRHOT signal will be reset to high. When TSEN voltage rises above 1.8V (97% of VR temperature), The RT8167A will update the bit1 data from 0 to 1 in the Status_1 register and assert ALERT. When TSEN voltage drops below 1.745V (94% of VR temperature), VR will update the bit1 data from 1 to 0 in the Status_1 register and assert ALERT. The temperature reporting function for the GFX VR can be disabled by pulling TSENA pin to VCC in case the temperature reporting function for the GFX VR is not used or the GFX VR is disabled. When the GFX VR's temperature reporting function is disabled, the RT8167A will reject the SVID command of getting the Temperature_Zone register content of the GFX VR. However, note that the temperature reporting function for the CORE VR is always active. CORE VR's temperature reporting function can not be disabled by pulling TSEN pin to VCC. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 36 Current Monitoring and Current Reporting The CORE/GFX VR provides current monitoring function via sensing the voltage difference of IMONFBx pin and output voltage. Figure 15 shows the current monitoring setting principle. The equivalent output current will be sensed from IMONFBx pin and mirrored to IMONx pin. The resistor connected to IMONx pin determines voltage gain of the IMON output. Current Monitor VREFx + 2 (VISENxP - VISENxN) 0LL EN IMIrror VREFx VCC_SENSE + Table 2. Temperature Zone Register Comparator Trip Points SVID Temperatures Scaled to maximum = VRHOT Thermal 100% Alert Voltage Represents Assert bit Minimum Level b7 b6 b5 b4 b3 b2 b1 b0 100% 97% 94% 91% 88% 85% 82% 75% 1.745 1.69 1.635 1.58 1.52 1.47 1.855V 1.8V V V V V 5V V RIMONFB IMONFBx VIMON IMONx RIMON C1 Figure 15. Current Monitor Setting Principle The voltage of IMONFBx is different when VR operates in droop enable mode and droop disable mode : Droop enable mode : VIMONFBx = VREFx (17) Droop disable mode : VIMONFBx = VREFx + 2 (VISENxP − VISENxN) (18) The current monitor indicator VIMON equation is shown as: VIMON = (IIMONFBx − VCC _ SENSE ) × RIMON RIMONFB (19) where VIMONFBx is the pin voltage of IMONFBx, VCC_SENSE is the output voltage of CORE/GFX VR, and RIMON and RIMONFB are the current monitor current setting resistors. The maximum voltage of current monitoring will be limited at 3.3V. Platform designers have to design the RIMON to meet the maximum voltage of IMON at full load. When VR operates in droop enable mode, find RIMON and RIMONFB based on : VIMON(MAX) RIMON = (20) RIMONFB I(MAX) × RDROOP where VIMON(MAX) is the maximum voltage at full load, RDROOP is the load line setting of VR, and IMAX is the full load current of VR. is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A When VR operate in droop disable mode, RIMON and RIMONFB can be obtained according to equation below : VIMON(MAX) RIMON = (21) RIMONFB I(MAX) × RSENSE × 2 where VIMON(MAX) is the maximum voltage at full load, RSENSE is the equivalent resistance of current sense circuit, and IMAX is the full load current of VR. The ADC circuit of the CORE/GFX VR monitors the voltage variation at the IMON pin from 0V to 3.3V, and this voltage is decoded into digital format and stored into the Output_Current register. The ADC divides 3.3V into 255 levels, so LSB = 3.3V/255 = 12.941mV. Platform designers should design VIMONx to be 3.3V at ICCMAX. For example, when load current = 0.5 x ICCMAX, VIMON = 1.65V and Output_Current register = 7Fh. The current limit is triggered when inductor current exceeds the current limit threshold ILIMIT, defined by VOCSET. The driver will be forced to turn off UGATE until the over current condition is cleared. If the over current condition remains valid for 15 PWM cycles, VR will trigger OCP latch. Latched OCP forces both UGATE and LGATE to go low. When OCP is triggered in one of VRs, the other VR will enter into soft shutdown sequence. The OCP latch mechanism will be masked when VRx_READY = low, which means that only the current limit will be active when VOUT is ramping up to initial voltage (or VREFx). If inductor DCR is used as the current sense component, then temperature compensation is recommended for protection under all conditions. Figure 17 shows a typical OCP setting with temperature compensation. VCC The IMON pin is the output of internal operational amplifier and sends out IMON signal. When IMON voltage rises above 3.3V (100% of VR output current), the VR will update the bit2 data from 0 to 1 in the Status_1 register. The 1 in bit2 of Status_1 register will be cleared to 0 only after the master (usually Intel's VR12/IMVP7 CPU) executes GetReg command to Status_1 register. ROC1a NTC ROC1b OCSETx ROC2 Figure 17. OCP Setting with Temperature Compensation Over Current Protection The CORE/GFX VR compares a programmable current limit set point to the voltage from the current sense amplifier output for Over Current Protection (OCP). The voltage applied to OCSETx pin defines the desired peak current limit threshold ILIMIT : VOCSET = 48 x ILIMIT x RSENSE (22) Connect a resistive voltage divider from VCC to GND, with the joint of the resistive divider connected to OCSET pin as shown in Figure 16. For a given ROC2, then ⎛ VCC ⎞ ROC1 = ROC2 × ⎜ − 1⎟ V ⎝ OCSET ⎠ VOCSET, HOT RSENSE, HOT = VOCSET, COLD RSENSE, COLD (24) According to the basic circuit calculation, VOCSET can be obtained at any temperature : VOCSET, T = VCC × (23) ROC2 ROC1a / /RNTC, T + ROC1b + ROC2 (25) VCC ROC1 OCSETx ROC2 Figure 16. OCP Setting without Temperature Compensation Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 Usually, ROC1a is selected to be equal to the thermistor's nominal resistance at room temperature. Ideally, VOCSET is assumed to have the same temperature coefficient as RSENSE (Inductor DCR) : Re-write (24) from (25), to get VOCSET at room temperature ROC1a // RNTC, COLD + ROC1b + ROC2 RSENSE, HOT = ROC1a // RNTC, HOT + ROC1b + ROC2 RSENSE, COLD (26) VOCSET, 25 = VCC × ROC1a ROC2 / /RNTC, 25 + ROC1b + ROC2 (27) is a registered trademark of Richtek Technology Corporation. www.richtek.com 37 RT8167A Under Voltage Lock Out (UVLO) Solving (26) and (27) yields ROC1b and ROC2 ROC2 = α × REQU, HOT − REQU, COLD + (1 − α ) × REQU, 25 VCC × (1 − α ) VOCSET, 25 ROC1b = (α − 1) × R2 + α × REQU, HOT − REQU, COLD (1 − α ) (28) (29) where α= RSENSE, HOT DCR25 × [1 + 0.00393 × (THOT − 25)] = RSENSE, COLD DCR25 × [1 + 0.00393 × (TCOLD − 25)] REQU, T = ROC1a // RNTC, T The switching frequency and ripple current determine the inductor value as follows : LMIN = VIN − VOUT ×t IRipple(MAX) ON (32) where tON is the UGATE turn on period. (31) Higher inductance induces less ripple current and hence higher efficiency. However, the tradeoff is a slower transient response of the power stage to load transients. This might increase the need for more output capacitors, thus driving up the cost. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must be large enough not to be saturated at the peak inductor current. The over voltage protection circuit of CORE/GFX VR monitors the output voltage via the ISENxN pin. The supported maximum operating VID of VR (V(MAX)) is stored in the VOUT(MAX) register. Once VISENxN exceeds “V(MAX) + 200mV”, OVP is triggered and latched. VR will try to turn on low side MOSFETs and turn off high side MOSFETs to protect CPU. When OVP is triggered by the one of the VRs, the other VR will enter soft shutdown sequence. A 10μs delay is used in OVP detection circuit to prevent false trigger. Negative Voltage Protection (NVP) During OVP latch state, both CORE/GFX VRs also monitor ISENxN pin for negative voltage protection. Since the OVP latch will continuously turn on low side MOSFET of VR, VR may suffer negative output voltage. Therefore, when the voltage of ISENxN drops below −0.05V after triggering OVP, VR will turn off low side MOSFETs while high side MOSFETs remain off. The NVP function will be active only after OVP is triggered. Under Voltage Protection (UVP) Both CORE/GFX VR implement Under Voltage Protection (UVP). If ISENxN is less than VREFx by 300mV + VOFFSET, VR will trigger UVP latch. The UVP latch will turn off both high side and low side MOSFETs. When UVP is triggered by one of the VRs, the other VR will enter into soft shutdown sequence. The UVP mechanism is masked when VRx_READY = low. www.richtek.com 38 Inductor Selection (30) Over Voltage Protection (OVP) Copyright © 2012 Richtek Technology Corporation. All rights reserved. During normal operation, if the voltage at the VCC pin drops below UVLO falling edge threshold, both VR will trigger UVLO. The UVLO protection forces all high side MOSFETs and low side MOSFETs off to turn off. Output Capacitor Selection Output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output capacitors can be found, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. Latter ones are for mid-frequency decoupling with very small ESR and ESL values while the bulk capacitors have to provide enough stored energy to overcome the low-frequency bandwidth gap between the regulator and the CPU. Layout Considerations Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flushed against one another. Follow these guidelines for optimum PC board layout : is a registered trademark of Richtek Technology Corporation. DS8167A-00 January 2012 RT8167A ` Keep the high current paths short, especially at the ground terminals. ` Keep the power traces and load connections short. This is essential for high efficiency. ` When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharging path. ` Place the current sense component close to the controller. ISENxP and ISENxN connections for current limit and voltage positioning must be made using Kelvin sense connections to guarantee the current sense accuracy. The PCB trace from the sense nodes should be parallel to the controller. ` Route high-speed switching nodes away from sensitive analog areas (COMPx, FBx, ISENxP, ISENxN, etc...) ` Special attention should be paid in placing the DCR current sensing components. The DCR current sensing capacitor and resistors must be placed close to the controller. ` The capacitor connected to the ISEN1N/ISENAN for noise decoupling is optional and it should also be placed close to the ISEN1N/ISENAN pin. ` The NTC thermistor should be placed physically close to the inductor for better DCR thermal compensation. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8167A-00 January 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 39 RT8167A Outline Dimension 2 1 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 5.950 6.050 0.234 0.238 D2 4.250 4.350 0.167 0.171 E 5.950 6.050 0.234 0.238 E2 4.250 4.350 0.167 0.171 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 48L QFN 6x6 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 40 DS8167A-00 January 2012