® RT9259 12V Synchronous Buck PWM DC/DC and Linear Power Controller General Description Features The RT9259 is a dual-channel DC/DC controller specifically designed to deliver high quality power where 12V power source is available. This part consists of a synchronous buck controller and an LDO controller. The synchronous buck controller integrates MOSFET drivers that support 12V + 12V bootstrapped voltage for high efficiency power conversion. The bootstrap diode is built-in to simplify the circuit design and minimize external part count. The LDO controller drives an external N-MOSFET for lower power requirement. z Other features include adjustable operation frequency, internal soft start, under voltage protection, over current protection and shut down function. With the above functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solution. This part comes to VQFN-16L 4x4, SOP14 and SSOP-16 packages. z z z z z z z z z z z Ordering Information RT9259 Package Type S : SOP-14 A : SSOP-16 QV : VQFN-16 4x4 (V-Type) z Applications z z Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) z Note : z Richtek products are : z ` RoHS compliant and compatible with the current require- Single 12V Bias Supply Support Dual Channel Power Conversion ` One Synchronous Rectified Buck PWM Controller ` One Linear Controller Both Controllers Drive Low Cost N-MOSFETs Adjustable Frequency from 150kHz to 1MHz and Free-Run Frequency at 230kHz Small External Component Count Output Voltage Regulation `PWM Controller : ±1% Accuracy `LDO Controller : ±2% Accuracy Two Internal VREF Power Support Lower to 0.8V Adjustable External Compensation Linear Controller Drives N-MOSFET Pass Transistor Fully-Adjustable Outputs Under Voltage Protection for Both Outputs Over Current Fault Monitor on MOSFET; No Current Sense Resistor is Required RoHS Compliant and 100% Lead (Pb)-Free z Graphic Card GPU, Memory Core Power Graphic Card Interface Power Motherboard, Desktop and Servers Chipset and Memory Core Power IA Equipments Telecomm Equipments High Power DC/DC Regulators ments of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9259-05 March 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9259 Pin Configurations SOP-14 UGATE PHASE PGND LGATE NC NC VCC12 VCC12 UGATE PHASE 16 15 14 13 12 11 10 9 2 3 4 5 6 7 8 16 15 14 13 COMP FB DRV FBL 1 12 PGND 2 11 3 10 LGATE NC NC 17 4 9 5 SSOP-16 6 7 VCC12 NC 2 3 4 5 6 7 BOOT RT_DIS COMP FB DRV FBL GND GND UGATE PHASE PGND LGATE NC NC VCC12 NC 14 13 12 11 10 9 8 GND BOOT RT_DIS COMP FB DRV FBL GND RT_DIS BOOT (TOP VIEW) 8 VQFN-16L 4x4 Marking Information RT9259PA RT9259PS RT9259PS : Product Number RT9259 PSYMDNN RT9259PA : Product Number RT9259 PAYMDNN YMDNN : Date Code YMDNN : Date Code RT9259PQV RT9259GS RT9259GS : Product Number RT9259 GSYMDNN A5- : Product Code YMDNN : Date Code YMDNN : Date Code A5-YM DNN Typical Application Circuit VCC 12V VIN1 3.3V/5V/12V CIN RT9259 VIN2 5V to 12V BOOT Q3 VOUT2 COUT2 VCC12 DRV FBL RT_DIS UGATE Q1 LGATE LOUT1 VOUT1 PHASE Q2 COUT PGND GND FB NC NC Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 COMP is a registered trademark of Richtek Technology Corporation. DS9259-05 March 2012 RT9259 Functional Pin Description Pin No. RT9259 S RT9259 A RT9259PQV Pin Name Pin Function 1 1 15 BOOT Bootstrap supply for the upper gate driver. Connect the bootstrap capacitor between BOOT pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. 2 2 16 RT_DIS Connect a resistor from RT_DIS to GND to set frequency. In addition, if this pin is pulled down towards GND, it will disable both regulator outputs until released. 3 3 1 COMP Buck converter external compensation. This pin is used to compensate the control loop of the buck converter. 4 4 2 FB Buck converter feedback voltage. This pin is the inverting input of the PWM error amplifier. FB senses the switcher output through an external resistor divider network. 5 5 3 DRV Connect this pin to the gate of an external MOSFET. This pin provides the drive for the linear regulator’s pass MOSFET. 6 6 4 FBL Linear regulator feedback voltage. This pin is the inverting input of the LDO error amplifier and protection monitor. Connect this pin to an external resistor divider network of the linear regulator. 7 7, 8 5 GND Ground. 8 9, 10 7 VCC12 Connect this pin to a well-decoupled 12V bias supply. It is also the positive supply for the lower gate driver, LGATE. 9, 10 11, 12 6, 8, 9, 10, NC 17 (Exposed Pad) No Internal Connection. 11 13 11 LGATE Lower gate driver output. Connect to the gate of the low-side power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. 12 14 12 PGND Power ground return for the lower gate driver. 13 15 13 PHASE Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. 14 16 14 UGATE Connect this pin to a well-decoupled 12V bias supply. It is also the positive supply for the lower gate driver, LGATE. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9259-05 March 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9259 Function Block Diagram VCC12 Voltage Reference VREF2 Power On Reset Bias POR VCC12 + + + - Inhibit 5VDD 0.4V FBL DRV 5V Regulator OC Soft-Start & Fault Logic + SSE + 0.4V 40uA ROCSET 20k PH_M - 1.5V + BOOT UGATE Shutdown SSE VREF1 RT_DIS PHASE + + EA - + - Driver Logic PWM LGATE Oscillator PGND GND FB COMP Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9259-05 March 2012 RT9259 Absolute Maximum Ratings (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------- −0.3V to 15V BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 15V z PHASE to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to 15V < 20ns -------------------------------------------------------------------------------------------------- −5V to 30V z LGATE to GND DC -------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V) < 20ns -------------------------------------------------------------------------------------------------- (GND − 5V) to (VCC + 5V) z UGATE to GND DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V) < 20ns -------------------------------------------------------------------------------------------------- (VPHASE − 5V) to (VBOOT + 5V) z PWM to GND ------------------------------------------------------------------------------------------ −0.3V to 7V z Power Dissipation, PD @ TA = 25°C SOP-14 ------------------------------------------------------------------------------------------------- 1.000W SSOP-16 ----------------------------------------------------------------------------------------------- 0.909W VQFN-16L 4x4 ---------------------------------------------------------------------------------------- 1.852W z Package Thermal Resistance (Note 2) SOP-14, θJA -------------------------------------------------------------------------------------------- 100°C/W SSOP-16, θJA ------------------------------------------------------------------------------------------ 110°C/W VQFN-16L 4x4, θJA ----------------------------------------------------------------------------------- 54°C/W z Junction Temperature -------------------------------------------------------------------------------- 150°C z Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C z Storage Temperature Range ----------------------------------------------------------------------- −40°C to 150°C z ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------- 2kV MM (Machine Mode) --------------------------------------------------------------------------------- 200V z z Recommended Operating Conditions z z z (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------- 12V ± 10% Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 12V, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit -- 12 15 V 8.8 9.6 10.4 V 0.4 0.78 1.2 V -- 3 -- mA Supply Input Power Supply Voltage VCC Power On Reset V VCCRTH Power On Reset Hysteresis V VCCHYS Power Supply Current IVCC Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9259-05 March 2012 V CC Rising UGATE, LGATE Open is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9259 Parameter Symbol Test Conditions Min Typ Max Unit 250 300 350 kHz -- 1.6 -- V Oscillator Free Running Frequency f OSC RRT = 110kΩ Ramp Amplitude Reference Voltage PWM Error Amplifier Reference VREF1 0.792 0.8 0.808 V Linear Driver Reference VREF2 0.784 0.8 0.816 V 70 88 -- dB 6 15 -- MHz 3 6 -- V/μs Error Amplifier DC Gain Gain-Bandwidth Product GBW Slew Rate SR C LOAD = 5pF Gate Driver Upper Drive Source RUGATE VBOOT − VPHASE = 12V, VBOOT − VUGATE = 1V -- 4 8 Ω Upper Drive Sink RUGATE VUGATE = 1V -- 4 8 Ω Lower Drive Source RLGATE VCC − VLGATE = 1V -- 4 6 Ω Lower Drive Sink RLGATE VLGATE = 1V -- 2 4 Ω 0.36 0.4 0.45 V Protection Under Voltage Protection VUVP Soft-Start Time Interval TSS 2 3 4 ms Over Current Threshold VOC -- −400 -- mV 0.35 0.4 -- V RT_DIS Shutdown Threshold Linear Regulator Output High Voltage VDRV 9.5 10.3 -- V Output Low Voltage VDRV -- 0.1 1 V Source Current IDRVSR 2 -- -- mA Sink Current IDRVSC 0.5 -- -- mA Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS9259-05 March 2012 RT9259 Typical Operating Characteristics Dead Time Dead Time No Load, Falling No Load, Rising UGATE UGATE VIN1 VIN1 PHASE PHASE (5V/Div) LGATE (5V/Div) LGATE Time (25ns/Div) Time (25ns/Div) OCP Power Off No Load UGATE V OUT1 (10V/Div) (2V/Div) V REF IL (10V/Div) LGATE (0.5A/Div) (10A/Div) IL (200mV/Div) Time (2.5ms/Div) Time (5μs/Div) Shut Down Start Up Full Load No Load VIN1 UGATE (20V/Div) (5V/Div) LGATE (10V/Div) RT_Dis (500mV/Div) V OUT1 (500mV/Div) PHASE RT_Dis (1V/Div) V OUT1 (500mV/Div) Time (5μs/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9259-05 March 2012 (10V/Div) Time (1ms/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9259 Start Up Start Up No Load ILOAD = 20A ILOAD (2.5A/Div) RT_Dis (500mV/Div) V OUT1 (500mV/Div) (500mV/Div) V OUT1 Time (1ms/Div) Time (1ms/Div) Transient Response Transient Response UGATE V OUT (20V/Div) (100mV/Div) (100mV/Div) VOUT1 (20V/Div) UGATE IL VIN1 = 12V, VOUT1 = 2V ILOAD = 1A to 20A (10A/Div) LDO (10A/Div) VIN1 = 12V, VOUT1 = 2V ILOAD = 20A to 1A IL Time (2.5μs/Div) Time (10μs/Div) Transient Response Under Voltage Protection VIN2 = 12V, VOUT2 = 2.5V ILOAD = 1A to 100mA VIN2 = 0V LDO LGATE (2mV/Div) (10V/Div) V OUT2 UGATE (20V/Div) IL COMP (500mV/Div) (0.5A/Div) (1V/Div) Time (100μs/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 V OUT2 Time (10ms/Div) is a registered trademark of Richtek Technology Corporation. DS9259-05 March 2012 RT9259 Application Information The RT9259 is a dual-channel DC/DC controller specifically designed to deliver high quality power where 12V power source is available. This part consists of a synchronous buck controller and an LDO controller. The synchronous buck controller integrates internal MOSFET drivers that support 12V+12V bootstrapped voltage for high efficiency power conversion. The bootstrap diode is built-in to simplify the circuit design and minimize external part count. The LDO controller drives an external N-MOSFET for lower power requirement. Internal 5VDD Regulator It is highly recommended to power the RT9259 with welldecoupled 12V to VCC12 pin. VCC12 powers the RT9259 control circuit, low side gate driver and bootstrap circuit for high side gate driver. A bootstrap diode is embedded to facilitates PCB design and reduce the total BOM cost. No external Schottky diode is required. The RT9259 integrates MOSFET gate drives that are powered from the VCC12 pin and support 12V + 12V driving capability. Converters that consist of RT9259 feature high efficiency without special consideration on the selection of MOSFETs. When let open, the free running frequency is 230kHz typically. Figure 1 shows the operation frequency vs. RRT for quick reference. 1400 1200 1000 f SW (kHz) Introduction 800 600 400 200 0 10 100 1000 RRT (kΩ) (kohm) Figure 1. RT vs. fsw at Low Frequency Shorting the RT_DIS pin to GND with an external signallevel MOSFET shuts down the device. This allows flexible power sequence control for specified application. The RT_DIS pin threshold voltage is 0.4V typically. VIN1 Detection An internal linear regulator regulates VCC12 input to a 5VDD voltage for internal control logic circuit. No external bypass capacitor is required for filtering the 5VDD voltage. This further facilitates PCB design and reduces the total BOM cost. The RT9259 continuously generates a 10kHz pulse train with 1μs pulse width to turn on the upper MOSFET for detecting the existence of VIN1 after VCC12V POR and RT_DIS enabled as shown in Figure 2. PHASE pin voltage is monitored during the detection duration. Power On Reset If the PHASE voltage crosses 1.5V four times, VIN1 existence is recognized and the RT9259 initiates its soft start cycle as described in next section. The RT9259 automatically initializes upon applying input power (at the VCC12) pin. The power on reset function (POR) continually monitors the input bias supply voltage at the VCC12 pin. The VCC12V POR level is typically 9.6V at VCC12V rising. Frequency Setting and Shut Down Connecting a resistor RRT from the RT_DIS pin to GND sets the operation frequency. The relation can be roughly expressed in the equation. fOSC ≅ 230kHz + 7700 (kHz) RRT Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9259-05 March 2012 VIN1 POR_H PHASE_M PHASE + - 1.5V UGATE 1st 2nd 3rd 4th PHASE waveform Internal Counter will count (VPHASE > 1.5V) four times (rising & falling) to recognize VIN1 is ready. Figure 2 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9259 Soft Start for Synchronous Buck Converter A built-in soft-start is used to prevent surge current from power supply input during power on (referring to the Functional Block Diagram). The error amplifier EA is a three-input device. SSE or VREF1 whichever is smaller dominates the behavior non-inverting input. The internal soft start voltage SSE linearly ramps up to about 4V after VIN1 existence is recognized with about 2ms delay. According, the output voltage ramps up smoothly to its target level. The rise time of output voltage is about 2ms as shown in Figure 3. VREF1 takes over the behavior EA when SSE > VREF1. VIN1 = 12V to 0V UGATE (20V/Div) FB (500mV/Div) VOUT (20V/Div) Time (10ms/Div) Figure 4. UVP triggered by FB SSE is also used for LDO soft start. LDO input voltage VIN2 MUST be ready before SSE starts to ramp up. Otherwise UVP function of LDO may be triggered and shut down the RT9259. VIN2 = 0V LGATE (10V/Div) UGATE (20V/Div) RT_DIS (500mV/Div) COMP (500mV/Div) UGATE (20V/Div) VOUT1 (500mV/Div) LGATE (10V/Div) VOUT1 (1V/Div) Time (10ms/Div) Time (1ms/Div) Figure 3 : Start up by RT_DIS Under Voltage Protection The voltages at FB and FBL pin are monitored for under voltage protection (UVP) after the soft start is completed. UVP is triggered if one of the feedback voltages is under (50% x VREFX) with a 30us delay. As shown in Figure 4, the RT9259 PWM controller is shut down when VFB drops lower than the UVP threshold. In Figure 5, the RT9259 shuts down after 4 time UVP hiccups triggered by FBL. Figure 5. UVP hiccups triggered by FBL Over Current Protection The RT9259 senses the current flowing through lower MOSFET for over current protection (OCP) by sensing the PHASE pin voltage as shown in the Functional Block Diagram. A 40μA current source flows through internal 20kΩ ROCSET to PHASE pin causes 0.8V voltage drop across the resistor. OCP is triggered if the voltage at PHASE pin (drop of lower MOSFET VDS) is lower than − 0.4V when low side MOSFET conducting. Accordingly inductor current threshold for OCP is a function of conducting resistance of lower MOSFET RDS(ON) as : IOCSET = Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 40 μA × R OCSET (20k Ω ) - 0.4V = 0.4V RDS(ON) RDS(ON) is a registered trademark of Richtek Technology Corporation. DS9259-05 March 2012 RT9259 If MOSFET with RDS(ON) = 16mΩ is used, the OCP threshold current is about 25A. Once OCP is triggered, the RT9259 enters hiccup mode and re-soft starts again. The RT9259 shuts down after 4 time OCP hiccups. A well-designed compensator regulates the output voltage to the reference voltage VREF with fast transient response and good stability. In order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. The goal of the compensation network is to provide adequate phase margin (greater than 45 degrees) and the highest 0dB crossing frequency. It is also recommended to manipulate loop frequency response that its gain crosses over 0dB at a slope of −20dB/dec. VIN OSC Driver PWM Comparator Inductor Current (20A/Div) ΔVOSC L Driver + PHASE COUT Time (2.5ms/Div) Figure 6. Shorted then Start Up VOUT ESR ZFB COMP EA + REF IL (20A/Div) ZFB C2 C1 LGATE (5V/Div) UGATE (5V/Div) Time (5μs/Div) ZIN ZIN C3 R2 VOUT R3 R1 COMP EA + FB REF Figure 8. Closed Loop Figure 7. Shorted then Start Up (Extended Figure 3) 1) Modulator Frequency Equations Feedback Compensation The RT9259 is a voltage mode controller. The control loop is a single voltage feedback path including a compensator and modulator as shown Figure 8. The modulator consists of the PWM comparator and power stage. The PWM comparator compares error amplifier EA output (COMP) with oscillator (OSC) sawtooth wave to provide a PulseWidth Modulated (PWM) with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter LOUT and COUT. The output voltage (VOUT) is sensed and fed to the inverting input of the error amplifier. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9259-05 March 2012 The modulator transfer function is the small-signal transfer function of VOUT/VCOMP (output voltage over the error amplifier output. This transfer function is dominated by a DC gain, a double pole, and a zero as shown in Figure 10. The DC gain of the modulator is the input voltage (VIN) divided by the peak to peak oscillator voltage VOSC. The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter expressed as : 1 fLC = 2π L OUT × C OUT is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9259 The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor expressed as follows : 1 fESR = 2π × COUT × ESR response, but often jeopardize the system stability. In order to cancel one of the LC filter poles, place the zero before the LC filter resonant frequency. In the experience, place the zero at 75% LC filter resonant frequency. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The second pole is placed at half the switching frequency. 2) Compensation Frequency Equations Thermal Considerations The compensation network consists of the error amplifier and the impedance networks ZC and ZF as shown in Figure 9. For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : ZF C1 ZC C2 R2 R1 VOUT PD(MAX) = ( TJ(MAX) − TA ) / θJA EA + COMP FB Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. RF VREF For recommended operating conditions specification, where TJ(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For VQFN-16L 4x4 packages, the thermal resistance θJA is 54°C/W on the standard JEDEC 51-7 four-layers thermal test board. Figure 9. Compensation Loop fZ1 = 1 2π x R2 x C2 fP1 = 1 2π x R2 x C1 x C2 C1 + C2 80 80 Loop Gain The maximum power dissipation at TA = 25°C can be calculated by following formula : 60 40 40 Compensation Gain Gain (dB) 20 0 PD(MAX) = ( 125°C − 25°C ) / 54°C/W = 1.852 W for QFN-16L 4x4 packages 0 -20 PD(MAX) = ( 125°C − 25°C) / 100°C/W = 1.000 W for SOP-14 packages Modulator Gain -40-40 -60-60 10Hz 10vdb(vo) 100Hz vdb(comp2)100 vdb(lo) 1.0KHz 10KHz 1k 10k Frequency (Hz) Frequency 100KHz 100k 1.0MHz 1M Figure 10. Bode Plot Figure 10 shows the DC/DC converter's gain vs. frequency. The compensation gain uses external impedance networks ZC and ZF to provide a stable, high bandwidth loop. High crossover frequency is desirable for fast transient Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 PD(MAX) = ( 125°C − 25°C ) / 110°C/W = 0.909 W for SSOP-16 packages The maximum power dissipation depends on operating ambient temperature for fixed T J (MAX) and thermal resistance θJA. The Figure 11 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. is a registered trademark of Richtek Technology Corporation. DS9259-05 March 2012 RT9259 Maximum Power Dissipation (W) 2.00 4-Layers PCB 1.75 QFN-16L 4x4 1.50 1.25 SOP-14 1.00 SSOP-16 0.75 0.50 0.25 0.00 0 25 50 75 100 125 Ambient Temperature (°C) Figure 11. Derating Curve of Maximum Power Dissipation Layout Consideration Use a dedicated grounding plane and use vias to ground all critical components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source of MOSFETs should be sized to carry 2A peak currents. IQ1 IL VOUT 5V/12V Q1 + + + MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. Careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. Consider, as an example, the turn-off transition of the upper MOSFET prior to turn-off, the upper MOSFET was carrying the full load current. During turn-off, current stops flowing in the upper MOSFET and is picked up by the low side MOSFET or schottky diode. The power components and the PWM controller should be placed firstly. Place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. Place the output inductor and output capacitors between the MOSFETs and the load. Also locate the PWM controller near by MOSFETs. A multi-layer printed circuit board is recommended. Figure 12 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each of them represents numerous physical capacitors. LOAD IQ2 Q2 Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selections, layout of the critical components, and use shorter and wider PCB traces help in minimizing the magnitude of voltage spikes. There are two sets of critical components in a DC/DC converter using the RT9259. The switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9259-05 March 2012 GND GND LGATE VCC RT9259 UGATE FB Figure 12. The Connections of the Critical Components in the Converter is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT9259 Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 8.534 8.738 0.336 0.344 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 14–Lead SOP Plastic Package Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS9259-05 March 2012 RT9259 c D L E E1 e A2 A A1 b Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 1.346 1.753 0.053 0.069 A1 0.102 0.254 0.004 0.010 A2 1.499 0.059 b 0.203 0.305 0.008 0.012 C 0.178 0.254 0.007 0.010 D 4.801 5.004 0.189 0.197 e 0.635 0.025 E 5.791 6.198 0.228 0.244 E1 3.810 3.988 0.150 0.157 L 0.406 1.270 0.016 0.050 16-Lead SSOP Plastic Package Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9259-05 March 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT9259 D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.250 0.380 0.010 0.015 D 3.950 4.050 0.156 0.159 D2 2.000 2.450 0.079 0.096 E 3.950 4.050 0.156 0.159 E2 2.000 2.450 0.079 0.096 e L 0.650 0.500 0.026 0.600 0.020 0.024 V-Type 16L QFN 4x4 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 16 DS9259-05 March 2012