® RT8901 35V Gate Pulse Modulator for LCD Panels General Description Features The Gate Pulse Modulator (GPM) is specially designed for the application of gate driver in TFT LCD panels. The GPM is controlled by frame signals from timing controller to modulate the Gate-On voltage that acts a flicker compensation circuit to reduce the coupling effect between gate lines and pixels. It also can delay the Gate-On voltage while power-on for achieving a correct power-on-sequence for gate driver ICs. Both of the delay time for flicker compensation and power-on-sequence are programmable by external resistors and capacitors. Flicker Compensation Circuit Reduction of Coupling Effect Between Gate Line and Pixel Programmable Power Sequence for Gate Driver IC Operation from 20V to 35V Positive Supply Input Adjustable Output Delay Time RoHS Compliant and 100% Lead (Pb)-Free Ordering Information Applications TFT-LCD Panels Typical Application Circuit RT8901 Package Type S : SOP-8 4 VCD Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) R2 33k 6 VGHM C3 100pF Note : Richtek products are : VDPM 7 RE GND VD RoHS compliant and compatible with the current require- 2 3 VGHM C2 1.5nF R1 1.2k R5A 200k 5 ments of IPC/JEDEC J-STD-020. VGH C1 1µF RT8901 8 VFLK VFLK VDPM VGH 1 CD VAVDD R5B 20k Suitable for use in SnPb or Pb-free soldering processes. Figure 1. Typical Application Circuit for Mode A and Mode C Marking Information RT8901GS RT8901GS : Product Number RT8901 GSYMDNN C4 100pF YMDNN : Date Code Pin Configurations R2 33k 6 7 VGH 8 VFLK VGHM 2 7 GND RE 3 6 VDPM CD 4 5 VD SOP-8 Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8901-03 October 2013 VDPM C3 100pF (TOP VIEW) VGH 1 CD VGHM RE GND VGH C1 1µF RT8901 8 VFLK VFLK VDPM 4 VD 2 3 5 VGHM C2 1.5nF R1 1.2k R5A 200k VAVDD R5B 20k Figure 2. Typical Application Circuit for Mode B is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8901 Timing Diagram VGH VREF VDPM 0V CD VCD = 5V High Low VFLK VGH VGHM 10VD 0V Duty is controlled by VFLK Discharging Time is controlled by R1 Figure 3. Timing Sequence of Mode A VGH VDPM VREF 0V 0.9VDD VREF CD VFLK VGH VGHM 10VD 0V Duty is controlled by VFLK and C4 Discharging Time is controlled by R1 Figure 4. Timing Sequence of Mode B VGH VREF VDPM 0V CD VCD = 3.3V High Low VFLK VGH VGHM 10VD 0V Duty is controlled by VFLK Discharging Time is controlled by R1 Figure 5. Timing Sequence of Mode C Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS8901-03 October 2013 RT8901 Functional Pin Description Pin No. Pin Name Pin Function 1 VGH Power Supply Input. 2 VGHM 3 RE 4 CD Switch output directly drives the power supply of Gate Driver IC. Source of the internal high-voltage MOSFET P2 connect to a resistor from this pin to ground. VGHM Discharging Delay Input. For mode selection and VGHM discharging delay time setting. 5 VD 6 VDPM 7 GND VGHM Low-Level Regulation Set-Point Input. The voltage level is 10VD. High-Voltage Switch Delay Input. Connect a capacitor from VDPM to GND to set the delay time. The internal current source is 5μA. Ground. 8 VFLK Control Signal Input Pin. VFLK is produced from timing controller in LCD module. Function Block Diagram VDD VREF Regulator VGH VDD 5µA P1 + VDPM VDD 50µA CD CDO + Logic Control Circuit VFLK GND Copyright © 2013 Richtek Technology Corporation. All rights reserved. October 2013 9R + - R Q3 DS8901-03 VGHM P2 RE VD is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8901 Absolute Maximum Ratings (Note 1) VGH, VGHM, RE to GND ------------------------------------------------------------------------------------------------ −0.3V to 40V VFLK, VDPM, VD, CD to GND ----------------------------------------------------------------------------------------- −0.3V to 6.5V Output Current Source from VGH (Pulse Width <500ns with period >2.5μs) ------------------------------ 1A Output Current (rms value), R1 = 0Ω -------------------------------------------------------------------------------- 133mA Power Dissipation, PD @ TA = 25°C SOP-8 -----------------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) SOP-8, θJA -----------------------------------------------------------------------------------------------------------------SOP-8, θJC ----------------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------- Recommended Operating Conditions 0.833W 120°C/W 30°C/W 260°C 150°C −65°C to 150°C 2kV 200V (Note 4) Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C −40°C to 85°C Electrical Characteristics (VGH = +30V, GND = 0V, TA = 25°C, unless otherwise specified.) Parameter Symbol Test Conditions Min Typ Max Unit 20 -- 35 V Input Supply Voltage VVGH Input Supply Current IVGH CD = VDPM = 5V, VVFLK = 5V -- 0.5 1.5 mA Adjustable VGHM Falling Regulation Voltage 10VD fVFLK = 25kHz, VGHM at Low, VGHM with 1.5nF, R1 = 1.2k 3 -- V GH V VFLK Threshold Voltage Logic- High VVFLK_H 1.5 -- 5.5 Logic- Low VVFLK_L 0 -- 0.4 VFLK Input Leakage Current ILeak VVFLK = 0V or High 1 VFLK to VGHM Rising Propagation Delay tPLH R1 = 1.2k, VGHM with 1.5nF, VVFLK = 0 to 3V, measure VVFLK = 1.5V to 10% VGHM -- VFLK to VGHM Falling Propagation Delay at Mode A tPHL CD = 5V, R1 = 1.2k, VGHM with 1.5nF , VVFLK = 3 to 0V, measure VVFLK = 1.5V to 90% VGHM VFLK to VGHM Falling Propagation Delay at Mode C tPHL CD = 3.3V, R1 = 1.2k, VGHM with 1.5nF , VVFLK = 3 to 0V, measure VVFLK = 1.5V to 90% VGHM Operation Frequency f OSC VDPM Voltage Threshold VDPM_H CD Mode A Operation Range VCD_A VDPM High Logic Threshold Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 V 1 μA 100 200 ns -- 100 200 ns -- 260 -- ns -- -- 300 kHz 2.4 2.5 2.6 V -- 5 -- V is a registered trademark of Richtek Technology Corporation. DS8901-03 October 2013 RT8901 Parameter Symbol CD Mode B Voltage Threshold VCD_THB CD Mode C Operation Range VCD_C VDPM Charge Current IVDPM CD Charge Current Test Conditions Min Typ Max Unit 2.4 2.5 2.6 V 3 -- 3.6 V Connect VDPM to GND, VVGH = 30V, VVFLK = 5V 4 5 6 μA ICD Connect CD to GND, VVGH = 30V, VVFLK = 0V 40 50 60 μA VGH Switch On Resistance RP1 VVGH = 30V/-20mA at VVFLK = 5V -- 15 30 RE Switch On Resistance RP2 VVGH = 30V/+20mA at VVFLK = 0V -- 15 30 CD Switch On Resistance RQ3 ICD = +1mA at VVFLK = 5V -- 1 -- k Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8901-03 October 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8901 Typical Operating Characteristics Supply Current vs. Temperature 600 490 500 Supply Current (uA) Supply Current (uA) Supply Current vs. Supply Voltage 495 485 480 475 400 300 200 470 100 VVDPM = VCD = VVFLK = 5V VVDPM = VCD = VVFLK = 5V 465 0 20 22 24 26 28 -40 -25 -10 30 5 5.75 53.5 CD Charge Current(uA) VDPM Charge Current (uA) 55 5.5 5.25 5 4.75 4.5 4.25 4 50 65 80 95 110 125 VVGH = 30V, VVFLK = 0V 52 50.5 49 47.5 46 44.5 43 41.5 3.5 VVGH = 30V, VVFLK = VCD = 5V 40 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) CD Threshold vs. Temperature VFLK Threshold vs. Temperature 1.5 3 1.3 2.8 CD Threshold (V) VFLK Threshold (V) 35 CD Charge Current vs. Temperature VDPM Charge Current vs. Temperature 6 3.75 20 Temperature (°C) Supply Voltage (V) Rising 1.1 Falling 0.9 0.7 2.6 2.4 Rising Falling 2.2 VVDPM = VCD = 5V, VVGH = 30V VVDPM = 5V, VVGH = 30V 2 0.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( °C ) is a registered trademark of Richtek Technology Corporation. DS8901-03 October 2013 RT8901 VGHM Falling Regulation Voltage VGHM Start Waveform VVFLK (2V/Div) VVFLK (2V/Div) VVGHM (10V/Div) VVDPM (5V/Div) VVGH = 0V to 30V, VCD = 5V VVD = 0V, fVFLK = 50kHz VVGHM (10V/Div) Time (25μs/Div) Time (2.5μs/Div) Mode A VGHM Propagation Delay Mode A VGHM Propagation Delay VVFLK (2V/Div) VVFLK (2V/Div) VVGHM (10V/Div) VVGHM (10V/Div) VVGH = 30V, VCD = 5V VVFLK = 0V to 3V VVGH = 30V, VCD = 5V VVFLK = 3V to 0V Time (25μs/Div) Time (50ns/Div) Mode C VGHM Propagation Delay Mode C VGHM Propagation Delay VVFLK (2V/Div) VVFLK (2V/Div) VVGHM (10V/Div) VVGHM (10V/Div) VVGH = 30V, VCD = 3.3V VVFLK = 0V to 3V Time (25ns/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8901-03 VVGH = 30V, VCD = 5V VVD = 1.6V, fVFLK = 50kHz October 2013 VVGH = 30V, VCD = 3.3V VVFLK = 3V to 0V Time (100ns/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8901 Applications Information Activate the Mode A by connecting CD to 5V. When VFLK is logic high, P1 turns on and P2 turns off, VGHM is connected to VGH. When VFLK is logic low, P1 turns off and P2 turns on, VGHM is connected to RE, and VGHM is discharged through the resistor between RE and GND. P2 turns off and stops discharging VGHM when VGHM reaches 10 times the voltage of the VD pin. When CD is connected with a capacitor, the switch control block works in the Mode B. The rising edge of the VFLK will turns on P1 and turns off P2, connecting VGHM to VGH. An internal N-MOSFET Q3 between CDO and GND is also turned on to discharge the external capacitor between CD and GND. The falling edge of VFLK turns off Q3, and an internal 50μA current source starts charging the CD capacitor. Once VCD exceeds VREF, the switch control circuit turns off P1 and turns on P2, connecting VGHM to RE. VGHM is discharged through the resistor connected between RE and GND. P2 turns off and stops discharging VGHM when VGHM reaches 10 times the voltage of the VD pin. Activate the Mode C by connecting CD to 3.3V. P1 will be turned on, P2 will be turned off and Q3 will be turned on respectively when VFLK is high. When VFLK is low, Q3 will be turned off and CDO will be pull to the same voltage level as CD through a 1kΩ resistor. P1 and P2 will be turn off and on respectively when comparator detects CDO voltage is greater than 2.5V. VGHM is discharged through the resistor connected between RE and GND. P2 turns off and stops discharging VGHM when VGHM reaches 10 times the voltage of VD pin. The timing of enabling the switch control block can be adjusted with an external capacitor connected between VDPM and GND. An internal 5μA current source starts charging the VDPM capacitor if all internal power is ready. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 The voltage on the VDPM linearly rises because of the constant-charging current. When VDPM goes above VREF, the switch control block is enabled. Output Current Maximum Rating (rms value) The GPM output current is RMS value and the RMS current boundary depends on ambient temperature with fixed P1 and P2 on-resistance. In figure 6, the test condition is VGH = 30V with R1 = 0Ω and R1 = 43Ω. The boundary is located at 125°C junction temperature for safe operation in SOP-8 package. RMSCurent Currentvs. vs.Ambient Ambient Temperature Temperature RMS 180 R1 = 43Ω 160 RMS Current (mA) The GPM consists of two high-voltage MOSFETs which include P1 between VGH and VGHM and P2 between VGHM and RE. The switch-control block is enabled when VDPM exceeds VREF and then P1 and P2 are controlled by VFLK and CD. There are three different modes of operation (see the Typical Application Circuit and Timing Diagram). 140 120 R1 = 0Ω 100 80 60 40 20 0 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 6. Output Current Maximum Rating vs. Ambient Temperature with R1 = 0Ω and R1 = 43Ω Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) - TA ) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. is a registered trademark of Richtek Technology Corporation. DS8901-03 October 2013 RT8901 For recommended operating conditions specification, the maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For SOP-8 package, the thermal resistance θJA is 120°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA =25°C can be calculated by following formula : PD(MAX) = ( 125°C - 25°C ) / (120°C/W) = 0.833W for SOP-8 package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. The Figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. Maximum Power Dissipation (W) 1.0 Four Layers PCB 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 15 30 45 60 75 90 105 120 135 Ambient Temperature (°C) Figure 7. Derating Curve Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8901-03 October 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8901 Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 10 DS8901-03 October 2013