RT9619/A Synchronous-Rectified Buck MOSFET Drivers General Description Features The RT9619/A is a high frequency, dual MOSFET driver specifically designed to drive two power N-Channel MOSFETs in a synchronous-rectified buck converter topology. This driver combined with Richtek's series of Multi-Phase Buck PWM controller form a complete corevoltage regulator solution for advanced micro-processors. z Drives Two N-Channel MOSFETs z Adaptive Shoot-Through Protection Embedded Boot Strapped Diode Supports High Switching Frequency Fast Output Rise Time Small SOP-8 Package Tri-State Input for Bridge Shutdown Supply Under Voltage Protection RoHS Compliant and 100% Lead (Pb)-Free The RT9619/A drives both the lower/upper gate in a synchronous-rectifier bridge with 12V. This drive-voltage flexibility provides the advantage of optimizing applications involving trade-offs between switching losses and conduction losses. RT9619A has longer UGATE/LGATE deadtime which can drive the MOSFETs with large gate RC value, avoiding the shoot-through phenomenon. RT9619 is targeted to drive low gate RC MOSFETs and performs better efficiency. The output drivers in the RT9619/A can efficiently switch power MOSFETs at frequency up to 500kHz. Switching z z z z z z z Applications z Core Voltage Supplies for Desktop, Motherboard CPU z High Frequency Low Profile DC-DC Converters High Current Low Voltage DC-DC Converters z Ordering Information RT9619/A Package Type S : SOP-8 Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) frequency above 500kHz has to take into account the thermal dissipation of SOP-8 package. RT9619/A is capable to drive a 3nF load with a 30ns rise time. RT9619/A implements bootstrapping on the upper gate with an external capacitor and an embedded diode. This reduces implementation complexity and allows the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. Long Dead Time Short Dead Time Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Pin Configurations Suitable for use in SnPb or Pb-free soldering processes. (TOP VIEW) BOOT 8 UGATE PWM 2 7 PHASE NC 3 6 PGND VCC 4 5 LGATE SOP-8 DS9619/A-06 April 2011 www.richtek.com 1 ATX_12V www.richtek.com 2 ATX_12V C8 10uF C9 10uF R1 10 PWM C1 1uF C10 1000uF L1 2.2uH 5 R4 0 Q2 Q1 L2 1uH C4 2200uF + C3 3.3nF R5 2.2 VIN C5 2200uF + LGATE PGND 6 PHASE R3 2.2 C14 10uF C6 10uF + PWM NC 7 8 C2 1uF C13 10uF C7 10uF + 2 3 UGATE 1 BOOT R2 1 C12 1000uF RT9619/A 4 VCC D1 C11 1000uF VCORE RT9619/A Typical Application Circuit DS9619/A-06 April 2011 RT9619/A Functional Pin Description Pin No. Pin Name Pin Function 1 BOOT Floating bootstrap supply pin for upper gate drive. 2 PWM Input PWM signal for controlling the driver. 3 NC No Connection Pin. 4 VCC +12V Supply Voltage. 5 LGATE Lower Gate Drive Output. Connected to gate of low-side power N-Channel MOSFET. 6 PGND Common Ground. 7 PHASE Connected this pin to the source of the high-side MOSFET and the drain of the low-side MOSFET. 8 UGATE Upper Gate Drive Output. Connected to gate of high-side power N-Channel MOSFET. Function Block Diagram VCC Internal 5V POR R BOOT Tri-State Detect PWM Shoot-Through Protection UGATE Turn off Detect PHASE R VCC Shoot-Through Protection LGATE PGND Timing Diagram PWM LGATE tpdlLGATE 90% tpdlUGATE 2V 2V 90% 2V 2V UGATE tpdhUGATE DS9619/A-06 April 2011 tpdhLGATE www.richtek.com 3 RT9619/A Absolute Maximum Ratings (Note 1) Supply Voltage, VCC ----------------------------------------------------------------------------------BOOT to PHASE --------------------------------------------------------------------------------------z BOOT to GND DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------z PHASE to GND DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------z LGATE DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------z UGATE ---------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------z PWM Input Voltage ------------------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C z SOP-8 ----------------------------------------------------------------------------------------------------z Package Thermal Resistance (Note 2) SOP-8, θJA ----------------------------------------------------------------------------------------------z Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------z Storage Temperature Range -------------------------------------------------------------------------z ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------MM (Machine Mode) ----------------------------------------------------------------------------------z z −0.3V to 15V −0.3V to 15V −0.3V to VCC + 15V −0.3V to 42V −5V to 15V −10V to 30V GND − 0.3V to VCC + 0.3V −2V to VCC + 0.3V VPHASE − 0.3V to VBOOT + 0.3V VPHASE − 2V to VBOOT + 0.3V GND − 0.3V to 7V 0.625W 160°C/W 260°C −40°C to 150°C 2kV 200V Recommended Operating Conditions z z z (Note 4) Supply Voltage, VCC ----------------------------------------------------------------------------------- 12V ±10% Junction Temperature Range ------------------------------------------------------------------------- 0°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------- 0°C to 70°C Electrical Characteristics (Recommended Operating Conditions, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units 7.3 -- 13.5 V -- 1 2.5 mA 5.5 6.4 7.3 V -- 2.2 -- V VCC Supply Voltage Power Supply Voltage VCC VCC Supply Current Power Supply Current IVCC VBOOT = 12V, PWM = 0V POR Threshold VVCCrth VCC Rising Hysteresis VVCChys Power-On Reset To be continued www.richtek.com 4 DS9619/A-06 April 2011 RT9619/A Parameter Symbol Test Conditions Min Typ Max Units PWM Input Maximum Input Current I PWM PWM = 0V or 5V -- 300 -- μA PWM Floating Voltage VPWMfl VCC = 12V -- 2.4 -- V PWM Rising Threshold VPWMrth 3.2 3.6 3.9 V 1.1 1.3 1.5 V 1.5 -- 3.2 V PWM Falling Threshold V PWMfth Shutdown W indow Timing UGATE Rise Time trUGATE VCC = 12V, 3nF load -- 27 35 ns UGATE Fall Time tfUGATE VCC = 12V, 3nF load -- 32 45 ns LGATE Rise Time trLGATE VCC = 12V, 3nF load -- 35 45 ns LGATE Fall Time tfLGATE VCC = 12V, 3nF load -- 27 38 ns tpdhUGATE VBOOT − VPHASE = 12V See Timing Diagram -- 20 -- -- 90 -- -- 15 -- -- 20 -- -- 8 -- RT9619 RT9619A Propagation Delay tpdlUGATE RT9619/A tpdhLGATE See Timing Diagram tpdlLGATE ns Output UGATE Drive Source RUGATEsr VBOOT – VPHASE = 12V -- 1.9 3 Ω UGATE Drive Sink RUGATEsk VBOOT – VPHASE = 12V -- 1.4 3 Ω LGATE Drive Source RLGATEsr VCC = 12V -- 1.9 3 Ω LGATE Drive Sink RLGATEsk VCC = 12V -- 1.1 2.2 Ω Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS9619/A-06 April 2011 www.richtek.com 5 RT9619/A Typical Operating Characteristics PWM to Drive Waveform PWM to Drive Waveform PWM (5V/Div) PWM (5V/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (10V/Div) LGATE (10V/Div) PHASE (10V/Div) PHASE (10V/Div) No Load No Load Time (25ns/Div) Time (25ns/Div) Dead Time Dead Time Full Load Full Load UGATE UGATE PHASE PHASE (5V/Div) (5V/Div) LGATE LGATE Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time No Load No Load UGATE UGATE PHASE PHASE (5V/Div) (5V/Div) LGATE Time (20ns/Div) www.richtek.com 6 LGATE Time (20ns/Div) DS9619/A-06 April 2011 RT9619/A Short Pulse Internal Diode I-V Curve 0.06 IOUT = 119A to 24A 0.05 LGATE PHASE Current (A) UGATE 0.04 0.03 0.02 (5V/Div) 0.01 0.00 Time (20ns/Div) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Voltage (V) DS9619/A-06 April 2011 www.richtek.com 7 RT9619/A Application Information The RT9619/A is designed to drive both high side and low side N-Channel MOSFET through externally input PWM control signal. It has power-on protection function which held UGATE and LGATE low before VCC up across the rising threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE signal turns low then UGATE signal is allowed to go high just after a non-overlapping time to avoid shootthrough current. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE signal reach a predetermined low level, LGATE signal is allowed to turn high. The PWM signal is acted as "High" if above the rising threshold and acted as "Low" if below the falling threshold. Any signal level enters and remains within the shutdown window is considered as "tri-state", the output drivers are disabled and both MOSFET gates are pulled and held low. If left the PWM signal floating, the pin will be kept around 2.4V by the internal divider and provide the PWM controller with a recognizable level. Also to prevent the overlap of the gate drives during LGATE turn low and UGATE turn high, the non-overlap circuit monitors the LGATE voltage. When LGATE go below 1.2V, UGATE is allowed to go high. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs at 12V (or 5V), the gate draws the current only few nano-amperes. Thus once the gate has been driven up to "ON" level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. D1 d1 L s1 VIN VOUT Cgs1 Cgd1 The RT9619/A typically operates at frequency of 200kHz to 500kHz. It shall be noted that to place a 1N4148 or schottky diode between the VCC and BOOT pin as shown in the typical application circuit for ligher efficiency. Cgd2 Igs1 Igd1 Ig1 g1 d2 Ig2 Igd2 g2 D2 Igs2 Cgs2 s2 GND Non-overlap Control To prevent the overlap of the gate drives during the UGATE turn low and the LGATE turn high, the non-overlap circuit monitors the voltages at the PHASE node and high side gate drive (UGATE-PHASE). When the PWM input signal goes low, UGATE begins to turn low (after propagation delay). Before LGATE can turn high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.2V. Once the monitored voltages fall below 1.2V, LGATE begins to turn high. For short pulse condtion, if the PHASE pin had not gone high after LGATE turns low, the LGATE has to wait for 200ns before turn high. By waiting for the voltages of the PHASE pin and high side gate drive to fall below 1.2V, the non-overlap protection circuit ensures that UGATE is low before LGATE turns high. www.richtek.com 8 Vg1 VPHASE +12V t Vg2 12V t Figure 1. Equivalent Circuit and Associated Waveforms In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging Cgd and Cgs. Cgs1 and Cgs2 are the capacitances from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs is referred as "Ciss" which is the input capacitance. Cgd1 and Cgd2 are the capacitances from gate to drain of the high side and the DS9619/A-06 April 2011 RT9619/A low side power MOSFETs, respectively and referred to the data sheets as "Crss" the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2 are showed below : the total current required from the gate driving source is Ig1 = Igs1 + Igd1 = (1.428 + 0.326) = 1.754 (A) Ig2 = Igs2 + Igd2 = (0.88 + 0.4) = 1.28 (A) (9) (10) , Igs1 = C gs1 dVg1 C gs1 × 12 = dt t r1 (1) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Igs2 = C gs1 dVg2 C gs1 × 12 = dt t r2 (2) Select the Bootstrap Capacitor Before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D2" had been turned on before high side MOSFETs turned on. Igd1 = C gd1 dV = C gd1 12V t r1 dt Figure 2 shows part of the bootstrap circuit of RT9619/A. The VCB (the voltage difference between BOOT and PHASE on RT9619/A) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CB has to be selected properly. It is determined by following constraints. (3) Before the low side MOSFET is turned on, the Cgd2 have been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is 1N4148 VCC BOOT UGATE Igd2 = Cgd2 dV = Cgd2 Vi + 12V dt t r2 (4) Igs1 = 1660 × 10 × 12 = 1.428 (A) 14 × 10 -9 (5) -12 Igs2 = 2200 × 10 × 12 = 0.88 30 × 10 -9 (6) -12 (A) from equation. (3) and (4) -12 -12 × (12 + 12) 30 × 10 -9 DS9619/A-06 April 2011 + VCB - LGATE PGND Figure 2. Part of Bootstrap Circuit of RT9619/A In practice, a low value capacitor CB will lead the overcharging that could damage the IC. Therefore to minimize the risk of overcharging and reducing the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. Here, to adopt either a ceramic or tantalum capacitor is suitable. Power Dissipation Igd1 = 380 × 10 -9× 12 = 0.326 (A) 14 × 10 500 × 10 PHASE CB VCC It is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage VIN = 12V, Vg1 = Vg2 = 12V. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF, and tr = 14ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and tr = 30ns, from the equation (1) and (2) we can obtain Igd2 = VIN = 0.4 (7) (A) (8) For not exceeding the maximum allowable power dissipation to drive the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate power dissipation appro-priately. www.richtek.com 9 RT9619/A This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 3 shows the power dissipation test circuit. CL and CU are the UGATE and LGATE load capacitors, respectively. The bootstrap capacitor value is 1μF. 10 1N4148 CBOOT 1uF +12V +12V (11) where the ambient temperature is 25°C. The method to improve the thermal transfer is to increase the PCB copper area around the RT9619/A first. Then, adding a ground pad under IC to transfer the heat to the peripheral of the board. Layout Consideration BOOT VCC TJ = (160°C/W x 100mW) + 25°C = 41°C 2N7002 UGATE 1uF CU 3nF RT9619/A PHASE Figure 5 shows the schematic circuit of a two-phase synchronous buck converter to implement the RT9619/A. The converter operates from 5V to 12V of VIN. 2N7002 PWM VIN 20 LGATE PGND CL 3nF circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close. Figure 3. Test Circuit Figure 4 shows the power dissipation of the RT9619/A as a function of frequency and load capacitance. The value of the CU and CL are the same and the frequency is varied from 100kHz to 1MHz. Power Dissipation vs. Frequency 1000 CU=CL=3nF Next, the trace from UGATE, and LGATE should also be short to decrease the noise of the driver output signals. PHASE signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C4 should be connected to PGND directly. Furthermore, the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible. 800 D1 VIN 12V 600 500 1.2uH C2 1uF C1 1000uF CU=CL=2nF 400 Q1 L2 300 CU=CL=1nF 7 VCORE + 200 C3 1500uF 100 CB 1uF 8 2uH Q2 PHB83N03LT PHB95N03LT 5 1 BOOT UGATE PHASE LGATE R1 C4 10 1uF 4 VCC RT9619/A L1 700 + Power Dissipation (mW) 900 When layout the PCB, it should be very careful. The power- VIN PGND 2 PWM 6 0 0 200 400 600 800 1000 Frequency (kHz) Figure 5. Two-Phase Synchronous Buck Converter Circuit Figure 4. Power Dissipation vs. Frequency The operating junction temperature can be calculated from the power dissipation curves (Figure 4). Assume VCC=12V, operating frequency is 200kHz and the CU=CL=1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 100mW. For RT9619/A, the package thermal resistance θJA is 160°C/W, the operating junction temperature is calculated as : www.richtek.com 10 DS9619/A-06 April 2011 12V RT9619/A Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9619/A-06 April 2011 www.richtek.com 11