® RT9629A Triple-Channel Synchronous Rectified Buck MOSFET Driver General Description Features The RT9629A is a high frequency, triple-channel synchronous rectified buck MOSFET driver specifically designed to drive six power N-MOSFETs. The part is promoted to pair with Richtek's multiphase buck PWM controller family for high-density power supply implementation. The output drivers of RT9629A can efficiently switch power MOSFETs at frequency 300kHz typically. Operating in higher frequency should consider the thermal dissipation carefully. The device implements bootstrapping on the upper gate with only an external capacitor and a diode required. This reduces circuit complexity and allows the use of higher performance, cost effective N-MOSFETs. All drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. The RT9629A has also detected the fault condition during initial start-up before the multi-phase PWM controller takes control. As a result, the input supply will latch into the shutdown state. The RT9629A comes in a small footprint package with WQFN-24L 5x5 package. z z z z z z z z z Drive Six N-MOSFETs for 3-Phase Buck PWM Control Shoot Through Protection Embedded Bootstrap Diode Support High Switching Frequency Fast Output Rising Time Tri-State PWM Input for Output Shutdown Enable Control Small 24-Lead WQFN Package RoHS Compliant and Halogen Free Applications z z z z Core Voltage Supplies for Desktop, Motherboard CPU High Frequency Low Profile DC/DC Converters High Current Low Voltage DC/DC Converters Core Voltage Supplies for GFX Card Marking Information RT9629AZQW : Product Number RT9629A ZQW YMDNN YMDNN : Date Code Simplified Application Circuit 12V VIN VCCx RT9629A PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 Chip Enable VOUT L2 PHASE2 EN1 EN2 EN3 L3 PHASE3 GND Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9629A-03 October 2012 L1 PHASE1 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9629A Ordering Information Pin Configurations RT9629A Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. LGATE3 VCC2 BOOT2 UGATE2 Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) GND Package Type QW : WQFN-24L 5x5 (W-Type) PHASE3 (TOP VIEW) 24 23 22 21 20 19 UGATE3 1 18 PHASE2 BOOT3 2 17 LGATE2 GND 3 16 VCC1 EN3 4 15 LGATE1 PWM3 5 14 GND EN2 6 13 PHASE1 GND 10 11 12 BOOT1 9 UGATE1 8 POR PWM2 7 PWM1 Suitable for use in SnPb or Pb-free soldering processes. EN1 25 ` WQFN-24L 5x5 Function Pin Description Pin No. 1, 12, 19 2, 11, 20 Pin Name UGATE3, UGATE1, UGATE2 BOOT3, BOOT1, BOOT2 3, 14, 23, GND 25 (Exposed Pad) 4, 6, 8 5, 7, 9 10 13, 18, 24 15, 17, 22 16, 21 EN3, EN2, EN1 PWM3, PWM2, PWM1 Pin Function High Side Gate Drive Outputs for Phase 3, Phase 1, and Phase 2. Connect this pin to the Gate of high side power MOSFET. Bootstrap Power Pins for Phase 3, Phase 1, and Phase 2. This pin powers the high side MOSFET driver. Connect this pin to the junction of the bootstrap capacitor and the cathode of the bootstrap diode. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Chip Enable (Active High). When this pin is low, both UGATEx and LGATEx are driven to low. PWM Signal Input. Connect this pin to the PWM output of the controller. POR Power On Reset Signal. PHASE1, PHASE2, PHASE3 LGATE1, LGATE2, LGATE3 Switch Nodes of High Side Driver 1, Driver 2, and Driver 3. Connect this pin to the high side MOSFET Source together with the low side MOSFET Drain and the inductor. VCC1, VCC2 Low Side Gate Drive Output for Phase 1, Phase 2, and Phase 3. This pin drives the Gate of low side MOSFET. Supply Input Pin. VCC1 supplies current for Channel 1 and Channel 2 gate drivers. VCC2 supplies current for Channel 3 gate driver. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9629A-03 October 2012 RT9629A Function Block Diagram VCC1 VCC2 POR Bootstrap Control POR Enable Detect EN1 BOOT1 Internal VDD Tri-State Detect PWM1 Shoot-Through Protection UGATE1 Turn Off Detection PHASE1 VCC1 Shoot-Through Protection LGATE1 GND VCC1 Bootstrap Control Enable Detect EN2 BOOT2 Internal VDD Tri-State Detect PWM2 Shoot-Through Protection UGATE2 Turn Off Detection PHASE2 VCC1 Shoot-Through Protection LGATE2 GND VCC2 Bootstrap Control Enable Detect EN3 Internal VDD PWM3 Tri-State Detect BOOT3 Shoot-Through Protection UGATE3 Turn Off Detection PHASE3 VCC2 Shoot-Through Protection LGATE3 GND Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9629A-03 October 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9629A Operation POR (Power On Reset) Bootstrap Control POR block detects the voltage at VCC1 pin and VCC2 pin. When the VCC1 and VCC2 pin voltage is higher than POR rising threshold, POR pin output voltage (POR output) is high. POR output is low when VCC1 and VCC2 are not both higher than POR rising threshold. When the POR pin voltage is high, UGATEx and LGATEx can be controlled by ENx pin and PWMx pin voltage. With low POR pin voltage, both UGATEx and LGATEx will be pulled to low. Bootstrap control block controls the integrated bootstrap switch. When LGATEx is high (low side MOSFET is turned on), the bootstrap switch is turned on to charge the bootstrap capacitor connected to BOOTx pin. When LGATEx is low (low side MOSFET is turned off), the bootstrap switch is turned off to disconnect VCCx pin and BOOTx pin. Turn-Off Detection Enable Detect When ENx pin input voltage is higher/lower than EN rising threshold, MOSFET driver is enabled/disabled. When the ENx input and POR output are high, UGATEx and LGATEx can be controlled by PWMx input voltage. When ENx input is low, both UGATEx and LGATEx are pulled to low. Turn-off detection block detects whether high side MOSFET is turned off by monitoring PHASEx pin voltage. To avoid shoot through between high side and low side MOSFETs, low side MOSFET can be turned on only after high side MOSFET is effectively turned off. Shoot-Through Protection Tri-State Detect When both POR block output and ENx pin voltages are high, UGATEx and LGATEx can be controlled by PWMx input. There are three PWMx input modes, which are high, low, and shutdown state. If PWMx input is within the shutdown window, both UGATEx and LGATEx output are low. When PWMx input is higher than its rising threshold, UGATEx is high and LGATEx is low. When PWMx input is lower than its falling threshold, UGATEx is low and LGATEx is high. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 Shoot-through protection block implements the dead time when both high side and low side MOSFETs are turned off. With shoot-through protection block, high side and low side MOSFET are never turned on simultaneously. Thus, shoot through between high side and low side MOSFETs is prevented. is a registered trademark of Richtek Technology Corporation. DS9629A-03 October 2012 RT9629A Absolute Maximum Ratings z z z z z z z z z z z z z (Note 1) Supply Voltage, VCC1, VCC2 --------------------------------------------------------------------- −0.3V to 15V BOOTx to PHASEx ---------------------------------------------------------------------------------- −0.3V to 15V PHASEx to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V < 20ns --------------------------------------------------------------------------------------------------- −10V to 35V LGATEx to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) < 20ns --------------------------------------------------------------------------------------------------- −2V to (VCC + 0.3V) UGATEx to GND DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V) < 20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V) ENx, PWMx to GND --------------------------------------------------------------------------------- −0.3V to 7V POR to GND ------------------------------------------------------------------------------------------- −0.3V to 5V Power Dissipation, PD @ TA = 25°C WQFN-24L 5x5 --------------------------------------------------------------------------------------- 2.778W Package Thermal Resistance (Note 2) WQFN-24L 5x5, θJA ---------------------------------------------------------------------------------- 36°C/W WQFN-24L 5x5, θJC --------------------------------------------------------------------------------- 6°C/W Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C Junction Temperature -------------------------------------------------------------------------------- 150°C Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) ------------------------------------------------------------------------- 2kV Recommended Operating Conditions z z z (Note 4) Supply Voltage, VCC1, VCC2 --------------------------------------------------------------------- 4.5V to 13.2V Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCCx = 12V, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.5 -- 13.2 V Power Supply Voltage VCC Power Supply Current IVCC VBOOTx = 12V, PWMx Floating -- 250 -- μA POR Rising Threshold VPOR_r VCCx Rising -- 4 4.4 V POR Falling Threshold VPOR_f VCCx Falling 3 3.5 -- V POR Pin High Voltage VPOR_H -- 3.5 4 V POR Pin Low Voltage VPOR_L -- -- 0.5 V Power On Reset (POR) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9629A-03 October 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9629A Parameter Symbol Test Conditions Min Typ Max Unit EN Input ENx Rising Threshold VENH -- 1.3 1.6 V ENx Falling Threshold VENL 0.7 1 -- V PWM Input Maximum Input Current IPWM VPWMx = 0V or 5V -- 160 -- μA PWMx Floating Voltage VPWM_fl PWMx = Open -- 1.8 -- V PWMx Rising Threshold VPWM_rth 2.3 2.8 3.2 V PWMx Falling Threshold VPWM_fth 0.7 1.1 1.4 V Timing UGATEx Rising Time tUGATEr 3nF load -- 25 -- ns UGATEx Falling Time tUGATEf 3nF load -- 12 -- ns LGATEx Rising Time tLGATEr 3nF load -- 24 -- ns LGATEx Falling Time tLGATEf 3nF load -- 10 -- ns Propagation Delay tUGATEpgh VBOOTx − VPHASEx = 12V tUGATEpdl See Timing Diagram -- 30 -- -- 22 -- tLGATEpdh -- 30 -- -- 8 -- tLGATEpdl See Timing Diagram ns ns Output UGATEx Drive Source RUGATEsr VBOOT − VPHASE = 12V, ISource = 100mA -- 1.7 -- Ω UGATEx Drive Sink RUGATEsk VBOOT − VPHASE = 12V, ISink = 100mA -- 1.4 -- Ω LGATEx Drive Source RLGATEsr ISource = 100mA -- 1.6 -- Ω LGATEx Drive Sink RLGATEsk ISink = 100mA -- 1.1 -- Ω Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS9629A-03 October 2012 RT9629A Typical Application Circuit RT9629A 16 VCC1 RVCC 2.2 12V 21 VCC2 RBOOT1 1 CBOOT1 11 BOOT1 1µF R UG1 2.2 12 UGATE1 CVCC 1µF PHASE1 10 8 Chip Enable 6 4 9 PWM1 LGATE1 POR L1 15 RLG1 0 EN2 EN3 PHASE2 18 PWM1 PWM2 7 PWM2 PWM3 5 PWM3 3, 14, 23, GND 25 (Exposed Pad) LGATE2 QUG1 13 RBOOT2 1 CBOOT2 BOOT2 20 1µF R UG2 2.2 19 UGATE2 EN1 VIN 12V CIN 270µF x 3 17 RPH1 2.2 QLG1 CPH1 3.3nF VIN QUG2 L2 RLG2 0 RBOOT3 1 CBOOT3 2 BOOT3 1µF R UG3 2.2 1 UGATE3 RPH2 2.2 QLG2 CPH2 3.3nF VIN QUG3 L3 PHASE3 24 LGATE3 22 VOUT COUT 820µF x 6 RLG3 0 RPH3 2.2 QLG3 CPH3 3.3nF Timing Diagram PWMx tLGATEpdl LGATEx 90% tUGATEpdl 1.5V 1.5V 1.5V 90% 1.5V UGATEx tUGATEpdh Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9629A-03 October 2012 tLGATEpdh is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9629A Typical Operating Characteristics Drive Enable Drive Disable UGATE (50V/Div) UGATE (50V/Div) PHASE (20V/Div) PHASE (20V/Div) LGATE (20V/Div) LGATE (20V/Div) EN (10V/Div) EN (10V/Div) VIN = 12V, No Load VIN = 12V, No Load Time (1μs/Div) Time (1μs/Div) PWM Rising Edge PWM Falling Edge PWM (10V/Div) PWM (10V/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (10V/Div) LGATE (10V/Div) PHASE (10V/Div) PHASE (10V/Div) Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE LGATE (5V/Div) (5V/Div) Full Load Full Load Time (20ns/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 Time (20ns/Div) is a registered trademark of Richtek Technology Corporation. DS9629A-03 October 2012 RT9629A Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE (5V/Div) LGATE (5V/Div) No Load Time (20ns/Div) No Load Time (20ns/Div) Short Pulse UGATE LGATE PHASE (5V/Div) UGATE − PHASE No Load Time (20ns/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9629A-03 October 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9629A Application Information The RT9629A is a high frequency, triple-channel synchronous rectified. MOSFET driver containing Richtek's advanced MOSFET driver technologies. The RT9629A is designed to be able to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. Supply Voltage and Power On Reset The RT9629A can be utilized under both VCCx = 5V or VCCx = 12V applications which may happen in different fields of electronics application circuits. In terms of efficiency, higher VCCx equals higher driving voltage of UGATEx/LGATEx which may result in higher switching loss and lower conduction loss of power MOSFETs. The choice of VCCx = 12V or VCCx = 5V can be a tradeoff to optimize system efficiency. And VCC1 pin must be directly connected to VCC2 pin. The RT9629A controls both high side and low side NMOSFETs of three half-bridge power according to three external input PWMx control signals. It has Power On Reset (POR) function which held UGATEx and LGATEx low before the VCCx voltage rises to higher than rising threshold voltage. When VCC1 and VCC2 exceed the POR threshold voltage, the voltage at the POR pin will be pulled high. Enable and Disable The RT9629A includes an ENx pin for sequence control. When the ENx pin rises above the VENH trip point, the RT9629A begins a new initialization and follows the PWMx command to control the UGATEx and LGATEx. When the ENx pin falls below the VENL trip point, the RT9629A shuts down and keeps UGATEx and LGATEx low. The PWMx signal is acted as “ High” if the signal is above the rising threshold and acted as “ Low” if the signal is below the falling threshold. When PWM signal level enters and remains within the shutdown window, the output drivers are disabled and both MOSFET gates are pulled and held low. If the PWMx signal is left floating, the pin will be kept around 1.8V by the internal divider and provide the PWMx controller with a recognizable level. Bootstrap Power Switch The RT9629A builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate PCB design and reduce total BOM cost of the system. Hence, no external bootstrap diode is required in real applications. Non-overlap Control To prevent the overlap of the gate drivers during the UGATEx pull low and the LGATEx pull high, the non-overlap circuit monitors the voltages at the PHASEx node and high side gate drive (UGATEx − PHASEx). When the PWMx input signal goes low, UGATEx begins to pull low (after propagation delay). Before LGATEx is pulled high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1V. Once the monitored voltages fall below 1.1V, LGATEx begins to turn high. By waiting for the voltages of the PHASEx pin and high side gate driver to fall below 1.1V, the non-overlap protection circuit ensures that UGATEx is low before LGATEx pulls high. Also to prevent the overlap of the gate drivers during LGATEx pull low and UGATEx pull high, the non-overlap circuit monitors the LGATEx voltage. When LGATEx goes below 1.1V, UGATEx goes high after propagation delay. Tri-state PWM Input After the initialization, the PWMx signal takes the control. The rising PWMx signal first forces the LGATEx signal to turn low then UGATEx signal is allowed to go high just after a non-overlapping time to avoid shoot through current. The falling of PWMx signal first forces UGATEx to go low. When UGATEx and PHASEx signal reach a predetermined low level, LGATEx signal is allowed to turn high. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs1 or Vgs2 is at 12V or 5V, the gate draws the current only for few nano-amperes. Thus once the gate has been driven up to “ ON” level, the current could be negligible. is a registered trademark of Richtek Technology Corporation. DS9629A-03 October 2012 RT9629A However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. d1 s1 VPHASEx VIN L VOUT Cgs1 Cgd1 Cgd2 Igs1 Igd1 Ig1 g1 d2 D2 Igs2 Cgs2 dVg2 dt = Cgs1 x 12 (2) tr2 Before driving the gate of the high side MOSFET up to 12V, the low side MOSFET has to be off; and the high side MOSFET will be turned off before the low side is turned on. From Figure 1, the body diode “ D2” will be turned on before high side MOSFETs turn on. dV 12 Igd1 = Cgd1 = Cgd1 (3) dt tr1 Before the low side MOSFET is turned on, the Cgd2 have been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is Ig2 Igd2 g2 Igs2 = Cgs1 Igd2 = Cgd2 s2 VIN + 12 dV = Cgd2 dt tr2 (4) GND It is helpful to calculate these currents in a typical case. Assume a synchronous rectified Buck converter, input voltage VIN = 12V, Vgs1 = 12V, Vgs2 = 12V.The high side MOSFET is PHB83N03LT whose C iss = 1660pF, Crss = 380pF, and tr = 14ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and tr = 30ns, from the equation (1) and (2) we can obtain Vg1 VPHASEx +12V t Vg2 12V Igs1 = t Figure 1. Equivalent Circuit and Waveforms (VCC = 12V) In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging Cgd1, Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs1 and C gs2 are referred as “ Ciss” which are the input capacitors. Cgd1 and Cgd2 are the capacitors from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as “ Crss” the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2, are shown as below : Igs1 = Cgs1 dVg1 dt = Cgs1 x 12 tr1 Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9629A-03 October 2012 Igs2 = 1660 x 10-12 x 12 14 x 10-9 2200 x 10-12 x 12 30 x 10-9 = 1.428 = 0.88 (5) (A) (A) (6) from equation. (3) and (4) Igd1 = Igd2 = 380 x 10-12 x 12 14 x 10-9 = 0.326 (A) 500 x 10-12 x (12+12 ) 30 x 10-9 (7) = 0.4 (A) (8) the total current required from the gate driving source can be calculated as following equations. Ig1 = Igs1 + Igd1 = (1.428 + 0.326 ) = 1.754 (A) Ig2 = Igs2 + Igd2 = ( 0.88 + 0.4 ) = 1.28 (A) (9) (10) By a similar calculation, we can also get the sink current required from the turned off MOSFET. (1) is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9629A Select the Bootstrap Capacitor Figure 2 shows part of the bootstrap circuit of the RT9629A. The VCB (the voltage difference between BOOTx and PHASEx on RT9629A) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CBOOT has to be selected properly. It is determined by the following constraints. CBOOT 1µF 10 12V 1µF 12V BOOTx VCCx UGATEx 2N7002 RT9629A POR Chip Enable PWMx CU 3nF POR PHASEx ENx PWNx VIN 2N7002 20 LGATEx GND CL 3nF BOOTx UGATEx PHASEx CBOOT Figure 3. Power Dissipation Test Circuit + VCB - VCCx LGATEx Figure 4 shows the power dissipation of the RT9629A as a function of frequency and load capacitance when VCC = 12V. The value of CU and CL are the same and the frequency is varied from 100kHz to 1MHz. Power Dissipation vs. Frequency GND 1000 In practice, a low value capacitor CBOOT will lead to the over charging that could damage the IC. Therefore, to minimize the risk of overcharging and to reduce the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. It is recommended to adopt a ceramic or tantalum capacitor. Power Dissipation To prevent driving the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate the power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 3 shows the power dissipation test circuit. CL and C U are the UGATEx and LGATEx load capacitors, respectively. The bootstrap capacitor value is 1μF. Power Dissipation (mW) 900 Figure 2. Part of Bootstrap Circuit of RT9629A 800 CU = CL = 3nF 700 600 CU = CL = 2nF 500 400 300 200 CU = CL = 1nF 100 VCC = 12V 0 0 200 400 600 800 1000 Frequency (kHz) Figure 4. Power Dissipation vs. Frequency The operating junction temperature can be calculated from the power dissipation curves (Figure 4). Assume VCCx = 12V, operating frequency is 200kHz and CU = CL = 1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 100mW. Thus, for example, with the SOP8 package, the package thermal resistance θJA is 120°C/ W. The operating junction temperature is then calculated as : TJ = (120°C/W x 100mW) + 25°C = 37°C (11) where the ambient temperature is 25°C. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS9629A-03 October 2012 RT9629A Thermal Considerations Layout Consideration For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : Figure 6 shows the schematic circuit of a synchronous buck converter to implement the RT9629A. The converter operates from 5V to 12V of input Voltage. PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-24L 5x5 package, the thermal resistance, θJA, is 36°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : For the PCB layout, it should be very careful. The power circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The location of QUGx, QLGx, Lx should be very close. Next, the trace from UGATEx, and LGATEx should also be short to decrease the noise of the driver output signals. PHASEx signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor CVCC should be connected to GND directly. Furthermore, the bootstrap capacitors (CBOOTx) should always be placed as close to the pins of the IC as possible. VIN 12V LIN 12V + PD(MAX) = (125°C − 25°C) / (36°C/W) = 2.778W for CIN CIN2 CBOOTx RVCC BOOTx VCCx WQFN-24L 5x5 package Maximum Power Dissipation (W)1 3.0 Four-Layer PCB UGATEx PHB83N03LT + The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. PHASEx COUT QLGx PHB95N03LT LGATEx RT9629A CVCC QUGx Lx VOUT PWMx ENx PWMx ENx GND Figure 6. Synchronous Buck Converter Circuit 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 5. Derating Curve of Maximum Power Dissipation Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9629A-03 October 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT9629A Outline Dimension D2 D SEE DETAIL A L 1 E E2 e 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options b A A3 1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. A1 Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.250 0.350 0.010 0.014 D 4.950 5.050 0.195 0.199 D2 3.100 3.400 0.122 0.134 E 4.950 5.050 0.195 0.199 E2 3.100 3.400 0.122 0.134 e L 0.650 0.350 0.026 0.450 0.014 0.018 W-Type 24L QFN 5x5 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 14 DS9629A-03 October 2012