CYPRESS CY7C343B

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CY7C343B
64-Macrocell MAX® EPLD
Features
Functional Description
• 64 MAX macrocells in 4 LABs
The CY7C343B is a high-performance, high-density erasable
programmable logic device, available in 44-pin PLCC and
HLCC packages.
• 8 dedicated inputs, 24 bidirectional I/O pins
• Programmable interconnect array
The CY7C343B contains 64 highly flexible macrocells and 128
expander product terms. These resources are divided into four
Logic Array Blocks (LABs) connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one
that doubles as a clock pin when needed. The CY7C343B also
has 28 I/O pins, each connected to a macrocell (6 for LABs A
and C, and 8 for LABs B and D). The remaining 36 macrocells
are used for embedded logic.
• Advanced 0.65-micron CMOS technology to increase
performance
• Available in 44-pin HLCC, PLCC
• Lowest power MAX device
The CY7C343B is excellent for a wide range of both
synchronous and asynchronous applications.
Logic Block Diagram
9 INPUT
INPUT 35
11 INPUT
INPUT/CLK 34
12 INPUT
INPUT 33
13 INPUT
INPUT 31
DEDICATED INPUTS
SYSTEM CLOCK
LAB A
I/O PINS
2
4
5
6
7
8
LAB D
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 56
MACROCELL 55
MACROCELL 54
MACROCELL 53
MACROCELL 52
MACROCELL 51
MACROCELL 50
MACROCELL 49
MACROCELLS 7 - 16
P
I
A
LAB B
I/O PINS
15
16
17
18
19
20
22
23
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
1
44
42
41
40
39
38
37
I/O PINS
30
29
28
27
26
24
I/O PINS
MACROCELLS57 - 64
LAB C
MACROCELL 38
MACROCELL 37
MACROCELL 36
MACROCELL 35
MACROCELL 34
MACROCELL 33
MACROCELLS39 - 48
MACROCELLS 25 - 32
(3, 14, 25, 36)
(10, 21, 32, 43)
Cypress Semiconductor Corporation
Document #: 38-03038 Rev. *B
•
VCC
GND
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 9, 2004
USE ULTRA37000TM FOR
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CY7C343B
Pin Configuration
I/O
I/O
1
2
I/O
3
I/O
4
GND
I/O
5
I/O
I/O
6
V
CC
I/O
I/O
HLCC, PLCC
Top View
44 43 42 41 40
I/O
7
39
I/O
I/O
8
38
I/O
INPUT
9
37
I/O
GND
10
36
VCC
INPUT
11
35
INPUT
INPUT
12
34
INPUT/CLK
INPUT
13
33
INPUT
VCC
14
32
GND
I/O
15
31
INPUT
I/O
16
30
I/O
I/O
17
29
I/O
7C343
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
GND
I/O
I/O
I/O
18 19 20 21 22 23 24 25 26 27 28
Selection Guide
Maximum Access Time (ns)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................–65°C to+135°C
Ambient Temperature with
Power Applied..............................................–65°C to+135°C
Maximum Junction Temperature
(Under Bias)................................................................. 150°C
Supply Voltage to Ground Potential[1] ............. –2.0V to+7.0V
7C343B-25
7C343B-30
7C343B-35
25
30
35
DC Output Current, per Pin[1] ...................–25 mA to +25 mA
DC Input Voltage[1] .........................................–2.0V to +7.0V
Operating Range[2]
Range
Commercial
Industrial
Military
Ambient
Temperature
VCC
0°C to +70°C
5V ±5%
–40°C to +85°C
5V ±10%
–55°C to +125°C (Case)
5V ±10%
Note:
1. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document #: 38-03038 Rev. *B
Page 2 of 11
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CY7C343B
Electrical Characteristics Over the Operating Range
Parameter
VCC
Description
Supply Voltage
VOH
Output HIGH Voltage
Test Conditions
Min.
Max.
Unit
Maximum VCC rise time is 10 ms
4.75(4.5)
5.25(5.5)
V
IOH = –4.0 mA DC
IOL = 8 mA DC
[3]
2.4
V
[3]
VOL
Output LOW Voltage
0.45
V
VIH
Input HIGH Level
VIL
Input LOW Level
2.0
VCC+0.3
V
–0.3
0.8
V
IIX
Input Current
VI = VCC or ground
–10
+10
µA
IOZ
Output Leakage Current
VO = VCC or ground
–40
+40
µA
tR
tF
Recommended Input Rise Time
100
ns
Recommended Input Fall Time
100
ns
Capacitance
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V, f = 1.0 MHz
10
pF
COUT
Output Capacitance
VOUT = 0V, f = 1.0 MHz
20
pF
Note:
3. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
AC Test Loads and Waveforms
R1 464Ω
R1 464Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
250Ω
50 pF
INCLUDING
JIG AND
SCOPE
3.0V
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
R2
250Ω
5 pF
10%
GND
<6 ns
90%
90%
10%
<6 ns
(b)
THÉVENIN EQUIVALENT (commercial/military)
163 Ω
OUTPUT
Document #: 38-03038 Rev. *B
1.75V
Page 3 of 11
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The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed
delay, regardless of programmable interconnect array configuration, simplifies design by ensuring that internal signal
skews or races are avoided. The result is simpler design implementation, often in a single pass, without the multiple internal
logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
Typical ICC vs. fMAX
200
ICC ACTIVE (mA) Typ.
Programmable Interconnect Array
CY7C343B
150
VCC = 5.0V
Room Temp.
100
50
0
100 Hz
Design Recommendations
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level (either
VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND, directly
at the device. Decoupling capacitors should have good
frequency response, such as monolithic ceramic types.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from a straight input pin.
When calculating synchronous frequencies, use tS1 if all inputs
are on the input pins. When expander logic is used in the data
path, add the appropriate maximum expander delay, tEXP to
tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1)
is the lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the synchronous configuration.
Document #: 38-03038 Rev. *B
Output Drive Current
IO OUTPUT CURRENT (mA) TYPICAL
Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure to absolute
maximum ratings conditions for extended periods of time may
affect device reliability. The CY7C343B contains circuitry to
protect device pins from high static voltages or electric fields;
however, normal precautions should be taken to avoid
applying any voltage higher than maximum rated voltages.
250
IOL
200
VCC = 5.0V
Room Temp.
150
100
IOH
50
0
1
2
3
4
5
VO OUTPUT VOLTAGE (V)
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on dedicated input pins.
When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous configuration.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchronous
clock. If tOH is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
are guaranteed to function properly with a common
synchronous clock under worst-case environmental and
supply voltage conditions.
Page 4 of 11
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EXPANDER
DELAY
tEXP
REGISTER
LOGIC ARRAY
CONTROL DELAY
tLAC
INPUT
INPUT
DELAY
tIN
LOGIC ARRAY
DELAY
tLAD
CY7C343B
OUTPUT
DELAY
tCLR
tPRE
tRSU
tRH
INPUT/
OUTPUT
tOD
tXZ
tZX
tRD
tCOMB
tLATCH
SYSTEM CLOCK DELAY tICS
PIA
DELAY
tPIA
CLOCK
DELAY
tIC
FEEDBACK
DELAY
tFD
I/O DELAY
tIO
Figure 1. CY7C343B Internal Timing Model
External Synchronous Switching Characteristics Over Operating Range
7C343B-25
Parameter
Description
Min.
Com’l/Ind
Max.
7C343B-30
Min.
25
Max.
7C343B-35
Min.
30
Max.
Unit
35
ns
tPD1
Dedicated Input to Combinatorial Output
Delay[4]
tPD2
I/O Input to Combinatorial Output Delay[4]
Com’l/Ind
tSU
Global clock setup time
Com’l/ Ind
tCO1
Synchronous Clock Input to Output Delay[3] Com’l/Ind
tH
Input Hold Time from Synchronous Clock
Input
Com’l/Ind
0
0
0
ns
tWH
Synchronous Clock Input HIGH Time
Com’l/Ind
8
10
12.5
ns
tWL
Synchronous Clock Input LOW Time
Com’l/Ind
8
10
12.5
ns
fMAX
Maximum Register Toggle Frequency[5]
Com’l/Ind
62.5
50
40
MHz
tCNT
Minimum Global Clock Period
Com’l/Ind
tODH
Output Data Hold Time After Clock
Com’l/Ind
2
2
2
ns
fCNT
Maximum Internal Global Clock
Frequency[6]
Com’l/Ind
50
40
33.3
MHz
40
15
45
20
14
55
25
16
20
20
25
ns
ns
30
ns
ns
Notes:
4. C1 = 35 pF.
5. The fMAX values represent the highest frequency for pipeline data.
6. This parameter is measured with a 16-bit counter programmed into each LAB.
Document #: 38-03038 Rev. *B
Page 5 of 11
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CY7C343B
External Asynchronous Switching Characteristics Over Operating Range
Parameter
Description
7C343B-25
7C343B-30
7C343B-35
Min.
Min.
Min.
Max.
Max.
Max.
Unit
35
ns
tACO1
Asynchronous Clock Input to Output Delay[4] Com’l/Ind
tAS1
Dedicated Input or Feedback Set-Up Time to Com’l/Ind
Asynchronous Clock Input
5
6
8
ns
tAH
Input Hold Time from Asynchronous Clock
Input
Com’l/Ind
6
8
10
ns
tAWH
Asynchronous Clock Input HIGH Time[7]
Com’l/Ind
11
14
16
ns
tAWL
Asynchronous Clock Input LOW Time[7]
Com’l/Ind
9
11
14
ns
tACNT
Minimum Internal Array Clock Frequency
Com’l/Ind
fACNT
Maximum Internal Array Clock Frequency[6] Com’l/Ind
25
30
20
25
50
40
30
33.3
ns
MHz
Internal Switching Characteristics Over Operating Range
7C343B-25
Parameter
Description
Min.
Max.
7C343B-30
Min.
Max.
7C343B-35
Min.
Max.
Unit
tIN
Dedicated Input Pad and Buffer Delay Com’l/Ind
5
7
11
ns
tIO
I/O Input Pad and Buffer Delay
Com’l/Ind
6
6
11
ns
tEXP
Expander Array Delay
Com’l/Ind
12
14
20
ns
tLAD
Logic Array Data Delay
Com’l/Ind
12
14
14
ns
tLAC
Logic Array Control Delay
Com’l/Ind
10
12
13
ns
tOD
Output Buffer and Pad Delay[4]
Com’l/Ind
5
5
6
ns
tZX
Output Buffer Enable
Delay[4]
Com’l/Ind
10
11
13
ns
tXZ
Output Buffer Disable Delay[8]
Com’l/Ind
10
11
13
ns
tRSU
Register Set-Up Time Relative to
Clock Signal at Register
Com’l/Ind
6
8
12
ns
tRH
Register Hold Time Relative to Clock
Signal at Register
Com’l/Ind
4
6
8
ns
tLATCH
Flow-Through Latch Delay
Com’l/Ind
3
4
4
ns
tRD
Register Delay
Com’l/Ind
1
2
2
ns
tCOMB
Transparent Mode Delay
Com’l/Ind
3
4
4
ns
tIC
Asynchronous Clock Logic Delay
Com’l/Ind
14
16
18
ns
tICS
Synchronous Clock Delay
Com’l/Ind
3
2
1
ns
tFD
Feedback Delay
Com’l/Ind
1
1
2
ns
tPRE
Asynchronous Register Preset Time
Com’l/Ind
5
6
7
ns
tCLR
Asynchronous Register Clear Time
Com’l/Ind
5
6
7
ns
tPIA
Programmable Interconnect Array
Delay Time
Com’l/Ind
14
16
20
ns
Notes:
7. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped.
8. C1 = 5 pF.
Document #: 38-03038 Rev. *B
Page 6 of 11
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CY7C343B
Switching Waveforms
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
tOD
tRD
DATA FROM
LOGIC ARRAY
tXZ
OUTPUT PIN
tZX
HIGH IMPEDANCE
STATE
Internal Asynchronous
tAWH
tIOtR
tAWL
tF
CLOCK PIN
tIN
CLOCK INTO
LOGIC ARRAY
tIC
CLOCK FROM
LOGIC ARRAY
tSU
tRH
DATA FROM
LOGIC ARRAY
tRD,tLATCH
tFD
tCLR,tPRE
tFD
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
tPIA
REGISTER OUTPUT
TO ANOTHER LAB
Internal Synchronous
SYSTEM CLOCK PIN
SYSTEM CLOCK
AT REGISTER
tIN
tICS
tRSU
tRH
DATA FROM
LOGIC ARRAY
Document #: 38-03038 Rev. *B
Page 7 of 11
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CY7C343B
Switching Waveforms (continued)
Internal Combinatorial
tIN
INPUT PIN
t IO
I/O PIN
tEXP
EXPANDER
ARRAY DELAY
tLAC, tLAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
External Combinatorial
DEDICATED INPUT/
I/O INPUT
tPD1/tPD2
COMBINATORIAL
OUTPUT
External Synchronous
tWH
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tH
tSU
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
tAS1
tAH
tAWH
tAWL
ASYNCHRONOUS
CLOCK INPUT
Document #: 38-03038 Rev. *B
Page 8 of 11
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CY7C343B
Package
Name
Operating
Range
Ordering Information
Speed
(ns)
25
30
35
Ordering Code
Package Type
CY7C343B-25HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
Commercial/Industrial
CY7C343B-25JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
CY7C343B-30JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
Commercial/Industrial
CY7C343B-35HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
Commercial/Industrial
CY7C343B-35JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
Package Diagrams
44-Pin Windowed Leaded Chip Carrier H67
51-80079-**
Document #: 38-03038 Rev. *B
Page 9 of 11
USE ULTRA37000TM FOR
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CY7C343B
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
51-85003-*A
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-03038 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000TM FOR
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CY7C343B
Document History Page
Document Title: CY7C343B 64-Macrocell Max ® EPLD
Document Number: 38-03038
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106461
07/11/01
SZV
Change from Spec Number: 38-00862 to 38-03038
*A
122237
12/28/02
RBI
Power up requirements added to Operating Range Information
*B
213375
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03038 Rev. *B
Page 11 of 11