41 CY7C341 192-Macrocell MAX® EPLD Features • • • • • • Programmable Interconnect Array 192 macrocells in 12 logic array blocks (LABs) Eight dedicated inputs, 64 bidirectional I/O pins 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages Functional Description The CY7C341 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic functions. The 192 macrocells in the CY7C341 are divided into 12 LABs, 16 per LAB. There are 384 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C341 allows them to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 37 times the functionality of 20-pin PLDs, the CY7C341 allows the replacement of over 75 TTL devices. By replacing large amounts of logic, the CY7C341 reduces board space and part count, and increases system reliability. Each LAB contains 16 macrocells. In LABs A, F, G, and L, eight macrocells are connected to I/O pins and eight are buried, while for LABs B, C, D, E, H, I, J, and K, four macrocells are connected to I/O pins and 12 are buried. Moreover, in addition to the I/O and buried macrocells, there are 32 single product term logic expanders in each LAB. Their use greatly enhances the capability of the macrocells without increasing the number of product terms in each macrocell. Logic Array Blocks There are 12 logic array blocks in the CY7C341. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Externally, the CY7C341 provides eight dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins that may be individually configured for input, output, or bidirectional data flow. Cypress Semiconductor Corporation Document #: 38-03034 Rev. *A • The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives. Timing Delays Timing delays within the CY7C341 may be easily determined using Warp™, Warp Professional™, or Warp Enterprise™ software. The CY7C341 has fixed internal delays, allowing the user to determine the worst case timing delays for any design. Design Recommendations For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types. Design Security The CY7C341 contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the device. The CY7C341 is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages. 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 11, 2001 CY7C341 Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current Commercial Industrial Military Commercial Industrial Military 7C341-25 25 380 480 480 360 435 435 7C341-30 30 380 480 480 360 435 435 7C341-35 35 380 480 480 360 435 435 Unit ns mA mA Logic Block Diagram 1 (A6) INPUT/CLK INPUT (C6) 84 2 (A5) INPUT INPUT (C7) 83 41 (K6) INPUT INPUT (L7) 44 42 (J6) INPUT INPUT (J7) 43 SYSTEMCLOCK 4 5 6 7 8 9 10 11 (C5) (A4) (B4) (A3) (A2) (B3) (A1) (B2) LAB G MACROCELL 97 MACROCELL 98 MACROCELL 99 MACROCELL 100 MACROCELL 101 MACROCELL 102 MACROCELL 103 MACROCELL 104 LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 7 MACROCELL 8 MACROCELL 9–16 (C2) (B1) (C1) (D2) 22 (G3) 23 (G1) 25 (F1) 26 (H1) 27 (H2) 28 (J1) 29 (K1) 30 (J2) LAB C MACROCELL 33 MACROCELL 34 MACROCELL 35 MACROCELL 36 (L1) (K2) (K3) (L2) (L3) (K4) (L4) (J5) P I A Document #: 38-03034 Rev. *A LAB I MACROCELL 129 MACROCELL 130 MACROCELL 131 MACROCELL 132 MACROCELL 37–48 MACROCELL 133–144 LAB D MACROCELL 49 MACROCELL 50 MACROCELL 51 MACROCELL 52 LAB J MACROCELL 145 MACROCELL 146 MACROCELL 147 MACROCELL 148 MACROCELL 53–64 MACROCELL 149–160 LAB K MACROCELL 161 MACROCELL 162 MACROCELL 163 MACROCELL 164 LAB E MACROCELL 65 MACROCELL 66 MACROCELL 67 MACROCELL 68 58 59 62 63 (H11) (F10) (G9) (F9) 64 65 67 68 (F11) (E11) (E9) (D11) 69 70 71 72 (D10) (C11) (B11) (C10) 73 74 75 76 77 78 79 80 (A11) (B10) (B9) (A10) (A9) (B8) (A8) (B6) MACROCELL 165–176 LAB F MACROCELL 81 MACROCELL 82 MACROCELL 83 MACROCELL 84 MACROCELL 85 MACROCELL 86 MACROCELL 87 MACROCELL 88 LAB L MACROCELL 177 MACROCELL 178 MACROCELL 179 MACROCELL 180 MACROCELL 181 MACROCELL 182 MACROCELL 183 MACROCELL 184 MACROCELL 89–96 MACROCELL 185–192 3, 24, 45, 66 (B5, G2, K7, E10) 18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7) (J10) (K11) (J11) (H10) MACROCELL 117–128 MACROCELL 69–80 31 32 33 34 35 36 37 38 54 55 56 57 LAB H MACROCELL 113 MACROCELL 114 MACROCELL 115 MACROCELL 116 MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21–32 16 (D1) 17 (E3) 20 (F2) 21 (F3) (L6) (L8) (K8) (L9) (L10) (K9) (L11) (K10) MACROCELL 105–112 LAB B 12 13 14 15 46 47 48 49 50 51 52 53 VCC GND () – PERTAIN TO 84-PIN PGA PACKAGE C341-1 Page 2 of 15 CY7C341 Pin Configurations PGA Bottom View L I/O I/O I/O I/O GND I/O INPUT I/O I/O I/O I/O K I/O I/O I/O I/O GND INPUT VCC I/O I/O I/O I/O J I/O I/O I/O I/O H I/O I/O I/O I/O G I/O VCC I/O I/O GND GND F I/O I/O I/O I/O I/O I/O E GND GND I/O I/O VCC I/O D I/O I/O I/O I/O C I/O I/O I/O I/O B I/O I/O I/O I/O A I/O I/O I/O I/O 1 2 3 4 I/O I/O I/O I/O I/O GND I/O GND INPUT INPUT/CLK INPUT INPUT I/O I/O VCC I/O I/O I/O I/O I/O I/O PLCC/HLCC Top View 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT INPUT VCC I/O I/O I/O I/O GND GND I/O 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 7C341 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O C341-2 I/O INPUT INPUT 7C341 I/O VCC INPUT INPUT GND I/O I/O I/O I/O INPUT/ INPUT CLK GND I/O I/O I/O I/O 8 9 10 11 5 I/O 6 7 C341-3 EXPANDER DELAY tEXP INPUT INPUT DELAY tIN LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD REGISTER OUTPUT DELAY tCLR tPRE tRSU tRH tRD tCOMB tLATCH INPUT/ OUTPUT tOD tXZ tZX SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC LOGIC ARRAY DELAY tFD I/O DELAY tIO C341-4 Figure 1. CY7C341 Internal Timing Model Document #: 38-03034 Rev. *A Page 3 of 15 CY7C341 DC Output Current, per Pin ........................ −25 mA to +25 mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .......................................−65°C to +150°C Ambient Temperature with Power Applied.................................................... 0°C to +70°C Maximum Junction Temperature (Under Bias)................................................................. 150°C DC Input Voltage[1]................................................−3.0V to +7.0V DC Program Voltage .................................................... 13.0V Static Discharge Voltage..................................................>1100V (per MIL-STD-883, method 3015) Operating Range Range Supply Voltage to Ground Potential .................−2.0V to +7.0V Commercial Maximum Power Dissipation...................................2500 mW Industrial DC VCC or GND Current......................................................500 mA Military Ambient Temperature VCC 0°C to +70°C 5V ± 5% –40°C to +85°C 5V ± 10% –55°C to +125°C (Case) 5V ± 10% Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8 mA VIH Input HIGH Level VIL Input LOW Level IIX Input Current IOZ Output Leakage Current VO = VCC or GND VCC = Max., VOUT = GND ICC1 Power Supply Current (Standby) VI = VCC or GND (No Load) Power Supply Current ICC2 [5] VI = VCC or GND (No Load) f = 1.0 MHz[3, 5] Unit V 0.45 V 2.2 VCC + 0.3 V −0.3 0.8 V −10 +10 µA −40 +40 µA −30 −90 mA Commercial 360 mA Military/Industrial 435 mA [3, 4] Output Short Circuit Current Max. 2.4 GND ≤ VIN ≤ VCC IOS Min. Commercial 380 mA Military/Industrial 480 mA tR (Recommended) Input Rise Time 100 ns tF (Recommended) Input Fall Time 100 ns Capacitance[6] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 5.0V 10 pF 20 pF Notes: 1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns. 2. Typical values are for TA = 25°C and VCC = 5V. 3. Guaranteed but not 100% tested. 4. No more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 5. This parameter is measured with device programmed as a 16-bit counter in each LAB and is tested periodically by sampling production material. 6. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device. Document #: 38-03034 Rev. *A Page 4 of 15 CY7C341 AC Test Loads and Waveforms R1 464Ω 5V OUTPUT R1 464Ω 5V ALL INPUT PULSES OUTPUT R2 250Ω 50 pF 3.0V 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 250Ω 90% 10% 90% 10% GND < 6 ns < 6 ns tF tR (b) C341-5 C341-6 THÉVENIN EQUIVALENT (commercial/military) 163Ω OUTPUT 1.75V External Synchronous Switching Characteristics Over the Operating Range[6] 7C341-25 Parameter tPD1 tPD2 Description Min. Max 7C341-30 Min. Max 7C341-35 Max Unit Dedicated Input to Combinatorial Output Delay[7] Com’l 25 30 Min. 35 ns Mil 25 30 35 I/O Input to Combinatorial Output Delay[8] Com’l 40 45 55 Mil 40 45 55 44 55 tPD3 Dedicated Input to Combinatorial Com’l Output Delay with Expander Delay[9] Mil 37 37 44 55 tPD4 I/O Input to Combinatorial Output Delay with Expander Delay[3, 10] Com’l 52 59 75 Mil 52 59 75 [3, 7] Com’l 25 30 35 Mil 25 30 35 25 30 35 tEA Input to Output Enable Delay tER Input to Output Disable Delay[6] Com’l Mil 25 30 35 tCO1 Synchronous Clock Input to Output Delay Com’l 14 16 20 Mil 14 16 20 Synchronous Clock to Local Feedback to Combinatorial Output[3, 11] Com’l 30 35 42 Mil 30 35 42 tCO2 tS1 tS2 Dedicated Input or Feedback Set-up Com’l Time to Synchronous Clock Mil Output[6, 12] 15 20 25 15 20 25 I/O Input Set-up Time to Synchronous Clock Input[8] Com’l 30 39 45 Mil 30 39 45 ns ns ns ns ns ns ns ns ns Notes: 7. This specification is a measure of the delay from input signal applied to a dedicated input to combinatorial output on any output pin. This delay assumes that no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders. 8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 9. This specification is a measure of the delay from an input signal applied to a dedicated input to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic functions and includes the worst-case expander logic delay for one pass through the expander logic. 10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation. Document #: 38-03034 Rev. *A Page 5 of 15 CY7C341 External Synchronous Switching Characteristics Over the Operating Range[6] (continued) 7C341-25 Parameter Description Min. Max 0 7C341-30 Min. Max 0 7C341-35 Min. tH Input Hold Time from Synchronous Clock Input[6] Com’l Mil 0 0 0 tWH Synchronous Clock Input High Time Com’l 8 10 12.5 Mil 8 10 12.5 tWL Synchronous Clock Input Low Time Com’l 8 10 12.5 Mil 8 10 12.5 tRW Asynchronous Clear Width[3, 6] Com’l 25 30 35 Mil 25 30 35 Max 0 ns ns ns ns Asynchronous Clear to Registered Output Delay[5] Com’l 25 30 35 Mil 25 30 35 tRR Asynchronous Clear Recovery[3, 7] Com’l Mil 25 30 35 tPW Asynchronous Preset Width[3, 6] Com’l 25 30 35 Mil 25 30 35 Asynchronous Preset Recovery Time[3, 6] Com’l 25 30 35 Mil 25 30 35 tPO Asynchronous Preset to Registered Output Delay[6] Com’l 25 30 35 Mil 25 30 35 tCF Synchronous Clock to Local Feedback Input[3, 13] Com’l 3 3 5 Mil 3 3 5 External Synchronous Clock Period (1/fMAX3)[3] Com’l 16 20 25 Mil 16 20 25 fMAX1 External Feedback Maximum Frequency (1/(tCO1 + tS1))[3, 14] Com’l 34.5 27.7 22.2 Mil 34.5 27.7 22.2 fMAX2 Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[3, 15] Com’l 55.5 43 33 Mil 55.5 43 33 Data Path Maximum Frequency, least Com’l of 1/(tWL + tWH), 1/(tS1 + tH), Mil or (1/tCO1)[3, 16] 62.5 50 40.0 62.5 50 40.0 Maximum Register Toggle Frequency Com’l (1/(tWL + tWH))[3, 17] Mil 62.5 50 40.0 62.5 50 40.0 Com’l 3 3 3 Mil 3 3 3 tRO tPR tP fMAX3 fMAX4 tOH Output Data Stable Time from Synchronous Clock Input[3, 18] 25 30 Unit 35 ns ns ns ns ns ns ns MHz MHz MHz MHz ns Notes: 13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed to be local originating within the same LAB. 15. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. 16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation. 17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycle by a clock signal applied to the dedicated clock input pin. 18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin. Document #: 38-03034 Rev. *A Page 6 of 15 CY7C341 External Synchronous Switching Characteristics Over the Operating Range[6] (continued) 7C341-25 Parameter Description Min. Max 7C341-30 Min. Max 7C341-35 Min. 30 Max Unit 35 ns tACO1 Dedicated Asynchronous Clock Input Com’l to Output Delay[6] Mil 25 25 30 35 tACO2 Asynchronous Clock Input to Local Com’l Feedback to Combinatorial Output[19] Mil 40 46 55 40 46 55 tAS1 Dedicated Input or Feedback Set-up Com’l Time to Asynchronous Clock Input[6] Mil 5 5 6 8 tAS2 I/O Input Set-Up Time to Asynchronous Clock Input[6] Com’l 20 27 30 Mil 20 27 30 Input Hold Time from Asynchronous Clock Input[6] Com’l 6 8 10 Mil 6 8 10 tAWH Asynchronous Clock Input HIGH Time[6] Com’l 11 14 16 Mil 11 14 16 tAWL Asynchronous Clock Input LOW Time[6, 20] Com’l 9 11 14 Mil 9 11 14 Asynchronous Clock to Local Feedback Input[21] Com’l 15 18 22 Mil 15 18 22 tAP External Asynchronous Clock Period (1/fMAX4) Com’l 20 25 30 fMAXA1 External Feedback Maximum Frequency in Asynchronous Mode 1/(tACO1 + tAS1)[22] Com’l 33.3 27 23 Mil 33.3 27 23 fMAXA2 Maximum Internal Asynchronous Frequency[23] Com’l 50 40 33.3 Mil 50 40 33.3 fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[24] Com’l 40 33.3 28.5 Mil 40 33.3 28.5 Maximum Asynchronous Register Com’l Toggle Frequency 1/(tAWH + tAWL)[25] Mil 50 40 33.3 50 40 33.3 Output Data Stable Time from Asyn- Com’l chronous Clock Input[26] Mil 15 15 15 15 15 15 tAH tACF fMAXA4 tAOH Mil 20 6 25 8 30 ns ns ns ns ns ns ns ns MHz MHz MHz MHz ns Notes: 19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material. 20. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge triggering, the tAWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, and assumes there is no expander logic in the clock path and the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the clock signal path or data path. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/tACF + tAS1)) or (1/(tAWH +tAWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. 24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the least of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied to an external dedicated input pin. Document #: 38-03034 Rev. *A Page 7 of 15 CY7C341 Internal Switching Characteristics Over the Operating Range[2] 7C341-25 Parameter Description Min. Max 7C341-30 Min. Min. Unit 9 ns Dedicated Input Pad and Buffer Delay Com’l Mil 5 7 9 tIO I/O Input Pad and Buffer Delay Com’l 6 6 9 Mil 6 6 9 Com’l 12 14 20 Mil 12 14 20 Com’l 12 14 16 Mil 12 14 16 Expander Array Delay tLAD Logic Array Data Delay 7 Max tIN tEXP 5 Max 7C341-35 ns tLAC Logic Array Control Delay Com’l 10 12 13 Mil 10 12 13 tOD Output Buffer and Pad Delay Com’l 5 5 6 Mil 5 5 6 Com’l 10 11 13 [27] tZX Output Buffer Enable Delay tXZ Output Buffer Disable Delay 10 11 13 Com’l 10 11 13 Mil 10 11 13 Register Set-Up Time Relative to Clock Signal at Register Com’l Mil 6 8 10 tRH Register Hold Time Relative to Clock Signal at Register Com’l 6 8 10 Mil 6 8 10 tLATCH Flow-Through Latch Delay Com’l 3 4 4 Mil 3 4 4 tRD Register Delay Com’l 1 2 2 Mil 1 2 2 3 4 4 [28] 6 8 10 tCOMB Transparent Mode Delay Com’l tCH Clock High Time Com’l 8 10 12.5 Mil 8 10 12.5 Com’l 8 10 12.5 Mil 8 Mil tCL Clock Low Time tIC Asynchronous Clock Logic Delay Com’l tICS Synchronous Clock Delay tFD Feedback Delay tPRE Asynchronous Register Preset Time Document #: 38-03034 Rev. *A 3 4 10 ns ns ns Mil tRSU ns ns ns ns ns ns ns ns 4 ns ns 12.5 14 16 18 Mil 14 16 18 Com’l 2 2 3 Mil 2 2 3 Com’l 1 1 2 Mil 1 1 2 Com’l 5 6 7 Mil 5 6 7 ns ns ns ns Page 8 of 15 CY7C341 Internal Switching Characteristics Over the Operating Range[2] (continued) 7C341-25 Parameter Max Unit Com’l 5 6 7 ns Mil 5 6 7 tPCW Asynchronous Preset and Clear Pulse Width Com’l Mil 5 6 7 tPCR Asynchronous Preset and Clear Recovery Time Com’l 5 6 7 Mil 5 6 7 Programmable Interconnect Array Delay Com’l tPIA Min. Max Min. 5 Max 7C341-35 Asynchronous Register Clear Time tCLR Description 7C341-30 6 Min. 7 14 Mil ns ns 16 20 16 20 ns Notes: 27. Sample tested only for an output change of 500 mV. 28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation. Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT tER COMBINATORIAL REGISTERED OUTPUT HIGH-IMPEDANCE 3-ST ATE tEA HIGH IMPEDANCE 3-STATE VALID OUTPUT C341-7 External Synchronous DEDICATED INPUT/ I/O INPUT [7] tS1 tH tWH tWL SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET [7] tRW/tPW tRR/tPR tOH tRO/tPO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK[10] C341-8 Document #: 38-03034 Rev. *A Page 9 of 15 CY7C341 Switching Waveforms (continued) External Asynchronous DEDICATEDINPUT/ I/OINPUT[7] tAH tAS1 tAWH tAWL ASYNCHRONOUS CLOCK INPUT tACO1 ASYNCHRONOUS CLEAR/PRESET [7] tRW/tPW tRR/tPR tAOH tRO/tPO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCH. REGISTERED FEEDBACK C341-9 Internal Combinatorial tIN INPUT PIN tIO tPIA I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT C341-10 Document #: 38-03034 Rev. *A Page 10 of 15 CY7C341 Switching Waveforms (continued) Internal Asynchronous tAWH tIOtR tAWL tF CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU tRH DATA FROM LOGIC ARRAY tRD,tLATCH tFD tCLR,tPRE tFD REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB C341-11 Internal Synchronous tCH tCL SYSTEM CLOCK PIN SYSTEM CLOCK AT REGISTER tIH tICS tRSU tRH DATA FROM LOGIC ARRAY C341-12 Internal Synchronous CLOCK FROM LOGIC ARRAY tRD tOD DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tXZ tZX HIGH IMPEDANCE STATE C341-13 Document #: 38-03034 Rev. *A Page 11 of 15 CY7C341 Ordering Information Speed (ns) 25 30 35 Ordering Code CY7C341-25HC/HI Package Name Operating Range Package Type H84 84-Lead Windowed Leaded Chip Carrier CY7C341-25JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C341-25RC/RI R84 84-Lead Windowed Pin Grid Array CY7C341-30HC/HI H84 84-Lead Windowed Leaded Chip Carrier CY7C341-30JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C341-30RC/RI R84 84-Lead Windowed Pin Grid Array CY7C341-30HMB H84 84-Lead Windowed Leaded Chip Carrier CY7C341-30RMB R84 84-Lead Windowed Pin Grid Array CY7C341-35HC/HI H84 84-Lead Windowed Leaded Chip Carrier CY7C341-35JC/JI J83 84-Lead Plastic Leaded Chip Carrier CY7C341-35RC/RI R84 84-Lead Windowed Pin Grid Array CY7C341-35HMB H84 84-Lead Windowed Leaded Chip Carrier CY7C341-35RMB R84 84-Lead Windowed Pin Grid Array Commercial/Industrial Commercial/Industrial Military Commercial/Industrial Military MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Switching Characteristics Subgroups Parameter Subgroups VOH 1, 2, 3 tPD1 7, 8, 9, 10, 11 VOL 1, 2, 3 tPD2 7, 8, 9, 10, 11 VIH 1, 2, 3 tPD3 7, 8, 9, 10, 11 VIL 1, 2, 3 tCO1 7, 8, 9, 10, 11 IIX 1, 2, 3 tS1 7, 8, 9, 10, 11 IOZ 1, 2, 3 tH 7, 8, 9, 10, 11 ICC1 1, 2, 3 tACO1 7, 8, 9, 10, 11 tACO2 7, 8, 9, 10, 11 tAS1 7, 8, 9, 10, 11 tAH 7, 8, 9, 10, 11 Document #: 38-03034 Rev. *A Page 12 of 15 CY7C341 Package Diagrams 84-Leaded Windowed Leaded Chip Carrier H84 51-80081 Document #: 38-03034 Rev. *A Page 13 of 15 CY7C341 Package Diagrams (continued) 84-Lead Plastic Leaded Chip Carrier J83 51-85006-A 84-Lead Windowed Pin Grid Array R84 51-80026-*B MAX is a registered trademark of Altera Corporation. Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-03034 Rev. *A Page 14 of 15 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C341 Document Title: CY7C341 192-Macrocell MAX® EPLD Document Number: 38-03034 REV. ECN NO. Issue Date Orig. of Change ** 106379 06/18/01 SZV Change from Spec#: 38-00499 to 38-03034 *A 111355 12/17/01 MYN PGA package diagram dimensions were updated Document #: 38-03034 Rev. *A Description of Change Page 15 of 15