RENESAS M62230FP

M62230FP
LCD Matrix Regulator
REJ03D0855-0201
Rev.2.01
Nov 14, 2007
Description
The M62230FP is a semiconductor circuit for LCD matrix regulator, which will generate the divided-voltage to drive
LCD matrix.
By changing the connection of R pin (i.e., Change the internal resistor ratio), M62230FP can support divided voltage
ratio ranging from 1/5 bias to 1/13 bias.
The high stability and any desired voltage levels is possible, since the variable voltage regulator for VREF is built-in.
Features
• Adjustable type voltage divider.
(The setting range of internal resistor is from 1/5 bias to 1/13 bias)
• 5 resident buffer-Amp. (5 divided output)
• Low power dissipation. (1.8 mA Typ.)
• Resident voltage-variable regulator for VREF.
Application
To drive LCD.
Recommend Operating Conditions (Ta = 25°C)
Supply voltage range:
GND − VCC: (if V1 > −1 V, it is necessary to support VIN)…. −30 to −10 V
Recommend input voltage GND − VREF: VREF ≥ VCC…………………………………....... −30 to −6 V
(To set VCC, VREF, in order that both |0 − V2| & |VCC − V5| are larger than 1 V)
Block Diagram
REGOUT
7
REGIN 8
R1
6
R2
5
R3
4
R4
3
−
+
R
R
R
R
−1.38 V
2 R5
4R
VIN3 9
R
1 R6
VIN2 10
20 VREF
GND 12
R
R
R
R
R
VIN 11
19 VIN5
18 VCC
13
14
15
16
17
VO1
VO2
VO3
VO4
VO5
REJ03D0855-0201 Rev.2.01 Nov 14, 2007
Page 1 of 6
M62230FP
Pin Arrangement
M62230FP
R6
1
20 VREF
R5
2
19 VIN5
R4
3
18 VCC
R3
4
17 VO5
R2
5
16 VO4
R1
6
15 VO3
REGOUT
7
14 VO2
REGIN
8
13 VO1
VIN3
9
12 GND
11 VIN
VIN2 10
(Top view)
Outline: PRSP0020DA-A (20P2N-A)
REJ03D0855-0201 Rev.2.01 Nov 14, 2007
Page 2 of 6
M62230FP
Explanation of Terminals
Pin No.
Symbol
Function
1
2
R6
R5
If the voltage of each pin can satisfy the following condition:
3
4
R4
R3
VO6 ≥ VO5 ≥ VO4 ≥ VO3 ≥ VO2 ≥ VO1
5
6
R2
R1
These pins will be used.
Please refer to page 5 to set the bias ratio.
7
8
REGOUT
REGIN
Regulator output for VREF to use
The inverting input pin of REG OP-Amp
9
10
VIN3
VIN2
VIN3 input
VIN2 input
11
VIN
VIN Power
12
GND
GND Pin
13
14
VO1
VO2
Divided-voltage output pin
15
16
VO3
VO4
To set VCC & VREF, in order that 0 − V2 ≥ 1 V
To set VCC & VREF, in order that V5 − VCC ≥ 1 V
17
VO5
18
VCC
VCC power (−Power)
19
20
VIN5
VREF
VIN5 input
Reference voltage input pin
REJ03D0855-0201 Rev.2.01 Nov 14, 2007
Page 3 of 6
if V1 > −1.0 V, it is necessary to support VIN
if V1 < −1.0 V, this pin connect to GND
M62230FP
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted)
Item
Supply voltage
Symbol
VCC
Ratings
−36 to 0
Unit
V
Maximum output current
Power dissipation
IOUT
Pd
30
550
mA
mW
Thermal derating
Operating temperature
Kθ
Topr
5.5
−20 to +75
mW/°C
°C
Storage temperature
Tstg
−40 to +125
°C
Conditions
Ta = 25°C
Ta > 25°C
Electrical Characteristics
(VCC = −16 V, VIN = GND, VREF = −12 V, Resistor setting = 5R, Ta = 25°C, unless otherwise noted)
Limits
VCC
Min.
−35
Typ.

Max.
−10
Unit
Supply voltage
Item
Symbol
Dissipation current
Output voltage ratio 1
ICC
RVO1

1.98
1.80
2.00

2.02
mA

VREF = −16 V
V2 / V1
Output voltage ratio 2
Output voltage ratio 3
RVO2
RVO3
1.98
8.90
2.00
9.00
2.02
9.10


(V5 − V3) / (V5 − V4)
V5 / V1
Output voltage ratio 4
Output voltage ratio 5
RVO4
RVO5
4.45
4.45
4.50
4.50
4.55
4.55


V5 / V2
V5 / (V5 − V3)
Output voltage ratio 6
Resistor ratio 1
RVO6
RR1
8.90

9.00
4
9.10



V5 / (V5 − V4)
Resistor between VIN3 and R1 /
resistor between R1 and R2
Resistor ratio 2
RR2

5


Resistor ratio 3
RR3

6


Resistor between VIN3 and R2 /
resistor between R1 and R2
Resistor between VIN3 and R3 /
resistor between R1 and R2
Resistor ratio 4
RR4

7


Resistor ratio 5
RR5

8


Resistor ratio 6
RR6

9


Resistance
R

20

kΩ
Resistor between VIN3 and R6 /
resistor between R1 and R2
Resistor between R1 and R2
Load regulation of output voltage 1
Load regulation of output voltage 2-1
∆V1
∆V2-1




20
20
mV
mV
+200 µA < IOUT1 < +10 mA
+200 µA < IOUT2 < +10 mA
Load regulation of output voltage 3-1
Load regulation of output voltage 2-2
∆V3-1
∆V2-2




20
20
mV
mV
+200 µA < IOUT3 < +10 mA
−10 mA < IOUT2 < −200 µA
Load regulation of output voltage 3-2
∆V3-2


20
mV
−10 mA < IOUT3 < −200 µA
Load regulation of output voltage 4
∆V4


20
mV
−20 mA < IOUT4 < −200 µA
Load regulation of output voltage 5
Output voltage of regulator
∆V5
VREG

−1.45

−1.38
20
−1.31
mV
V
−20 mA < IOUT5 < −200 µA
Buffer output
Load regulation of VREF
REG-L


50
mV
−10 mA < IREG < +2 mA
REJ03D0855-0201 Rev.2.01 Nov 14, 2007
Page 4 of 6
Test Conditions
V
Resistor between VIN3 and R4 /
resistor between R1 and R2
Resistor between VIN3 and R5 /
resistor between R1 and R2
M62230FP
The Setting Method of Divided-voltage
R
+
−
VO1
+
−
VO2
+
−
VO3
+
−
VO4
+
−
VO5
R
Rx
R
R
R
VREF
Rx
Bias Ratio
Example of Setting
R
2R
1/5
1/6
9 pin-6 pin short, 10 pin-5 pin short
9 pin-6 pin short, 10 pin-4 pin short
3R
4R
1/7
1/8
9 pin-6 pin short, 10 pin-3 pin short
10 pin-6 pin short
5R
6R
1/9
1/10
10 pin-5 pin short
10 pin-4 pin short
7R
8R
1/11
1/12
10 pin-3 pin short
10 pin-2 pin short
9R
1/13
10 pin-1 pin short
REJ03D0855-0201 Rev.2.01 Nov 14, 2007
Page 5 of 6
M62230FP
Package Dimensions
JEITA Package Code
P-SOP20-5.3x12.6-1.27
RENESAS Code
PRSP0020DA-A
Previous Code
20P2N-A
MASS[Typ.]
0.3g
20
E
*1
HE
11
F
1
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
10
c
Index mark
*2
A2
D
A1
L
A
Reference
Symbol
*3
e
bp
y
Detail F
D
E
A2
A1
A
bp
c
HE
e
y
L
REJ03D0855-0201 Rev.2.01 Nov 14, 2007
Page 6 of 6
Dimension in Millimeters
Min Nom Max
12.5 12.6 12.7
5.2 5.3 5.4
1.8
0.1 0.2
0
2.1
0.35 0.4 0.5
0.18 0.2 0.25
0°
8°
7.5 7.8 8.1
1.12 1.27 1.42
0.1
0.4 0.6 0.8
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