HD74AC166/HD74ACT166 8-bit Shift Register REJ03D0255–0200Z (Previous ADE-205-375 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources or one CP input can be used to trigger the other. Features • Outputs Source/Sink 24 mA • HD74ACT166 has TTL-Compatible Inputs • Ordering Information: Ex. HD74AC166 Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC166AFPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) HD74AC166ARPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) HD74AC166TELL T ELL(2,000 pcs/reel) TSSOP-16 pin TTP-16DAV Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement DS 1 16 VCC P0 2 15 PE P1 3 14 P7 P2 4 13 Q7 P3 5 12 P6 CP2 6 11 P5 CP1 7 10 P4 GND 8 9 MR (Top view) Rev.2.00, Jul.16.2004, page 1 of 8 HD74AC166/HD74ACT166 Logic Symbol 15 2 3 4 5 10 11 12 14 PE P0 P1 P2 P3 P4 P5 P6 P7 1 DS 1 2 CP 7 6 MR Q7 9 13 VCC=Pin16 GND=Pin8 Pin Names CP1, CP2 DS PE P0 to P7 MR Q7 Clock Pulse Inputs (Active Rising Edge) Serial Data Input Parallel Enable Input (Active Low) Parallel Data Inputs Asynchronous Master Reset Input (Active Low) Last Stage Output Functional Description Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should attain the High state while the other clock is still in the High state following the previous operation. When the Parallel Enable (PE) input is Low, data is loaded into the register from the Parallel Data (P0 to P7) inputs on the next rising edge of the clock. When PE is High, information is shifted from the Serial Data (DS) input to Q0 and all data in the register is shifted one bit position (i.e., Q0 → Q1, Q1 → Q2, etc.) on the rising edge of the clock. Truth Table Inputs MR L H H H H H PE X X L H H X H : L : X : : CP1 CP2 X L L L L H X L High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition Rev.2.00, Jul.16.2004, page 2 of 8 DS X X X H L X Parallel P0 to P7 X X a ··· h X X X Internal Outputs Q0 Q6 L QA0 a H L QA0 L QB0 b QAn QAn QB0 Output Q7 L QH0 h QGn QGn QH0 HD74AC166/HD74ACT166 Logic Diagram P0 DS P1 P2 P3 P4 P5 MR P6 R CP S CD Q P7 PE CP 1 2 R CP S CD Q Q7 Absolute Maximum Ratings Supply voltage Item Symbol VCC Ratings –0.5 to 7 V Unit DC input diode current IIK –20 20 mA mA DC input voltage DC output diode current VI IOK –0.5 to Vcc+0.5 –50 V mA DC output voltage VO 50 –0.5 to Vcc+0.5 mA V DC output source or sink current DC VCC or ground current per output pin IO ICC, IGND ±50 ±50 mA mA Storage temperature Tstg –65 to +150 °C Condition VI = –0.5V VI = Vcc+0.5V VO = –0.5V VO = Vcc+0.5V Recommended Operating Conditions: HD74AC166 Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Rev.2.00, Jul.16.2004, page 3 of 8 Symbol VCC 2 to 6 Ratings V Unit VI, VO Ta 0 to VCC –40 to +85 V °C tr, tf 8 ns/V Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V HD74AC166/HD74ACT166 DC Characteristics: HD74AC166 Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25°°C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.1 — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOL = 24 mA Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. Recommended Operating Conditions: HD74ACT166 Supply voltage Item Symbol VCC 2 to 6 V Input and output voltage Operating temperature VI, VO Ta 0 to VCC –40 to +85 V °C Input rise and fall time (except Schmitt inputs) VIN 0.8 to 2.0 V tr, tf 8 ns/V Rev.2.00, Jul.16.2004, page 4 of 8 Ratings Unit Condition VCC = 4.5V VCC = 5.5V HD74AC166/HD74ACT166 DC Characteristics: HD74ACT166 Item Input voltage Output voltage Symbol Ta = 25°°C VIH 4.5 min. 2.0 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.0 — VIL 5.5 4.5 2.0 — 1.5 1.5 — 0.8 2.0 — — 0.8 VOH 5.5 4.5 — 4.4 1.5 4.49 0.8 — — 4.4 0.8 — 5.5 4.5 5.4 3.94 5.49 — — — 5.4 3.80 — — 5.5 4.5 4.94 — — 0.001 — 0.1 4.80 — — 0.1 5.5 4.5 — — 0.001 — 0.1 0.32 — — 0.1 0.37 — — — — 0.32 ±0.1 — — 0.37 ±1.0 VOL VCC (V) Unit V Condition VOUT = 0.1 V or Vcc–0.1 V VOUT = 0.1 V or Vcc–0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL IOL = 24 mA Input current IIN 5.5 5.5 µA VIN = VCC or GND ICC/input current Dynamic output current* ICCT IOLD 5.5 5.5 — — 0.6 — — — — 86 1.5 — mA mA VIN = VCC–2.1 V VOLD = 1.1 V IOHD ICC 5.5 5.5 — — — — — 8.0 –75 — — 80 mA µA VOHD = 3.85 V VIN = VCC or ground Quiescent supply current IOL = 24 mA *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics: HD74AC166 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF fmax VCC (V)*1 Min 3.3 75 65 — MHz frequency Propagation delay tPLH 5.0 3.3 100 1.0 — 11.0 — 14.5 80 1.0 — 15.5 ns CP1 or CP2 to Q7 Propagation delay tPHL 5.0 3.3 1.0 1.0 9.5 10.5 11.5 14.0 1.0 1.0 12.5 15.0 CP1 or CP2 to Q7 Propagation delay tPHL 5.0 3.3 1.0 1.0 9.0 9.5 11.0 12.0 1.0 1.0 12.0 13.0 5.0 1.0 6.5 9.0 1.0 10.0 Item Maximum clock Symbol MR to Q7 Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 5 of 8 Typ — Max — Min Max Unit HD74AC166/HD74ACT166 AC Operating Requirements: HD74AC166 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Setup time Symbol VCC (V)*1 Typ tsu 3.3 3.0 PE or Pn or DS to CPn Hold time th 5.0 3.3 2.0 –1.5 4.0 3.0 4.5 3.0 CPn to PE or Pn or DS Pulse width tw 5.0 3.3 –0.5 2.0 3.0 5.5 3.0 7.0 CPn or MR Recovery time trec 5.0 3.3 2.0 –2.5 4.5 0.0 5.0 0.0 5.0 –1.5 0.0 0.0 Item MR to CPn Note: Guaranteed Minimum 5.5 6.0 Unit ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Characteristics: HD74ACT166 Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Maximum clock fmax 5.0 frequency Propagation delay tPLH 5.0 CPn to Q7 Propagation delay tPHL 5.0 CPn to Q7 Propagation delay tPHL 5.0 MR to Q7 Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Ta = –40°C to +85°C CL = 50 pF Min 100 Typ — Max — Min Max Unit 80 — MHz 1.0 10.0 12.5 1.0 13.5 ns 1.0 9.5 12.0 1.0 13.0 1.0 8.5 11.0 1.0 12.0 AC Operating Requirements: HD74ACT166 Item Setup time PE or Pn or DS to CPn Hold time CPn to PE or Pn or DS Pulse width CPn or MR Recovery time MR to CPn Note: Ta = –40°C to +85°C Ta = +25°C CL = 50 pF CL = 50 pF Typ Guaranteed Minimum Symbol VCC (V)*1 tsu 5.0 2.5 7.0 8.0 th 5.0 0.0 1.5 1.5 tw 5.0 4.5 7.0 8.0 trec 5.0 –2.5 0.5 0.5 Unit ns 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 6 of 8 Symbol CIN CPD Typ 4.5 35.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC166/HD74ACT166 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 7 of 8 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g HD74AC166/HD74ACT166 As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 *0.20 ± 0.05 1.0 0.13 M Rev.2.00, Jul.16.2004, page 8 of 8 *0.15 ± 0.05 1.10 Max *Ni/Pd/Au plating 0.10 0.07 +0.03 –0.04 6.40 ± 0.20 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. 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