HD74LV74A Dual D–type Flip Flops with Preset and Clear REJ03D0312–0300Z (Previous ADE-205-244A (Z)) Rev.3.00 Jun. 02, 2004 Description The HD74LV74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV74AFPEL SOP–14 pin(JEITA) FP–14DAV FP EL (2,000 pcs/reel) HD74LV74ARPEL HD74LV74ATELL SOP–14 pin(JEDEC) TSSOP–14 pin FP–14DNV TTP–14DV RP T EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Outputs PRE CLR CLK D Q Q L H L H H H H L L H H H X X X ↑ ↑ ↓ X X X H L X H L H*1 H L Q0 L H H*1 L H Q0 Note: H: High level L: Low level X: Immaterial ↑: Low to high transition ↓: High to low transition Q0: The level of Q immediately before the input conditions shown in the above table is determined. 1.: Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go HIGH simultaneously. Rev.3.00 Jun. 02, 2004 page 1 of 9 HD74LV74A Pin Arrangement 1CLR 1 14 VCC 1D 2 13 2CLR 1CLK 3 12 2D 1PRE 4 11 2CLK 1Q 5 10 2PRE 1Q 6 9 2Q GND 7 8 2Q (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input voltage range*1 Output voltage range*1, 2 VCC VI VO V V V Input clamp current Output clamp current Continuous output current IIK IOK IO Continuous current through VCC or GND ICC or IGND –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±25 ±50 Maximum power dissipation at 3 Ta = 25°C (in still air)* PT Storage temperature Tstg 785 500 –65 to 150 mA mA mA mA mW Conditions Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.3.00 Jun. 02, 2004 page 2 of 9 HD74LV74A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range Output current VI VO IOH 2.0 0 0 — — — — — — — — 0 0 0 5.5 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 V V V µA mA –40 85 °C IOL Input transition rise or fall rate ∆t /∆v Operating free-air temperature Ta µA mA ns/V Conditions VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Note: Unused or floating inputs must be held high or low. Logic Diagram PRE C CLK C C Q TG D C C TG TG TG C C C CLR Rev.3.00 Jun. 02, 2004 page 3 of 9 C C Q HD74LV74A DC Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V)* Min Typ Max Unit Input voltage VIH 1.5 VCC × 0.8 VCC × 0.8 VCC × 0.8 — — — — VCC – 0.1 2.0 2.48 3.8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0.3 VCC × 0.2 VCC × 0.2 VCC × 0.2 — — — — 0.1 0.4 0.44 0.55 ±1 20 V Input current Quiescent supply current IIN ICC 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 Output leakage current IOFF 0 — — Input capacitance CIN 3.3 — 2.0 VIL Output voltage VOH VOL Test Conditions µA µA IOL = –50 µA IOL = –2 mA IOL = –6 mA IOL = –12 mA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 5 µA VI or VO = 0 V to 5.5 V — pF VI = VCC or GND V Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00 Jun. 02, 2004 page 4 of 9 HD74LV74A Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum clock frequency tmax tPLH tPHL 100 70 9.8 11.1 13.0 14.2 — — — — — — — 14.8 16.4 17.4 20.0 — — — — — 40 25 1.0 1.0 1.0 1.0 9.0 7.0 0.5 9.0 9.0 — — 17.0 19.0 20.0 23.0 — — — — — MHz Propagation delay time 50 30 — — — — 8.0 7.0 0.5 8.0 8.0 Setup time tsu Hold time Pulse width th tw ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns ns FROM (Input) TO (Output) PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK Data PRE or CLR inactive PRE or CLR “L” CLK “H” or “L” VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum clock frequency tmax tPLH tPHL 140 90 6.9 7.9 9.2 10.2 — — — — — — — 12.3 11.9 15.8 15.4 — — — — — 70 45 1.0 1.0 1.0 1.0 7.0 5.0 0.5 7.0 7.0 — — 14.5 14.0 18.0 17.5 — — — — — MHz Propagation delay time 80 50 — — — — 6.0 5.0 0.5 6.0 6.0 Setup time tsu Hold time Pulse width th tw ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns ns FROM (Input) TO (Output) PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK Data PRE or CLR inactive PRE or CLR “L” CLK “H” or “L” VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum clock frequency tmax tPLH tPHL 180 140 5.0 5.6 6.6 7.2 — — — — — — — 7.7 7.3 9.7 9.3 — — — — — 110 75 1.0 1.0 1.0 1.0 5.0 3.0 0.5 5.0 5.0 — — 9.0 8.5 11.0 10.5 — — — — — MHz Propagation delay time 130 90 — — — — 5.0 3.0 0.5 5.0 5.0 Setup time tsu Hold time Pulse width th tw Rev.3.00 Jun. 02, 2004 page 5 of 9 ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns ns FROM (Input) TO (Output) PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK Data PRE or CLR inactive PRE or CLR “L” CLK “H” or “L” HD74LV74A Operating Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 5.0 — — 21.0 23.0 — — pF f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Quiet output, maximum dynamic VOL VOL (P) 3.3 — 0.1 0.8 V Quiet output, minimum dynamic VOL VOL (V) 3.3 — 0 –0.8 V Quiet output, minimum dynamic VOH VOH (V) 3.3 — 3.2 — V High-level dynamic input voltage VIH (D) 3.3 2.31 — — V Low-level dynamic inout voltage VIL (D) 3.3 — — 0.99 V Test Circuit Measurement point C L* Note: C L includes the probe and jig capacitance. Rev.3.00 Jun. 02, 2004 page 6 of 9 Test Conditions HD74LV74A • Waveform − 1 tr tf 90% 50% VCC Timming input 10% t su VCC 90% 50% VCC 10% th 0V VCC Data input 50% VCC 50% VCC 0V tw VCC Input 50% VCC 50% VCC 0V • Waveform − 2 tr tf 90% 50% VCC Input VCC 90% 50% VCC 10% 10% t PHL t PLH 0V VOH Same-phase output 50% VCC 50% VCC VOL t PHL t PLH VOH Opposite-phase output 50% VCC 50% VCC VOL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns 2. The output are measured one at a time with one transition per measurement. Rev.3.00 Jun. 02, 2004 page 7 of 9 HD74LV74A Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 8 5.5 14 1 1.42 Max *0.20 ± 0.05 2.20 Max 7 *0.40 ± 0.06 1.15 0˚ – 8˚ 0.10 ± 0.10 1.27 0.20 7.80 +– 0.30 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-14DAV — Conforms 0.23 g As of January, 2003 Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 + 0.67 0.14 – 0.04 *0.40 ± 0.06 + 0.11 0˚ – 8˚ 1.27 0.60 – 0.20 0.15 0.25 M *Ni/Pd/Au plating Rev.3.00 Jun. 02, 2004 page 8 of 9 Package Code JEDEC JEITA Mass (reference value) FP-14DNV Conforms Conforms 0.13 g HD74LV74A As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 14 8 1 7 0.65 1.0 *0.20 ± 0.05 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.3.00 Jun. 02, 2004 page 9 of 9 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.83 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-14DV — — 0.05 g Sales Strategic Planning Div. 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