Application Note MSAN-124
MT9171/72 DNIC Application Circuits
ISSUE 5
October 1997
Connection to Line
Protection Circuit for the LIN Pin
Transformer Selection
In a typical application, the LIN pin of the MT9171/72
will be connected to a line through a transformer.
This means that voltage spikes on the line could
cause the voltage at LIN to exceed its Absolute
Maximum Rating and damage the device. The circuit
shown in Figure 1 is designed to prevent this.
The major criterion for the selection of a transformer
is that it should not significantly attenuate or distort
the signals travelling between MT9171/72’s. A
transformer with the following specifications may be
used:
Primary Inductance
Primary Leakage Inductance
Primary Resistance
Secondary Resistance
Turns Ratio
Longitudinal Balance
DC Current without saturation
30mH min.
200 H max.
2.25 max.
1.0 max.
Primary
2:0.5:0.5
70dB @ 200Hz
60dB @ 1kHz
46dB @ 100kHz
100mA max.
A center-tap to ground on the secondary will
probably be necessary to ensure good longitudinal
balance. The effect of the variations from the
specification can be checked with a spectrum
analyzer.
The diodes, D1 and D2 clamp the voltage received
from the line. Further protection is provided by R1
which limits the current at LIN. The diodes will
handle several amps of current from the line before
the Absolute Maximum Ratings on LIN are
exceeded.
Generation of ST-BUS Timing Signals
for MT9171/72 in Master Mode
The circuit shown in Figure 2 generates the ST-BUS
framing and clock signals for the MT9171/72 in
Master Mode.
The basic clock source is a 16.384 MHz oscillator.
This is used as an input to the MT8940 which
generates all the ST-BUS timing signals except C10.
C10 is generated by the phase-locked loop formed
by the remaining components. The C10 clock is the
output of the 74LS624 Voltage Controlled Oscillator.
This is input to the 74LS163 counter which is
synchronously reset to 0 after it reaches a count of 4,
C2’ = 1.5 nF
DV Port ST-BUS
CD Port ST-BUS
{
DSTi
{
CDSTi
CDSTo
F0
C4
Mode Select
Lines
+5V
0.33 F
0.33 F
DSTo
F0
C4
MS0
MS1
MS2
VRef
For 80 kbit/s: C2’ = 3.3 nF
+5V
MT9171/72
C2 = 22 nF
D1 = D2 = MUR405
LOUT
R2 = 390
D2
2:1
0.5
R1 = 47
LIN
OSC1
OSC2
F0o
C10
Line Feed
Voltage
1.0 F
2
68 Volts
(Typ)
2.5 Joules
0.02 Watt
0.5
NC
C1 = 0.33 F
VBias
To Next DNIC
Note: Low leakage diodes (1 & 2) are required so
VBias
that the DC voltage at LIN
MSAN-124
Application Note
+5V
24
23
4
2
VDD
RST
MS1
MS0
5
3
1
10
8
17
9
F0i
C12i
ENCV
C8Kb
C16i
MS3
ENC4o
16
ENC2o
7
18
19
MS2
Ai
Bi
C10 [624 Pin 8]
CLR [163 Pin 1]
MT8940
+5V
14
VCC
OUT
8
16.384 MHZ
GND
7
CV
CVb
[163 Pin 13]
22
21
C2 [86 Pin 1]
C4b 13
C4o 11
C2o 14
C2o 15
F0b 6
[624 Pin 13]
Yo
[86 Pin 3]
C4
F0
20
33pF
VSS
12
+5V
+5V
+5V
14
3
vCC
1
2
4
5
1A
1B
2A
2B
9
10
12
13
3A
3B
4A
4B
10kΩ
1Y
3
2Y
6
3Y
8
4Y
11
74LS86
13
5
2
56pF
+5V
9
14
θVCC VCC
CX2
CX1
74LS624
FREQ
EN
RNG
θGND GND
1
7
4
8
6
1
7
10
2
3
4
5
6
9
16
VCC
CLR
EP
ET
74LS163
CLK
Q1
D1
D2
Q2
D4
Q4
D8
Q8
CO
LD
GND
8
14
13
12
11
15
C10
7
Figure 2 - Generation of ST-BUS Timing Signals for MT9171/72 in Master Mode
DIGITAL LINE
LINE
INTERFACE
(MT9171/72)
HANDSET
INTERFACE
(8962)
ST-BUS
TIMING
CIRCUITRY
(8940)
RS232
INTERFACE
(8950)
PERSONAL COMPUTER
Figure 3 - Integrated Voice and RS232 Data Capability for a Personal Computer
A-116
MSAN-124
Application Note
giving an output which is the 10.24 MHz input
divided by 5. This 2.048 MHz output is compared to
the C2 clock generated by the MT8940 using the
74LS86 exclusive-or chip.
to slow down. The phase-locked loop was found to
lock when the period of C2 was between 400 ns and
600 ns.
As C2 slows down, the overlap between the two
signals increases causing the output of the
exclusive-or to spend more time low. This reduces
the input voltage on the 74LS624 and so causes C10
+5V
+5V
14
C2
1
F0
2
DSTi
13
12
16
VCC
1CK
1Q1
1Q2
1CLR
1Q4
1Q8
74LS393
2Q1
2CK
2Q2
2Q4
2CLR
2Q8
GND
7
VCC
11
10
9
8
+5V
2.5V
DSTo
12
11
10
9
7
14
8
3
9
VCC VREF VEE
F1i
C2i
CA MT8962
2
1
DSTi
CSTi
DSTo
(CD)SD0
(CD)SD1
(CD)SD2
(OA)SD3
(OD)SD4
(OD)SD5
VR
ANUL
15 VX
15
14
13
-5V
19
5
VOICE IN
6 G1
Y0
4 G2A
Y1
5 G2B
Y2
74HCT138
1 A1
Y3
2 A2
Y4
Y5
3 A4
Y6
Y7
GND
8
3
4
5
6
4
13
12
11
10
7
6
17
16
VOICE OUT
100nF
GNDD GNDA
18
20
+5V
24
22
5
3
6
VDD
RESET
F1i
C2i
CA
MT8950
2 DSTi
1 CSTi
15 SPi
DATA IN
7
8
9
10
DF
RMP
RD
RV
DSTo
DP
SPO
DA
4
14
16
17
RDO 11
TD/S 19
13 CWCK TV/M 18
VSS
12
DATA OUT
Figure 4 - Handset and RS232 Interface Circuit
A-117
MSAN-124
Application Note
Integrated Voice and RS232 Data
Capability for a Personal Computer
This particular approach could be used with any
Personal Computer which can handle an RS232 link.
No additional software is required and there is no
microprocessor to be programmed.
Figure 3 shows how an integrated voice and data
capability can be added to a Personal Computer.
Microprocessor Interface to MT9171/72
Data is transmitted and received on the ISDN compatible digital line using an MT9171/72. If the
MT9171/72 acts as master on the line then timing is
provided by an MT8940. If the MT9171/72 acts as a
slave then it extracts timing from the line and passes
it on to the rest of the circuit.
Figure 5 shows a simple microprocessor interface to
a MT9171/72 in Slave Mode. A similar approach can
be used for Master Mode.
The MT9171/72 in Slave Mode generates the STBUS frame and clock signals needed for the
MT8981. As only channels 0 and 16 are used on the
ST-BUS streams in this configuration, the A0 to A3
address lines on the MT8981 can be strapped to
ground. This reduces the number of address lines
needed for the microprocessor interface.
The basic schematic diagram for the handset and
RS232 interface is shown in Figure 4. Level shifters
(typically an MC1488 and an MC1489) for the RS232
interface and a suitable transducer interface for the
handset complete the design.
+5V
4
5
6
17
8
15
13
9
21
LIN
c1
c1 - 100nF
c2 - 200nF
22
VDD
XT1
2
20
MS2
MS1
MS0
OSC1 OSC2
REGC
MT9171/72
F0b
F0o
C4b
DSTo
DSTi
CDSTi CDSTo
LOUT
LIN
VBIAS VREF
TEST
VSS
11
XT1 - 10.24 MHz.
16
7
14
12
10
1
LOUT
3
c2
+5V
10
11
12
9
8
7
6
5
4
3
2
DS
CS
R/W
A5
A4
19
21
20
18
17
16
15
14
13
VDD
F0i
ODE
C4i
IC
IC
IC
IC
IC
IC
IC
IC
IC
STi3
STo3
STi2
STo2
STi1
STo1
STi0
STo0
MT8981
DTA
DS
D7
CS
D6
R/W
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
VSS
39
40
31
32
33
34
35
36
37
38
1
22
23
24
25
26
27
28
29
30
Figure 5 - Microprocessor Interface to MT9171/72
A-118
DTA
D7
D6
D5
D4
D3
D2
D1
D0
MSAN-124
Application Note
The status of the MT9171/72 and data received from
the line can be read through the MT8981 by
selecting the appropriate input stream and reading
the appropriate channel. The MT9171/72 can be
controlled and data transmitted on LOUT by
selecting the appropriate memory on the MT8981
and writing to the appropriate channel. The MT8981
is used in its Message Mode here.
subsequent MT9171/72 in the chain accepts the
framing signal output by the previous MT9171/72
and generates a delayed signal from it. This
eliminates the need for a timeslot assignment circuit
for the MT9171/72’s on the digital line card.
In this example data is transmitted down the lines
from channels on the DSTi input stream and data
from the lines is output on channels on the DSTo
output stream. The MT9171/72’s are controlled and
monitored on the channels on the CSTi and CSTo
streams.
Digital Line Card
A digital line card can be built by chaining MT9171/
72’s together (see Figure 6).
The first MT9171/72 in the chain receives a framing
signal from the system and generates a delayed
framing signal for the second MT9171/72. Each
+5V
22
VDD
4
5
6
17
C10
8
15
13
9
21
F0
C4
DSTi
CSTi
100nF
2
20
MS2
MS1
MS0
OSC2
REGC
MT9171/72
F0b
F0o
C4b
DSTo
DSTi
CDSTi CDSTo
LOUT
LIN
VBIAS VREF
TEST
VSS
OSC1
16
7
14
12
10
LIN0
LOUT0
1
3
100nF
11
DSTo
CSTo
+5V
22
4
5
6
17
8
15
13
9
100nF
21
2
20
VDD
MS2
MS1
MS0
OSC1 OSC2
REGC
MT9171/72
F0b
F0o
C4b
DSTo
DSTi
CDSTi CDSTo
LOUT
LIN
VBIAS VREF
TEST
16
7
14
12
10
1
LIN1
LOUT1
3
100nF
11
Figure 6 - Digital Line Card
A-119
MSAN-124
Notes:
A-120
Application Note
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other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use
of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned
by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability,
performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee
that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily
include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE