ZL70271/72/73/74/88 Medical Surge Protection Device Data Sheet Features September 2008 • Extremely fast turn-on • Very small size and very low leakage • 5, 6 and 7 terminals available • Standard delivery form: solder bumped die • Variant for wire bonding: ZL70288 • Facilitates compliance with EN-45502 and EN50061 • Superior Quality Ordering Information ZL70271UDJ ZL70272UDJ ZL70273UDJ ZL70274UDJ ZL70288UBJ Bumped Die, Waffle Tray Bumped Die, Waffle Tray Bumped Die, Waffle Tray Bumped Die, Waffle Tray Wirebondable Die, Waffle Tray 0°C to +55°C • QA procedures based on MIL-PRF-38535 Applications • Traceability for every chip to lot and wafer number • • 100% burn-in capability Pacemakers, Implantable Cardioverter Defibrillators (ICDs), Neurostimulators, Bladder Control Devices • Lot Acceptance Testing (LAT) Included • Medical devices with electronics requiring protection against a high voltage surge die substrate Rb T1 Rb Rb Rb T4 T3 T2 Rb Rb T5 T6 Figure 1 - ZL70273 Block Diagram die substrate Rb T1 Rb Rb Rb T2 Rb T4 T3 Rb Rb T5 Figure 2 - ZL70274 and ZL70288 Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2008, Zarlink Semiconductor Inc. All Rights Reserved. T6 T7 ZL70271/72/73/74/88 Rb Rb Rb T1 T2 Data Sheet Rb Rb SUB1 T3 SUB2 T4 T5 Figure 3 - ZL70271 and ZL70272 Block Diagram 1.0 Change Summary Changes from May 2008 Issue to July 2008 Issue. Page Item Change 15 Figure 12 Corrected dimensions and tolerances. 17 Figure 16 Corrected dimensions and tolerances. Changes from July 2008 Issue to September 2008 Issue. Page Item Change 1 Ordering Information Removed ZL70270UDJ from ordering. Part has been obsoleted. 2.0 Description The ZL70271/72/73/74/88 is a family of transient surge suppressing devices designed specifically for implanted medical devices. The device terminals exhibit extremely low leakage during normal voltages and can therefore be connected in parallel with the pins of the device they protect. When the voltage rises to dangerous level it then rapidly turns on and limits the voltage by shunting the current thr7ough its thyristors. This makes the ZL70271/72/73/74/88 family an effective means of compliance with international regulations EN-45502, “Active implantable” and EN-50061, “Safety of Implantable Cardiac Pacemakers”. 2 Zarlink Semiconductor Inc. ZL70270/71/72/73/74/88 Data Sheet Table of Contents 1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 ZL70273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 ZL70274 and ZL70288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 ZL70271 and ZL70272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.0 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.0 Quality Assurance Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.0 Additional Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 Evaluation Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 Flip Chip Processing Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.0 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 Mechanical Data - ZL70273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 Mechanical Data - ZL70274 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.3 Mechanical Data - ZL70271 and ZL70272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.4 Mechanical Data - Solder bumps ZL70271/72/73/74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.5 Mechanical Data - ZL70288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Zarlink Semiconductor Inc. ZL70270/71/72/73/74/88 Data Sheet List of Figures Figure 1 - ZL70273 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL70274 and ZL70288 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 3 - ZL70271 and ZL70272 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 4 - Pacemaker Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5 - ZL70273 and ZL70274 Bumped Chip Appearance and ZL70288 Bond Pad Placement . . . . . . . . . . . . 6 Figure 6 - ZL70270, ZL70271 and ZL70272 Bumped Chip Appearance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7 - 10 ms Surge Current Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8 - Terminal to Terminal Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9 - Holding Current Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 10 - Turn-on Delay Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11 - dV/dt Immunity Test Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12 - Die Size and Bump Placement of ZL70273. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 13 - Die Size and Bump Placement of ZL70274. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 14 - Die Size and Bump Placement of ZL70271 and ZL70272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 15 - Solder Bump Appearance of ZL70271/72/73/74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 16 - Size and Bond Pad Placement of ZL70288. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 3.0 Data Sheet Applications The EN-45502 standard states that all active medical devices implanted in a human torso should not be permanently affected by an external defibrillation of the patient. Compliance is confirmed if the implanted device continues to meet device specification after being subjected to a sequence of 140 Volt pulses, in series with a 300 Ohm resistor between each conductive part of the device, including the device case (see EN-45502 for details). The ZL70271/72/73/74/88 family meets this test and is an effective means of complying with the EN-45502 standard. Without surge protection, the electronics, in almost all cases would be destroyed. The same compliance tests are also described in EN-50061. In the application example shown in Figure 4, each of the dual chamber pacemaker's terminals, and the case, are connected to a terminal on the protection device. If a defibrillation pulse causes the ventricular tip to begin to go positive, relative to the case, the ZL70271 thyristor structure rapidly becomes active and forms a low impedance path between T2 and T3 to absorb the current and limit the voltage. This provides an effective means of protecting the pacemaker chip. The voltages and currents the implanted device is subjected to in an actual defibrillation can be higher than described in EN-45502/EN-50061 and has been taken into account in the design of the ZL70271/72/73/74/88 family. Surge Protection Device ZL70271 T1 T2 T3 Typical Dual Chamber Pacemaker T5 T4 Analog chip Atrial tip lead Digital chip Charge Pump Atrial ring lead Stimulation and Sensing block Case Ventricular tip lead Voltage and Current Reference Ventricular ring lead Figure 4 - Pacemaker Application Example Terminals placed most remotely to others must get special attention since they effectively form a large pick-up coil and could therefore be exposed to a large amount of current. When implanted, the pacemaker case is placed beneath the collarbone and all other terminals are placed together inside the heart. For this reason, the largest current will pass through the surge protection terminal connected to the case of the pacemaker. For ZL70271/72, it is recommended that the case be connected to T3 of the protection device; this terminal is designed to withstand the largest amount of current. If the ZL70273/74/88 device is used in a 5 terminal application, we recommend that 2/3/3 pins of the protection device are connected to the implantable device terminal with the largest current flow (typically the terminal for the device case). 5 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 Data Sheet Pin Description Table - ZL70273, ZL70274 and ZL70288 Pin # In/Output Name Description 1 I T1 Transient Surge Protection Terminal 1 2 I T2 Transient Surge Protection Terminal 2 3 I T3 Transient Surge Protection Terminal 3 4 I T4 Transient Surge Protection Terminal 4 5 I T5 Transient Surge Protection Terminal 5 6 I T6 Transient Surge Protection Terminal 6 7 I T7 Transient Surge Protection Terminal 7 (ZL70274 and ZL70288 only) ZL70273 T1 T2 T3 T4 T5 T6 T2 T3 T4 T5 T6 T7 T2 T3 T4 T5 T6 T7 ZL70274 T1 ZL70288 T1 Figure 5 - ZL70273 and ZL70274 Bumped Chip Appearance and ZL70288 Bond Pad Placement 6 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 Data Sheet Pin Description Table - ZL70271 and ZL70272 Pin # In/Output Name Description 1 I T1 Transient Surge Protection Terminal 1 2 I T2 Transient Surge Protection Terminal 2 3 I/O SUB1 Transient Surge Protection Substrate Connection 1 4 I T3 Transient Surge Protection Terminal 3 Doubled Area 5 I/O SUB2 Transient Surge Protection Substrate Connection 2 6 I T4 Transient Surge Protection Terminal 4 7 I T5 Transient Surge Protection Terminal 5 ZL70271 and ZL70272 T1 T2 SUB1 T3 SUB2 T4 T5 Figure 6 - ZL70270, ZL70271 and ZL70272 Bumped Chip Appearance 7 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 4.0 Functional Description 4.1 ZL70273 Data Sheet The ZL70273 is a six-branch device. The suppression is achieved by a self-triggering thyristor-diode device in parallel with a diode between each branch-input and a common node which is also the substrate of the device. The six branches of the device are reached through terminals T1, T2, T3, T4, T5 and T6. The electrical characteristic observed between any two of the terminals (T1, T2, T3, T4, T5 and T6) very much resembles that of a DIAC (see Figure 8). When a transient current is forced between two branch-input terminals, the positive terminal will be clamped to the common node by the diode of one branch, and the negative terminal to the forward voltage of the thyristor-diode of the other branch. Due to the low on-state voltage of the thyristor that voltage will stay at a safe value during the transient. 4.2 ZL70274 and ZL70288 The ZL70274 and ZL70288 are seven-branch devices with exactly the same electrical characteristics as ZL70273. 4.3 ZL70271 and ZL70272 The ZL70271 and ZL70272 are five-branch transient surge suppressing devices with the same functionality as ZL70273. The only functional difference is that the substrate of the device is accessible through the two terminals SUB1 and SUB2. 8 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 5.0 Data Sheet Electrical Data Absolute Maximum Ratings* Parameter Sym. Min. Max. Units -40 125 °C 1 Storage Temperature range TS 2 Maximum junction temperature Tj 125 °C 3 Maximum surge current ITSM 8 A 4 Continuous power dissipation Pmax 300 mW Test Conditions Test according to Figure 7. tp for flip mounted chips with underfill: 10 ms. tp die wire bonded die: 1ms. t>1 s * Exceeding these values may cause permanent damage. Functional operations under these conditions is not implemented. Recommended Operating Conditions Parameter 5 Operating temperature range Note 1: Sym. Min. Typ.1 Max. Units TOP 0 37 55 °C Max. Units Test Conditions Typical figures are at 37°C and are for design only. DC Electrical Characteristics @ +37oC Parameter 6 7 8 9 10 Min. Typ. Test Conditions Iz=10 µA Forward breakdown voltage, Zener diode, terminal to terminal ZL70273/74/88 Vfz 9.0 10.1 11.0 V ZL70271 Vfz 9.0 9.5 12.2 V ZL70272 Vfz 17.0 18.0 19.5 V Iz=10 µA Forward breakdown voltage, Zener diode, terminal to substrate ZL70271 Vfz 8.5 9.2 11.5 V ZL70272 Vfz 16.5 17.7 19.0 V Breakover voltage, terminal to terminal Figure 8 ZL70273/74/88 Vbo 9.0 11.2 12.0 V ZL70271 Vbo 9.0 10.5 12.2 V ZL70272 Vbo 17.0 18.7 19.5 V Breakover voltage, terminal to substrate Figure 8 ZL70271 Vbo 8.5 9.8 11.5 V ZL70272 Vbo 16.5 18.4 19.0 V Forward diode voltage drop, substrate to terminal ZL70271/72 11 Sym. Vfwd Measured @2A 2 V Breakover current Figure 8 ZL70273/74/88 Ibo 15 200 mA ZL70271 Ibo 15 40 mA 9 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 Data Sheet DC Electrical Characteristics @ +37oC (continued) Parameter Sym. Min. Typ. Max. Units 15 40 mA Test Conditions ZL70272 Ibo 12 Holding current Ih 13 On-state voltage terminal to terminal Von 2.2 3.0 V Measured with a 300 µs pulse, IT=1 A 14 On-state voltage terminal to substrate, ZL70271/72 Von 1.0 3.0 V Measured with a 300 µs pulse, IT=1 A 15 On-state dynamic resistance 16 18 Ron 0.4 1 Ω ZL70272 Ron 0.3 1 Ω Figure 9. Measured after a current pulse of Ip=0.2A for tp=1 ms, RG<200 Ω Measured with a 300 µs pulse, dIT=1-2 A Off-state current, terminal to terminal ZL70273/74/88 Id 10 100 nA Measured at 8.0 V ZL70271/72 Id 10 150 nA ZL70271 measured at +8.5 V ZL70272 measured at +16.5 V 20 nA Force 3 current surge pulses, with max 10 s between each (I=3A, t=2 ms), between the Terminal under test and the rest of inputs (they should be tied together). If there are substrate connections, these should be left floating. ∆Id Off-state current terminal to substrate ZL70271 Id 10 150 nA ZL70271 measured at +8.0 V ZL70272 Id 10 150 nA Measured at +16.0 V Cp 50 pF Cp 200 pF Parasitic capacitance ZL70273/74/88 19 mA ZL70271/73/74/88 After Surge pulse 17 1 Parasitic capacitance ZL70271/72 10 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 Data Sheet AC Electrical Characteristics @ +37oC Parameter 20 21 22 Sym Min Typ Max Units Turn-on delay Test Conditions Defined according to Figure 10. ZL70273/74/88 tond 500 13000 ns Measured at 8.0 V ZL70271 tond 140 4000 ns Measured at 8.0 V terminal to terminal and at 7.5 V terminal to substrate ZL70272 tond 6000 ns Measured at 16 V terminal to terminal and at 15.5 V terminal to substrate Maximum voltage during surge ZL7073/74/88 Vpeak 13 15 V ZL70271 Vpeak 11.5 13 V ZL70272 Vpeak 21.5 V Immunity to dV/dt triggering Measured at peak and defined according to Figure 10. Defined according to Figure 10. ZL70073/74/88 dV/dt 1000 >2300 V/us Measured at 8.0 V ZL70271 dV/dt 100 160 V/us Measured at 9 V terminal to terminal and at 8.5 V terminal to substrate ZL70272 dV/dt 100 V/us Measured at 17 V terminal to terminal and at 16.5 V terminal to substrate 11 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 I Data Sheet Slewrate= 4 A/µs ITSM 0.9xITSM 0.1xITSM t tp Figure 7 - 10 ms Surge Current Waveform I IT Ibo Ih Id Ifz Von Vd Vfz Vbo U Figure 8 - Terminal to Terminal Characteristic Rg DUT Ip + Vg Figure 9 - Holding Current Circuit 12 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 Data Sheet 1V VT Vpeak Vfzmin t t ond IT Ip= 4 A Ipeak surge current pulse width = 100 us 0.5 x Ipeak dI/dt = 4A/us + 10% 0.1 x Ipeak t Figure 10 - Turn-on Delay Definition VT pulse amplitude fixed, device dependent pulse duration: 10 us dV/dt variable, adjusted to determine the maximum slew rate for which a device does not trigger. t Figure 11 - dV/dt Immunity Test Pulse 13 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 6.0 Data Sheet Quality Assurance Procedures Zarlink’s QA procedures are based on MIL-PRF-38535. Zarlink maintains traceability records for every chip to the wafer lot and wafer level. Each wafer lot is subjected to a Lot Acceptance Test (LAT). The devices are assembled to a ceramic test substrate and subjected a 168-hour burn-in test at +125oC, or equivalent. Wafer lots acceptance requires all LAT devices must pass the pre- and post burn-in electrical tests. A certification of compliance (C of C) is included with each shipment. Additional details/information are available upon request from Zarlink. 7.0 Additional Information 7.1 Evaluation Boards For bench evaluation purposes, Zarlink offers the surge protection devices mounted on ceramic substrate. Each surge protection device terminal and substrate terminal (if present) is accessible by two through hole solder pins attached to either side of the test substrate. Ordering information is listed in the table below. Evaluation boards are for testing and evaluation purposes only and are not for use in implanted devices. Evaluation Board, Cross-Reference Surge Protection Device Part Number Evaluation Board Part Number Evaluation Board Description ZL70271UDJ ZLE70271MAD Eval Board, Surge Protection, ZL70271 ZL70272UDJ ZLE70272MAD Eval Board, Surge Protection, ZL70272 ZL70273UDJ ZLE70273MAD Eval Board, Surge Protection, ZL70273 ZL70274UDJ ZLE70274MAD Eval Board, Surge Protection, ZL70274 ZL70288UBJ ZLE70288MAD Eval Board, Surge Protection, ZL70288 7.2 Flip Chip Processing Recommendations The surge protection devices described in this document (with the exception of ZL70288) are designed for Flip Chip assembly. The face or active surface of the chip is covered with small tin/lead solder bumps designed to connect to solder pads on the surface of a circuit board via reflow soldering. For best results, an underfill should be added to fill in the gap between the die and circuit board to reduce thermal stresses imposed on the solder joint. Zarlink does not offer a recommended circuit board pad pattern for these devices. However, there are two approaches to consider when designing the circuit board pad pattern. One method is too layout a pattern of individual pads matched to each solder bump. A second method is to design a pattern of rectangular pads large enough to connect all of the pads for a single terminal. No matter the method used, all of the solder bumps associated with an individual terminal must be connected together via the circuit board (refer to Figure 5 & Figure 6). Likewise, in the case of ZL70271/72, all of the “Sub1” and Sub2” solder bumps must also be connected together (refer to Figure 6). If unfamiliar with flip chip processing, Zarlink recommends that the customer seek advice from a consultant or sub-contractor familiar with the process. 14 Zarlink Semiconductor Inc. ZL70271/72/73/74/88 Mechanical Data 8.1 Mechanical Data - ZL70273 528 + 25 µm 8.0 650 + 5 µm 186 + 5 µm 1075 + 5 µm 1290 + 5 µm 107+ 5 µm 1874 + 30 µm 4074 + 30 µm 314 + 25 µm 287 + 25 µm 3436 + 5 µm Data Sheet 108+ 5 µm 215+ 5 µm Figure 12 - Die Size and Bump Placement of ZL70273 528 + 25 µm Mechanical Data - ZL70274 650 + 5 µm 186 + 5 µm 1075 + 5 µm 107 + 5 µm 1290 + 5 µm 4710 + 30 µm 307 + 25 µm 280 + 25 µm 4086 + 5 µm 1860 + 30 µm 8.2 15 Zarlink Semiconductor Inc. 108 + 5 µm 215+ 5 µm Figure 13 - Die Size and Bump Placement of ZL70274 ZL70271/72/73/74/88 Mechanical Data - ZL70271 and ZL70272 Die thickness is: - ZL70271: 528 + 18 µm - ZL70272: 452 + 18 µm 342.5 + 5 µm 342.5 + 5 µm 516 + 5 µm 187 + 5 µm 372 + 25 µm die th. 187 + 5 µm 187 + 5 µm 186 + 5 µm 566 + 5 µm 108 + 5 µm Figure 14 - Die Size and Bump Placement of ZL70271 and ZL70272 16 Zarlink Semiconductor Inc. 107 + 5 µm 430 + 5 µm 2286 + 5 µm 1290 + 5 µm 1075 + 5 µm 215 + 5 µm 2754 + 20 µm 4454 + 20 um 234 + 25 µm 3710 + 5 µm 215 + 5 µm 8.3 Data Sheet ZL70271/72/73/74/88 8.4 Data Sheet Mechanical Data - Solder bumps ZL70271/72/73/74 95 + 25/-20 um Sn/Pb 63/37 o 120 um nominal Barrier layers Si3N4 AL o 60 um 1 o 90 um 1 Note 1: drawn size Figure 15 - Solder Bump Appearance of ZL70271/72/73/74 Mechanical Data - ZL70288 Die Thickness is 528 + 25µm 280 + 5 µm 4710 + 30 µm 270 + 5 µm 221 + 25 µm 265 + 25 µm 848 + 5 µm 1860 + 30 µm 8.5 380 + 5 µm Figure 16 - Size and Bond Pad Placement of ZL70288 17 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE