ZL30106 SONET/SDH/PDH NETWORK INTERFACE DIGITAL PLL VOICE/DATA ZL30106 Simplified Block Diagram High Performance IED;J%I:>%F:> D[jmeha?dj[h\WY[:FBB Clock & Sync Pair Inputs Independant Input References Primary Reference 2, 8 kHz, 1.5, 2, 8, 16 or 19 MHz Secondary Reference 2, 8 kHz, 1.5, 2, 8, 16 or 19 MHz Clock Input Tertiary Reference 2, 8 kHz, 1.5, 2, 8, 16 or 19 MHz Digital PLL Reference Switching with Phase Transient Suppression Jitter and Wander Filtering Selectable Loop Filter Bandwidth High Accuracy Holdover (0.01 ppm) Precise Input to Output Phase Alignment Low Jitter Clock & Frame Pulse Outputs T1/E1 8 kHz 1.5, 2, 3, 4, 8 16, 32, 65 MHz Programmable 6, 8.4, 34, 44 MHz SONET/SDH Ultra Low Jitter (< 20 psRMS) 2 kHz, 19 MHz Industry-leading digital PLL jitter performance of 20 psRMS on 19.44 MHz clock allows a direct interface to STM-1/ OC-3 framers and mappers 8 Clock Outputs 4 Frame Pulse Outputs Hardware Control and Advanced Monitoring Manual or Automatic Reference Switching and Holdover Reference Monitoring with selectable out of range frequency limits 20 MHz Osc./xtal Control and Monitoring Accepts three reference clocks that synchronize to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz and 19.44 MHz Automatic reference frequency detection with reference out-of-range detectors continuously monitors timing references and raise an alarm if frequency error exceeds user defined limits Primary and secondary input references synchronize to clock-and-sync pair • Provides phase re-alignment of misaligned references • Enables simultaneous hitless reference switching of a clock-and-sync pair • Allows wide-bandwidth DPLL operation with low-frequency references Accurate holdover ensures precise timing when the network reference is down Simplifies Design of Line Cards The ZL™30106 is a DPLL (digital phase locked loop) that synchronizes SONET/SDH and PDH line cards. Supports free-run, normal (locked), holdover or automatic modes The ZL30106 is based on an enhanced DPLL architecture that provides an efficient route to compliance with international synchronization standards. Featuring industry-leading jitter performance, reference out-of-range detection, and excellent holdover accuracy, the ZL30106 ensures reliable line card clocks in the presence of jitter, wander and interruptions to the reference signal. Provides a range of clock outputs for SONET/SDH, DS3/ E3, DS2/E2, DS1/E1, and TDM bus This new DPLL is a standard, IC-based device that eliminates the requirements for external loop filter components and reduces board space, cost and complexity compared to traditional approaches. Selectable loop filter corner frequency of 29 Hz or 922 Hz supports multiple line card configurations Tertiary reference clock input offers additional synchronization and monitoring for the line card Simplified control via hardware interface pins for device operation, without the need for a dedicated microprocessor interface External xtal./oscillator enhances flexibility, offering the designer choice of size, source, quality and cost Packaging and Availability 64-pin TQFP package Available now in production quantities Standards Compliant Applications Line card synchronization for SONET, SDH and PDH systems Wireless base station network interface cards AdvancedTCA™ and H.110 line cards www.ZARLINK.com ITU-T G.813 Option 1 and Option 2 STM-1 jitter performance Telcordia GR-253-CORE OC-3 jitter performance Customer Support The ZL30106 is supported by a customer evaluation board and Zarlink’s network of in-house field application and design engineers. ZL30106 SONET/SDH/PDH NETWORK INTERFACE DIGITAL PLL VOICE/DATA Applications SONET and SDH are the leading transport technologies for high-speed networks, offering versatility, reliability and the ability to support synchronous and asynchronous traffic. As shown below, the ZL30106 can be used to provide fully featured, high-performance line card synchronization, complying with ITU-T and Telcordia OC-3/STM-1 jitter specifications. The ZL30106 accepts a wide range of standard reference clock and frame pulse frequencies. Each reference input is monitored within its specific frequency range and maximum frequency deviation limits. The device simultanously synchronizes to clock-and-sync pair references, enabling a wide bandwidth PLL operation while synchronized to a lowfrequency frame pulse. When the network frequencies are outside the programmable frequency range, the ZL30106 provides hitless reference switching between the primary and secondary clock and sync pair references without any phase disruption to the line card clocks and frame pulses. When clock references are down, the ZL30106’s holdover mode keeps the line card clocks accurate within 0.01 ppm of the previous valid reference. The tertiary reference clock input offers additional synchronization and monitoring for the line card. Clock and frame pulse signals are often skewed by backplane delays, which reduces timing signal margins. The ZL30106 eliminates this effect by providing precise phase re-alignment of the active clock and sync references. Achieving the industry’s best digital PLL jitter performance, the ZL30106 offers a wide range of clocks and frame pulses that can directly drive jitter-sensitive STM-1 and OC-3 components. Zarlink also offers a range of high-performance clock multiplier analog PLLs for SONET/SDH line cards from OC-12/STM-4 up to OC-192/STM-64. SONET/SDH/PDH Line Card Timing Application Accepts 3 Frequency Independant Clock References IED;J%I:>B_d[9WhZikfjeE9#'/(%IJC#,* Primary Clock & Sync Redundant Card SONET/SDH Network Element DPLL ZL30407 Clock Control & Monitoring 20 MHz Osc. Tertiary Clock SONET/SDH Timing Distribution via Backplane IED;J%I:> J_c_d]9WhZ Secondary Clock & Sync Input Frequencies 2, 8 kHz, 1.544, 2.048, 8.192, 16.384 or 19 MHz SONET/SDH/PDH Network Interface DPLL 19.44 MHz CMOS Output Up to OC-3/STM-1 Available Output Frequencies SONET/SDH Clock Multiplier APLL* 19.44, 38.88, 77.76, 155.52, or 622.08 MHz ZL30106 Clock Control & Monitoring * ZL30414 (Up to OC-192/STM-64) ZL30416 (Up to OC-192/STM-64) ZL30406 (Up to OC-48/STM-16) ZL30415 (Up to OC-12/STM-4) 20 MHz Osc. IED;J%I:>WdZF:>B_d[9WhZikfjeE9#)%IJC#' Clock and frame pulse phase re-alignment to compensate backplane delays SONET/SDH/PDH Network Interface DPLL Tertiary Clock Provides Additional Synchronization and Clock Monitoring Available Output Frequencies 8 Clocks ZL30106 4 Sync. (Frame Pulses) Clock Control & Monitoring 20 MHz Osc. Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively Zarlink) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee expressed or implied is made regarding the capability, performance or suitability of any product or service. ZARLINK, ZL, and the Zarlink logo are trademarks of Zarlink Semiconductor Inc. Advanced TCA is the trademark of PCI Industrial Computer Manufacturers Group. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved. Publication Number PP5880 www.ZARLINK.com 2, 8 kHz 1.544, 2.048, 3.088, 4.096, 6.312, 8.192, 8.448, 16.384, 19.44, 32.768, 34.368, 44.736, or 65.536 MHz STM-1/OC-3 Framer, Mapper SERDES DS3/E3 DS2/E2 Mux., Framers T1/E1/J1 Framers TDM Bus Clocks