ZL30414 SONET/SDH Clock Multiplier PLL Data Sheet Features • February 2005 Meets jitter requirements of Telcordia GR-253CORE for OC-192, OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM64, STM-16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at 622.08 MHz • Provides a CML differential clock at 155.52 MHz • Provides a single-ended CMOS clock at 19.44 MHz • Lock Indicator • Provides enable/disable control of output clocks • Accepts a CMOS reference at 19.44 MHz • 3.3 V supply Ordering Information ZL30414QGC 64 Pin TQFP Trays ZL30414QGC1 64 Pin TQFP* Trays *Pb Free Matte Tin -40°C to +85°C Description The ZL30414 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30414 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 rates. Applications • SONET/SDH line cards • Network Element timing cards The ZL30414 accepts a CMOS compatible reference at 19.44 MHz and generates four LVPECL differential output clocks at 622.08 MHz, a CML differential clock at 155.52 MHz and a single-ended CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled. The ZL30414 provides a LOCK indication. C622oEN-A C622oEN-B C622oEN-C C622oEN-D LPF C622oP/N-A C19i Frequency & Phase Detector Loop Filter VCO Frequency Dividers and Clock Drivers 19.44MHz State Machine Reference and Bias Circuit LOCK BIAS C622oP/N-B C622oP/N-C C622oP/N-D C155oP/N C19o VDD GND VCC C155oEN C19oEN 05 Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. ZL30414 GND C622oN-A C622oP-A VCC GND C622oP-B C622oN-B VCC GND C622oN-C C622oP-C VCC GND C622oP-D C622oN-D VCC Data Sheet GND VCC1 VCC C155oN C155oP GND VCC2 LPF GND GND 62 60 58 56 54 52 50 65 - EP_GND 48 46 4 44 6 42 8 ZL30414 40 10 38 12 36 14 34 16 18 20 22 24 26 28 30 32 GND VCC VDD GND VCC GND VDD GND NC GND GND LOCK GND C19o VDD GND GND VDD NC NC NC VDD IC NC NC C19oEN GND C19i VDD GND VDD GND BIAS C155oEN C622oEN-A C622oEN-B C622oEN-C C622oEN-D 64 2 Figure 2 - TQFP 64 pin (Top View) Pin Description Pin Description Table Pin # Name Description 1 GND Ground. 0 volt 2 VCC1 Positive Analog Power Supply. +3.3 V ±10%. 3 VCC Positive Analog Power Supply. +3.3 V ±10%. 4 5 C155oN C155oP 6 GND Ground. 0 volt 7 VCC2 Positive Analog Power Supply. +3.3 V ±10% 8 LPF Low Pass Filter (Analog). Connect to this pin external RC network (RF and CF) for the low pass filter. 9 GND Ground. 0 volt 10 GND Ground. 0 volt C155 Clock Output (CML). These outputs provide a differential 155.52 MHz clock. 2 Zarlink Semiconductor Inc. ZL30414 Data Sheet Pin Description Table (continued) Pin # Name 11 BIAS 12 Description Bias. See Figure 13 for the recommended bias circuit. C155oEN C155o Clock Enable (CMOS Input). If tied high this control pin enables the C155oP/N differential driver. Pulling this input low disables the output clock and deactivates differential drivers. 13 C622oEN-A C622 Clock Output Enable A (CMOS Input). If tied high this control pin enables the C622oP/N-A output clock. Pulling this input low disables the output clock without deactivating differential drivers. 14 C622oEN-B C622 Clock Output Enable B (CMOS Input). If tied high this control pin enables the C622oP/N-B output clock. Pulling this input low disables the output clock without deactivating differential drivers. 15 C622oEN-C C622 Clock Output Enable C (CMOS Input). If tied high this control pin enables the C622oP/N-C output clock.Pulling this input low disables the output clock without deactivating differential drivers. 16 C622oEN-D C622 Clock Output Enable D (CMOS Input). If tied high this control pin enables the C622oP/N-D output clock.Pulling this input low disables the output clock without deactivating differential drivers. 17 GND Ground. 0 volt 18 VDD Positive Digital Power Supply. +3.3 V ±10% 19 NC No internal bonding Connection. Leave unconnected. 20 NC No internal bonding Connection. Leave unconnected. 21 NC No internal bonding Connection. Leave unconnected. 22 VDD 23 IC Internal Connection. Connect this pin to Ground (GND). 24 NC No internal bonding Connection. Leave unconnected. 25 NC No internal bonding Connection. Leave unconnected. 26 C19oEN 27 Positive Digital Power Supply. +3.3 V ±10% C19o Output Enable (CMOS Input). If tied high this control pin enables the C19o output clock. Pulling this pin low forces output driver into a high impedance state. GND Ground. 0 volt C19i C19 Reference Input (CMOS Input). This pin is a single-ended input reference source used for synchronization. This pin accepts 19.44 MHz. 29 VDD Positive Digital Power Supply. +3.3 V ±10% 30 GND Ground. 0 volt 31 VDD Positive Digital Power Supply. +3.3 V ±10% 32 GND Ground. 0 volt 28 3 Zarlink Semiconductor Inc. ZL30414 Data Sheet Pin Description Table (continued) Pin # Name 33 GND Ground. 0 volt 34 VDD Positive Digital Power Supply. +3.3 V ±10% C19o C19 Clock Output (CMOS Output). This pin provides a single-ended CMOS clock at 19.44 MHz. 36 GND Ground. 0 volt 37 LOCK Lock Indicator (CMOS Output). This output goes high when PLL is frequency locked to the input reference C19i. 38 GND Ground. 0 volt 39 GND Ground. 0 volt 40 NC 41 GND Ground. 0 volt 42 VDD Positive Digital Power Supply. +3.3 V ±10% 43 GND Ground. 0 volt 44 VCC Positive Analog Power Supply. +3.3 V ±10% 45 GND Ground. 0 volt 46 VDD Positive Digital Power Supply. +3.3 V ±10% 47 VCC Positive Analog Power Supply. +3.3 V ±10% 48 GND Ground. 0 volt 49 VCC Positive Analog Power Supply. +3.3 V ±10%. 35 50 51 C622oN-D C622oP-D Description No internal bonding Connection. Leave unconnected. C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current. 52 GND Ground. 0 volt 53 VCC Positive Analog Power Supply. +3.3 V ±10%. 54 55 C622oP-C C622oN-C C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current. 56 GND Ground. 0 volt 57 VCC Positive Analog Power Supply. +3.3 V ±10%. 58 59 C622oN-B C622oP-B C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current. 4 Zarlink Semiconductor Inc. ZL30414 Data Sheet Pin Description Table (continued) 1.0 Pin # Name Description 60 GND Ground. 0 volt 61 VCC Positive Analog Power Supply. +3.3 V ±10%. 62 63 C622oP-A C622oN-A 64 GND 65 NC C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt No internal bonding Connection. Leave unconnected. Functional Description The ZL30414 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30414 is shown in Figure 1 and a brief description is presented in the following sections. 1.1 Frequency/Phase Detector The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit. 1.2 Lock Indicator The ZL30414 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency then the LOCK pin is set high. The LOCK pin is pulled low if the frequency difference exceeds ±1000 ppm. 1.3 Loop Filter The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF pin and ground as shown in Figure 3. ZL30414 Frequency and Phase Detector LPF Loop RF Filter VCO RF=8.2 kΩ, CF=470 nF CF Figure 3 - Loop Filter Elements 5 Zarlink Semiconductor Inc. ZL30414 1.4 Data Sheet VCO The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers and Clock Drivers" block that divides VCO frequency and buffer generated clocks. 1.5 Output Interface Circuit The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at 622.08 MHz, one CML differential clock at 155.52 MHz and a single-ended 19.44 MHz output clock. This block provides also a 19.44 MHz feedback clock that closes PLL loop. Each output clock can be enabled or disabled individually with the associated Output Enable pin. Output Clocks Output Enable Pins C622oP/N-A C622oEN-A C622oP/N-B C622oEN-B C622oP/N-C C622oEN-C C622oP/N-D C622oEN-D C155oP/N C155oEN C19o C19oEN Table 1 - Output Enable Control To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations. 6 Zarlink Semiconductor Inc. ZL30414 2.0 Data Sheet ZL30414 Performance The following are some of the ZL30414 performance indicators that complement results listed in the Characteristics section of this data sheet. 2.1 Input Jitter Tolerance Jitter tolerance is a measure of the PLL’s ability to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its input reference. The input jitter tolerance of the ZL30414 is shown in Figure 4. On this graph, the single line at the top represents measured input jitter tolerance and the three overlapping lines below represent minimum input jitter tolerance for OC-192, OC-48, and OC-12 network interfaces. The jitter tolerance is expressed in picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates. Figure 4 - Input Jitter Tolerance 7 Zarlink Semiconductor Inc. ZL30414 2.2 Data Sheet Jitter Transfer Characteristic Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a PLL. This ratio is expressed in dB and it characterizes the PLLs ability to attenuate (filter) jitter. The jitter transfer characteristic for the ZL30414 configured with recommended loop filter components (RF=8.2 kΩ, CF=470 nF) is shown in Figure 5. The plotted curves represent jitter transfer characteristics over the recommended voltage (3.0 V to 3.6 V) and temperature (-40C to 85C) ranges. Figure 5 - Jitter Transfer Characteristic 8 Zarlink Semiconductor Inc. ZL30414 3.0 Applications 3.1 Ultra-Low Jitter SONET/SDH Equipment Clocks Data Sheet The ZL30414 functionality and performance complements the entire family of the Zarlink’s advanced network synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating up to OC-192/STM-64 rate (10 Gbit/s). The ZL30414 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 6) . C19i ZL30414 C622oA LVPECL 622.08 MHz C622oB LVPECL 622.08 MHz C622oC LVPECL 622.08 MHz C622oD LVPECL 622.08 MHz CML 155.52 MHz C155o C19o CMOS C155oEN C19o PRI C155o SEC Synchronization Reference Clocks RefSel RefAlign ZL30407 or PRIOR SECOR MT90401 CMOS LVDS 19.44 MHz 155.52 MHz C34o/C44o CMOS C16o CMOS 16.384 MHz C8o CMOS 8.192 MHz 34.368 MHz or 44.736 MHz C6o CMOS 6.312 MHz C4o CMOS 4.096 MHz C2o CMOS 2.048 MHz C1.5o CMOS 1.544 MHz F16o CMOS F8o CMOS F0o CMOS D0 - D7 A0 - A6 CS R/W DS C20i LOCK HOLDOVER 20 MHz OCXO 19.44 MHz C19oEN C622oEN-D RF C622oEN-C LOCK C622oEN-A CF C622oEN-B LPF Data Port uP Controller Port Note: Only main functional connections are shown Figure 6 - SONET/SDH Equipment Clock 9 Zarlink Semiconductor Inc. 8 kHz 8 kHz 8 kHz ZL30414 Data Sheet The ZL30414 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 7). C19i ZL30414 C622oA LVPECL 622.08 MHz C622oB LVPECL 622.08 MHz C622oC LVPECL 622.08 MHz C622oD LVPECL 622.08 MHz CML 155.52 MHz C155o C19o PRI SEC Synchronization Reference Clocks RSEL MT9046 LOCK HOLDOVER C19o CMOS C16o CMOS 16.384 MHz C8o CMOS 8.192 MHz 19.44 MHz C6o CMOS 6.312 MHz C4o CMOS 4.096 MHz C2o CMOS 2.048 MHz C1.5o CMOS 1.544 MHz 8 kHz F16o CMOS F8o CMOS F0o CMOS TCLR PCCi FS2 FS1 MS1 MS2 20 MHz TCXO FLOCK C20i 19.44 MHz C19oEN C155oEN C622oEN-D C622oEN-C C2 C622oEN-B R1 C1 LOCK R1 = 680 Ω C1 = 820 nF C2 = 22 nF C622oEN-A LPF CMOS uC Hardware Control Note: Only main functional connections are shown Figure 7 - SONET/SDH Line Card 10 Zarlink Semiconductor Inc. 8 kHz 8 kHz ZL30414 3.2 3.2.1 Data Sheet Recommended Interface circuit LVPECL to LVPECL Interface The C622oP/N-A, C622oP/N-B, C622oP/N-B, and C622oP/N-D outputs provide differential LVPECL clocks at 622.08 MHz. The LVPECL output drivers require a 50 Ω termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed as close as possible to the LVPECL receiver. +3.3 V 0.1 uF ZL30414 VCC=+3.3 V VCC LVPECL Driver Z=50 Ω C622oP-A R1 R1 R2 R2 LVPECL Receiver Z=50 Ω 622.08 MHz C622oN-A GND Typical resistor values: R1 = 130 Ω, R2 =82 Ω Figure 8 - LVPECL to LVPECL Interface 3.2.2 CML to CML Interface The C155o output provides a differential CML/LVDS compatible clock at 155.52 MHz. The output drivers require a 50 Ω load at the terminating end if the receiver is CML type. +3.3 V ZL30414 CML Driver 0.1 uF VCC C155oP 0.1 uF Z=50 Ω Low impedance DC bias source 50 Ω Z=50 Ω 155.52 MHz C155oN 0.1 uF GND Figure 9 - CML to CML Interface 11 Zarlink Semiconductor Inc. 50 Ω CML Receiver ZL30414 3.2.3 Data Sheet CML to LVDS Interface To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the VCM (common mode voltage) as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for LVDS applications. +3.3 V 0.1 uF ZL30414 VCC=+3.3 V VCC CML Driver 10 nF Z=50 Ω C155oP R1 R1 100 Ω Z=50 Ω 155.52 MHz LVDS Receiver C155oN 10 nF R2 R2 GND Typical resistor values: R1 = 16 kΩ, R2 = 10 kΩ Figure 10 - LVDS Termination 3.2.4 CML to LVPECL Interface The CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as close as possible to the LVPECL receiver. +3.3 V 0.1 uF ZL30414 CML Driver VCC=+3.3 V VCC C155oP Z=50 Ω 10 nF R1 R1 R2 R2 Z=50 Ω 155.52 MHz C155oN 10 nF GND Typical resistor values: R1 = 82 Ω, R2 =130 Ω Figure 11 - CML to LVPECL Interface 12 Zarlink Semiconductor Inc. LVPECL Receiver ZL30414 3.3 Data Sheet Tristating LVPECL Outputs The ZL30414 has four differential 622.08 MHz LVPECL outputs, which can be used to drive four different OC-3/OC12/OC-48/OC-192 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required, a user can disable unused LVPECL outputs on the ZL30414 by pulling the corresponding enable pins low. When disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V. For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling can be used as shown in Figure 12. Typically this might be required in hot swappable applications. Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC coupling capacitors. During disable mode (C622oEN pin pulled low) those capacitors present infinite impedance to the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6 are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4, R5 and R6 should not be populated. C622oEN 3.3 V 3.3 V ZL30414 C1 0.1 u Z=50 R3 127 R5 127 R4 82.5 R6 82.5 Z=50 R1 200 R2 200 C2 0.1 u Figure 12 - Tristatable LVPECL Outputs 13 Zarlink Semiconductor Inc. ZL30414 3.4 Data Sheet Power Supply and BIAS Circuit Filtering Recommendations Figure 13 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink’s web site for updates. 0.1 uF 0.1 uF 0.1 uF 0.1 uF 0.1 uF Ferrite Bead 0.1 uF 10 uF 0.1 uF VCC1 VCC + 33 uF 0.1 uF 33 uF 220 Ω 0.1 uF BIAS + 33 uF 64 62 0.1 uF VCC GND VCC GND VCC 60 58 56 54 52 50 46 GND VCC VDD 44 VCC 48 2 4 VCC2 + GND 0.1 uF GND 4.7 Ω + VCC GND +3.3 V Power Rail GND 6 GND GND 42 8 0.1 uF VDD 0.1 uF GND ZL30414 GND 10 GND 0.1 uF 40 GND GND 38 11 12 GND 36 14 34 16 26 0.1 uF 28 0.1 uF 30 32 0.1 uF GND VDD GND 24 VDD 22 GND 20 VDD GND VDD 18 VDD GND 0.1 uF Notes: 1. All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same ground plane. 2. Select Ferrite Bead with IDC > 400 mA and RDC in a range from 0.10 Ω to 0.15 Ω Figure 13 - Power Supply and BIAS Circuit Filtering 14 Zarlink Semiconductor Inc. ZL30414 4.0 Data Sheet Characteristics Absolute Maximum Ratings† Characteristics Sym. Min.‡ Max.‡ Units VDDR, VCCR TBD TBD V 1 Supply voltage 2 Voltage on any pin VPIN -0.5 VCC + 0.5 VDD + 0.5 V 3 Current on any pin IPIN -0.5 30 mA 4 ESD Rating 1250 V 5 Storage temperature TST 125 °C 6 Package power dissipation PPD 1.8 W VESD -55 † Voltages are with respect to ground unless otherwise stated. ‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions† Characteristics 1 Operating Temperature 2 Positive Supply Sym. Min. Typ.‡ Max. Units TOP -40 25 +85 °C VDD, VCC 3.0 3.3 3.6 V Max. Units Notes Notes † Voltages are with respect to ground unless otherwise stated. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics† Characteristics Sym. Min. Typ.‡ 1 Supply Current IDD+ICC 146 mA LVPECL, CML drivers disabled and unterminated 2 Incremental Supply Current to single LVPECL driver (driver enabled and terminated, see Figure 8) ILVPECL 37 mA Note 1 Note 2 3 Incremental Supply Current to CML driver (driver enabled and terminated, see Figure 9) ICML 26 mA Note 3 4 CMOS: High-level input voltage VIH 0.7VDD VDD V 5 CMOS: Low-level input voltage VIL 0 0.3VDD V 6 CMOS: Input leakage current IIL 5 uA 1 15 Zarlink Semiconductor Inc. VI = VDD or 0 V ZL30414 Data Sheet DC Electrical Characteristics† (continued) Characteristics Sym. Min. Typ.‡ Max. Units Notes 7 CMOS: Input bias current for pulled-down inputs: C622oEN-A, C622oEN-C, C622oEN-D, OC-CLKoEN IB-PU 300 uA VI = VDD 8 CMOS: Input bias current for pulled-up inputs: , C622oEN-B, C19oEN IB-PD 90 uA VI = 0V 9 CMOS: High-level output voltage VOH V IOH = 8 mA 10 CMOS: Low-level output voltage VOL V IOL = 4 mA 11 LOCK pin: High-level output voltage VOH 12 LOCK pin: Low-level output voltage VOL 13 CMOS: C19o output rise time TR 1.8 3.3 ns 18 pF load 14 CMOS: C19o output fall time TF 1.1 1.4 ns 18 pF load 15 LVPECL: Differential output voltage (622.08 MHz) IVOD_LVPECLI 1.17 V Note 2 16 LVPECL: Offset voltage (622.08 MHz) V Note 2 17 LVPECL: Output rise/fall times (622.08 MHz) 18 CML: Differential output voltage (155.52 MHz) 19 CML: Offset voltage (155.52 MHz) 20 CML: Output rise/fall times (155.52 MHz) - 2.4 0.4 2.4 IOH = 0.5 mA 0.4 VOS_LVPECL Vcc1.31 Vcc1.20 Vcc1.09 IOL = 0.5 mA TRF 170 ps Note 2 IVOD_CMLI 0.73 V Note 3 V Note 3 ps Note 3 VOS_CML Vcc0.58 Vcc0.54 Vcc0.50 220 TRF †: Voltages are with respect to ground unless otherwise stated. ‡ :Typical figures are for design aid only: not guaranteed and not subject to production testing. Supply voltage and operating temperature are as per Recommended Operating Conditions Note 1: The ILVPECL current is determined by the termination network connected to LVPECL outputs. More than 25% of this current flows outside the chip and it does not contribute to the internal power dissipation. Note 2: LVPECL outputs terminated with ZT = 50 Ω resistors biased to VCC-2V (see Figure 8) Note 3: CML outputs terminated with ZT = 50 Ω resistors connected to low impedance DC bias voltage source (see Figure 9) 16 Zarlink Semiconductor Inc. ZL30414 Data Sheet AC Electrical Characteristics† - Output Timing Parameters Measurement Voltage Levels Characteristics Sym CMOS LVPECL CML Units VT-CMOS VT-LVPECL VT-CML 0.5VDD 0.5VOD_LVPECL 0.5VOD_CML V 1 Threshold Voltage 2 Rise and Fall Threshold Voltage High VHM 0.7VDD 0.8VOD_LVPECL 0.8VOD_CML V 3 Rise and Fall Threshold Voltage Low VLM 0.3VDD 0.2VOD_LVPECL 0.2VOD_CML V † Voltages are with respect to ground unless otherwise stated. Timing Reference Points VHM VT VLM All Signals tIF, tOF tIR, tOR Figure 14 - Output Timing Parameter Measurement Voltage Levels 17 Zarlink Semiconductor Inc. ZL30414 Data Sheet AC Electrical Characteristics† - C19i Input to C19o, C155o and C622o Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 C19i to C19o delay tC19D 6.2 7.2 8.2 ns 2 C19i to C155o delay tc155D 3 4 5 ns 3 C19i to C622oA delay tC622D 0 0.8 1.6 ns 4 C155o duty cycle dC155L 48 50 52 % 5 C622o duty cycle dC622L 48 50 52 % Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i VT-CMOS (19.44 MHz) tC19D C19o VT-CMOS (19.44 MHz) tC155D C155o (155.52 MHz) VT-CML tC622D C622oA VT-LVPECL (622.08 MHz) Figure 15 - C19i Input to C19o, C155o and C622o Output Timing 18 Zarlink Semiconductor Inc. ZL30414 Data Sheet AC Electrical Characteristics†- C622 Clocks Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 C622oA to C622oB tC622D-AB -50 0 +50 ps 2 C622oA to C622oC tC622D-AC -50 0 +50 ps 3 C622oA to C622oD tC622D-AD -50 0 +50 ps Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C622oA VT-LVPECL tC622D-AB VT-LVPECL C622oB tC622D-AC VT-LVPECL C622oC tC622D-AD C622oD VT-LVPECL Note: All output clocks have nominal 50% duty cycle. Figure 16 - C622oB, C622oC, C622oD Outputs Timing 19 Zarlink Semiconductor Inc. ZL30414 Data Sheet Performance Characteristics - Functional (VCC = 3.3 V ±10%; TA = -40 to 85°C ) Characteristics 1 Pull-in range 2 Lock Time Min. Typ. Max. Units ±1000 ppm 300 Notes At nominal input reference frequency C19i = 19.44 MHz ms Performance Characteristics : Output Jitter Generation - GR-253-CORE conformance (VCC = 3.3V ±10%; TA = -40 to 85°C ) ZL30414 Jitter Generation Performance GR-253-CORE Jitter Generation Requirements Interface (Category II) 1 2 3 Jitter Measurement Filter OC-192 STS-192 50 kHz - 80 MHz OC-48 STS-48 12 kHz - 20 MHz OC-12 STS-12 12 kHz - 5 MHz Equivalent limit in time domain Typ.† Max.‡ 0.1 UIPP 10.0 - 7.31 psP-P 0.01 UIRMS 1.0 0.52 0.94 psRMS 0.1 UIPP 40.2 - 7.32 psP-P 0.01 UIRMS 4.02 0.58 0.83 psRMS 0.1 UIPP 161 - 4.37 psP-P 0.01 UIRMS 16.1 0.34 0.60 psRMS Limit in UI † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF 20 Zarlink Semiconductor Inc. Units ZL30414 Data Sheet Performance Characteristics : Output Jitter Generation - G.813 conformance (Option 1 and 2) (VCC = 3.3V ±10%; TA = -40 to 85°C ) ZL30414 Jitter Generation Performance G.813 Jitter Generation Requirements Interface Jitter Measurement Filter Limit in UI Equivalent limit in time domain Typ.† Max.‡ 10.0 - 6.95 psP-P 0.49 0.89 psRMS - 11.5 psP-P 0.82 1.04 psRMS - 6.40 psP-P 0.50 0.68 psRMS - 8.67 psP-P 0.68 1.06 psRMS - 3.33 psP-P 0.26 0.42 psRMS - 19.1 psP-P 1.51 2.88 psRMS - 6.95 psP-P 0.49 0.89 psRMS - 11.5 psP-P 0.82 1.04 psRMS - 7.32 psP-P 0.58 0.83 psRMS - 4.37 psP-P 0.34 0.60 psRMS Units Option 1 1 STM-64 4 MHz to 80 MHz 20 kHz to 80 MHz 2 STM-16 1 MHz to 20 MHz 5 kHz to 20 MHz 3 STM-4 250 kHz to 5 MHz 1 kHz to 5 MHz 0.1 UIpp 0.5 UIpp 50.2 0.1 UIpp 40.2 0.5 UIpp 201 0.1 UIpp 161 0.5 UIpp 804 Option 2 5 STM-64 4 MHz to 80 MHz 20 kHz to 80 MHz 6 7 STM-16 STM-4 12 kHz - 20 MHz 12 kHz - 5 MHz 0.1 UIpp 10.0 0.3 UIpp 30.1 0.1 UIpp 40.2 0.1 UIpp 161 † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF 21 Zarlink Semiconductor Inc. ZL30414 Data Sheet Performance Characteristics : Output Jitter Generation - ETSI EN 300 462-7-1conformance (VCC = 3.3V ±10%; TA = -40 to 85°C ) ZL30414 Jitter Generation Performance EN 300 462-7-1 Jitter Generation Requirements Interface 1 STM-16 Jitter Measurement Filter 1 MHz to 20 MHz 5 kHz to 20 MHz 2 STM-4 250 kHz to 5 MHz 1 kHz to 5 MHz Limit in UI Equivalent limit in time domain Typ.† Max.‡ 40.2 - 6.40 psP-P 0.50 0.68 psRMS - 8.67 psP-P 0.68 1.06 psRMS - 3.33 psP-P 0.26 0.42 psRMS - 19.1 psP-P 1.51 2.88 psRMS 0.1 UIpp 0.5UIpp 201 0.1 UIpp 161 0.5 UIpp 804 † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF 22 Zarlink Semiconductor Inc. Units Package Code c Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. 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