ZL30406 SONET/SDH Clock Multiplier PLL Data Sheet Features February 2005 • Meets jitter requirements of Telcordia GR-253CORE for OC-48, OC-12, and OC-3 rates • Meets jitter requirements of ITU-T G.813 for STM16, STM-4 and STM-1 rates • Provides four LVPECL differential output clocks at 77.76 MHz • Provides a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz • Provides a single-ended CMOS clock at 19.44 MHz • Provides enable/disable control of output clocks • Accepts a CMOS reference at 19.44 MHz • 3.3 V supply Ordering Information ZL30406QGC 64 Pin TQFP ZL30406QGC1 64 Pin TQFP* *Pb Free Matte Tin -40°C to +85°C Description The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30406 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-16, STM-4 and STM-1 rates. Applications • SONET/SDH line cards • Network Element timing cards Trays Trays The ZL30406 accepts a CMOS compatible reference at 19.44 MHz and generates four LVPECL differential output clocks at 77.76 MHz, a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz and a single-ended CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled. C77oEN-A C77oEN-B OC-CLKoEN LPF C77o ,C155o C19o, C38o, CML-P/N outputs OC-CLKoP/N C19i Frequency & Phase Detector Loop Filter Output VCO Interface Circuit C77oP/N-A C77oP/N-B C77oP/N-C 19.44MHz C77oP/N-D BIAS Reference & Bias circuit VDD GND C19o VCC FS1-2 C19oEN C77oEN-C C77oEN-D 15 Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. ZL30406 GND C77oN-A C77oP-A VCC GND C77oP-B C77oN-B VCC GND C77oN-C C77oP-C VCC GND C77oP-D C77oN-D VCC Data Sheet 64 2 62 60 58 56 54 52 50 65 - EP_GND 48 46 4 44 6 42 ZL30406 8 40 10 38 12 36 14 34 16 18 20 22 24 26 28 30 32 GND VCC VDD GND VCC GND VDD GND NC GND GND NC GND C19o VDD GND GND VDD NC NC NC VDD IC FS2 FS1 C19oEN GND C19i VDD GND NC GND GND VCC1 VCC OC-CLKoN OC-CLKoP GND VCC2 LPF GND GND BIAS OC-CLKoEN C77oEN-A C77oEN-B C77oEN-C C77oEN-D Figure 2 - TQFP 64 pin (Top View) Pin Description Pin Description Table Pin # Name Description 1 GND Ground. 0 volt. 2 VCC1 Positive Analog Power Supply. +3.3 V ±10% 3 VCC Positive Analog Power Supply. +3.3 V ±10% 4 5 OC-CLKoN OC-CLKoP 6 GND Ground. 0 volt 7 VCC2 Positive Analog Power Supply. +3.3 V ±10% SONET/SDH Clock (CML Output). These outputs provide a programmable differential CML clock at 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz. The output frequency is selected with FS2 and FS1 pins. LPF Low Pass Filter (Analog). Connect to this pin external RC network (RF and CF) for the low pass filter. 9 GND Ground. 0 volt 10 GND Ground. 0 volt 11 BIAS Bias. See Figure 11 for the recommended bias circuit. 8 2 Zarlink Semiconductor Inc. ZL30406 Data Sheet Pin Description Table (continued) Pin # Name Description 12 OC-CLKoEN SONET/SDH Clock Enable (CMOS Input). If tied high this control pin enables the OC-CLKoP/N differential driver. Pulling this input low disables the output clock without deactivating differential drivers. C77oEN-A C77 Clock Output Enable A (CMOS Input). If tied high this control pin enables the C77oP/N-A output clock. Pulling this input low disables the output clock without deactivating differential drivers. C77oEN-B C77 Clock Output Enable B (CMOS Input). If tied high this control pin enables the C77oP/N-B output clock. Pulling this input low disables the output clock without deactivating differential drivers. C77oEN-C C77 Clock Output Enable C (CMOS Input). If tied high this control pin enables the C77oP/N-C output clock. Pulling this input low disables the output clock without deactivating differential drivers. C77oEN-D C77 Clock Output Enable D (CMOS Input). If tied high this control pin enables the C77oP/N-D output clock. Pulling this input low disables the output clock without deactivating differential drivers. 13 14 15 16 17 GND Ground. 0 volt 18 VDD Positive Digital Power Supply. +3.3 V ±10% 19 NC No internal bonding Connection. Leave unconnected. 20 NC No internal bonding Connection. Leave unconnected. 21 NC No internal bonding Connection. Leave unconnected. 22 VDD 23 IC 24 25 FS2 FS1 26 C19oEN 27 GND Ground. 0 volt 28 C19i C19 Reference Input (CMOS Input). This pin is a single-ended input reference source used for synchronization. This pin accepts 19.44 MHz. 29 VDD Positive Digital Power Supply. +3.3 V ±10% 30 GND Ground. 0 volt 31 NC 32 GND Ground. 0 volt. 33 GND Ground. 0 volt 34 VDD Positive Digital Power Supply. +3.3 V ±10% 35 C19o C19 Clock Output (CMOS Output). This pin provides a single-ended CMOS clock at 19.44 MHz. Positive Digital Power Supply. +3.3 V ±10% Internal Connection. Connect this pin to Ground (GND). Frequency Select 2-1 (CMOS Input). These inputs program the clock frequency on the OC-CLKo output. The possible output frequencies are 19.44 MHz (00), 38.88 MHz (01), 77.76 MHz (10), 155.52 MHz (11). C19o Output Enable (CMOS Input). If tied high this control pin enables the C19o output clock. Pulling this pin low forces output driver into a high impedance state. No internal bonding Connection. Leave unconnected. 3 Zarlink Semiconductor Inc. ZL30406 Data Sheet Pin Description Table (continued) Pin # Name Description 36 GND 37 NC 38 GND Ground. 0 volt 39 GND Ground. 0 volt 40 NC 41 GND Ground. 0 volt 42 VDD Positive Digital Power Supply. +3.3 V ±10% 43 GND Ground. 0 volt 44 VCC Positive Analog Power Supply. +3.3 V ±10% 45 GND Ground. 0 volt 46 VDD Positive Digital Power Supply. +3.3 V ±10% 47 VCC Positive Analog Power Supply. +3.3 V ±10% 48 GND Ground. 0 volt 49 VCC Positive Analog Power Supply. +3.3 V ±10%. 50 51 C77oN-D C77oP-D 52 GND Ground. 0 volt 53 VCC Positive Analog Power Supply. +3.3 V ±10%. 54 55 C77oP-C C77oN-C 56 GND Ground. 0 volt 57 VCC Positive Analog Power Supply. +3.3 V ±10%. 58 59 C77oN-B C77oP-B 60 GND Ground. 0 volt 61 VCC Positive Analog Power Supply. +3.3 V ±10%. 62 63 C77oP-A C77oN-A 64 GND 65 EP_GND Ground. 0 volt No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated to decrease supply current. C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated to decrease supply current. C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated to decrease supply current. C77 Clock Output (LVPECL Output). These outputs provide a differential LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated to decrease supply current. Ground. 0 volt Exposed die Pad Ground. 0 volt (connect to GND) 4 Zarlink Semiconductor Inc. ZL30406 1.0 Data Sheet Functional Description The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30406 is shown in Figure 1 and a brief description is presented in the following sections. 1.1 Frequency/Phase Detector The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit and averaged to control the VCO frequency. 1.2 Loop Filter The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF pin and ground as shown below. ZL30406 LPF Internal Loop Filter RF CF RF=8.2 kΩ, CF=470 nF (for 14 kHz PLL bandwidth) Figure 3 - External Loop Filter 1.3 VCO The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the voltage of the error signal, generates a primary frequency. The VCO output is connected to the Output Interface Circuit that divides VCO frequency and buffers generated clocks. 5 Zarlink Semiconductor Inc. ZL30406 1.4 Data Sheet Output Interface Circuit The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at 77.76 MHz, one programmable CML differential clock (19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz) controlled with FS1-2 pins and a single-ended 19.44 MHz output clock. This block provides also a 19.44 MHz feedback clock that closes PLL loop. Each output clock can be enabled or disabled individually with the associated Output Enable pin. Output Clocks Output Enable Pins C77oP/N-A C77oEN-A C77oP/N-B C77oEN-B C77oP/N-C C77oEN-C C77oP/N-D C77oEN-D OC-CLKoP/N OC-CLKoEN C19o C19oEN Table 1 - Output Enable Control To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations. The output clock frequency of the OC-CLKo CML differential output clock is selected with FS1-2 pins as shown in the following table. FS2 FS1 OC-CLKo Frequency 0 0 19.44 MHz 0 1 38.88 MHz 1 0 77.76 MHz 1 1 155.52 MHz Table 2 - OC-CLKo Clock Frequency Selection 6 Zarlink Semiconductor Inc. ZL30406 2.0 Applications 2.1 Ultra-Low Jitter SONET/SDH Equipment Clocks Data Sheet The ZL30406 functionality and performance complements the entire family of the Zarlink’s advanced network synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating at OC-48/STM-16 rate (2.5 Gbit/s). The ZL30406 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 4). C19i OC-CLKo C77oA C77oB C77oC C77oD C19o ZL30406 CML LVPECL LVPECL LVPECL LVPECL CMOS C19oEN C77oEN-D C77oEN-C CF C77oEN-B RF C77oEN-A OC-CLKoEN LPF PRI SEC Synchronization Reference Clocks RefSel RefAlign MT90401 or PRIOR SECOR ZL30407 D0 - D7 R/W A0 - A6 DS CS C20i LOCK HOLDOVER 20 MHz OCXO 155.52 MHz, 77.76 MHz 38.88 MHz, 19.44 MHz 77.76 MHz 77.76 MHz 77.76 MHz 77.76 MHz 19.44 MHz C19o C155o C34o/C44o C16o C8o C6o C4o C2o C1.5o F16o F8o CMOS LVDS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS F0o CMOS Data Port uP Controller Port Note: Only main functional connections are shown Figure 4 - SONET/SDH Equipment Timing Card 7 Zarlink Semiconductor Inc. 19.44 MHz 155.52 MHz 34.368 MHz or 44.736 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHz 8 kHz ZL30406 Data Sheet The ZL30406 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 5). C19i OC-CLKo C77oA C77oB C77oC C77oD C19o ZL30406 PRI SEC Synchronization Reference Clocks RSEL MT9046 LOCK HOLDOVER FS1 FS2 MS1 MS2 20 MHz TCXO C19o C16o C8o C6o C4o C2o C1.5o F16o F8o CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS F0o CMOS FLOCK PCCi TCLR C20i 155.52 MHz, 77.76 MHz 38.88 MHz, 19.44 MHz 77.76 MHz 77.76 MHz 77.76 MHz 77.76 MHz 19.44 MHz C19oEN C77oEN-D C77oEN-C C2 C77oEN-B R1 C1 C77oEN-A R1 = 680 Ω C1 = 820 nF C2 = 22 nF OC-CLKoEN LPF CML LVPECL LVPECL LVPECL LVPECL CMOS uC Hardware Control Note: Only main functional connections are shown Figure 5 - SONET/SDH Line Card 8 Zarlink Semiconductor Inc. 19.44 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHz 8 kHz ZL30406 2.2 2.2.1 Data Sheet Recommended Interface circuit LVPECL to LVPECL Interface The C77oP/N-A, C77oP/N-B, C77oP/N-B, and C77oP/N-D outputs provide differential LVPECL clocks at 77.76 MHz. The LVPECL output drivers require a 50 Ω termination connected to the VCC-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed as close as possible to the LVPECL receiver. +3.3 V 0.1 uF ZL30406 VCC=+3.3 V VCC LVPECL Driver Z=50 Ω C77oP-A R1 R1 R2 R2 LVPECL Receiver Z=50 Ω C77oN-A GND Typical resistor values: R1 = 130 Ω, R2 =82 Ω Figure 6 - LVPECL to LVPECL Interface 2.2.2 CML to CML Interface The CMLP/N output provides a differential CML/LVDS compatible clock at 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz selected with FS1-2 pins. The output drivers require a 50 Ω load at the terminating end if the receiver is CML type. +3.3 V ZL30406 CML Driver Low Impedance DC bias source 0.1 uF VCC OC-CLKoP 0.1 uF Z=50 Ω 50 Ω Z=50 Ω OC-CLKoN 0.1 uF GND Figure 7 - CML to CML Interface 9 Zarlink Semiconductor Inc. 50 Ω CML Receiver ZL30406 2.2.3 Data Sheet CML to LVDS Interface To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the VCM (common mode voltage) as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for LVDS applications. +3.3 V 0.1 uF ZL30406 CML Driver VCC=+3.3 V VCC Z=50 Ω OC-CLKoP 10 nF LVDS Receiver R1 R1 100Ω Z=50 Ω OC-CLKoN 10 nF R2 R2 GND Typical resistor values: R1 = 16 kΩ, R2 = 10 kΩ Figure 8 - LVDS Termination 2.2.4 CML to LVPECL Interface In the case when more than four 77.76 MHz clocks are required to drive LVPECL receivers then the unused OCCLKo clock (CML output) can be configured to output the 77.76 MHz clock and interface to the LVPECL receiver as is shown in the Figure 9. The terminating resistors should be placed as close as possible to the LVPECL receiver. +3.3 V VCC CML Driver 0.1 uF VCC=+3.3 V ZL30406 Z=50 Ω OC-CLKoP 77.76MHz 10 nF R1 R1 R2 R2 Z=50 Ω OC-CLKoN 10 nF GND Typical resistor values: R1 = 82 Ω, R2 =130 Ω Figure 9 - CML to LVPECL Interface 10 Zarlink Semiconductor Inc. LVPECL Receiver ZL30406 2.3 Data Sheet Tristating LVPECL Outputs The ZL30406 has four differential 77.76 MHz LVPECL outputs, which can be used to drive four different OC-3/OC12/OC-48 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required, a user can disable unused LVPECL outputs on the ZL30406 by pulling the corresponding enable pins low. When disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V. For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling capacitors can be used as shown in Figure 10. Typically this might be required in hot swappable applications. Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC coupling capacitors. During disable mode (C77oEN pin pulled low) those capacitors present infinite impedance to the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6 are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4, R5 and R6 should not be populated. C77oEN 3.3 V 3.3 V ZL30406 C1 0.1 u Z=50 R3 127 R5 127 R4 82.5 R6 82.5 Z=50 R1 200 R2 200 C2 0.1 u Figure 10 - Tristatable LVPECL Outputs 11 Zarlink Semiconductor Inc. ZL30406 2.4 Data Sheet Power Supply and BIAS Circuit Filtering Recommendations Figure 11 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink’s web site for updates. 0.1uF 0.1uF 0.1 uF 0.1uF 0.1uF 4.7 Ω + 33 uF 0.1 uF VCC2 + 33 uF 220 Ω 0.1 uF BIAS + 33 uF 0.1 uF 60 58 56 54 52 6 GND 8 ZL30406 GND 10GND 11 12 50 48 46 GND 44 GND 42 GND 40 GND GND38 4 GND VCC VDD VCC VDD 0.1 uF 0.1 uF 0.1 uF GND36 14 34 22 24 26 0.1uF GND 0.1uF 28 VDD 20 VDD 18 GND VDD 16 VCC GND VCC GND VCC GND 0.1 uF 62 30 32 VDD GND 0.1 uF GND + 0.1 uF 10 uF 0.1 uF GND 64 VCC1 2 VCC GND Ferrite Bead VCC GND +3.3 V Power Rail 0.1uF Notes: 1. All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same 2. Select Ferrite Bead with IDC > 400mA and R DC in a range from 0.10Ω to 0.15Ω Figure 11 - Power Supply and BIAS circuit filtering 12 Zarlink Semiconductor Inc. ZL30406 3.0 Data Sheet Characteristics Absolute Maximum Ratings† Characteristics Sym Min.‡ Max.‡ Units VDDR, VCCR TBD TBD V 1 Supply voltage 2 Voltage on any pin VPIN -0.5 VCC + 0.5 VDD + 0.5 V 3 Current on any pin IPIN -0.5 30 mA 4 ESD Rating 1500 V 5 Storage temperature TST 125 °C 6 Package power dissipation PPD 1.8 W VESD -55 † Voltages are with respect to ground unless otherwise stated. ‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions† Characteristics 1 Operating Temperature 2 Positive Supply Sym. Min. Typ.‡ Max. Units TOP -40 25 +85 °C VDD, VCC VCC_VCO 3.0 3.3 3.6 V Typ.‡ Max. Units Notes 155 mA LVPECL, CML drivers disabled and unterminated Notes † Voltages are with respect to ground unless otherwise stated. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ DC Electrical Characteristics† Characteristics Sym. Min. 1 Supply Current IDD+ICC 140 2 Incremental Supply Current to single LVPECL driver (driver enabled and terminated, see Figure 6) ILVPECL 40 mA Note 1,2 3 Incremental Supply Current to CML driver (driver enabled and terminated, see Figure 7) ICML 24 mA Note 3 4 CMOS: High-level input voltage VIH 0.7VDD VDD V 5 CMOS: Low-level input voltage VIL 0 0.3VDD V 6 CMOS: Input leakage current, C19i IIL 1 13 Zarlink Semiconductor Inc. uA VI = VDD or 0V ZL30406 Data Sheet DC Electrical Characteristics† (continued) Characteristics Sym. 7 CMOS: Input bias current for pulled-down inputs: FS1, FS2, C77oEN-A, C77oEN-C, C77oEN-D, OC-CLKoEN IB-PU 8 CMOS: Input bias current for pulled-up inputs: , C77oEN-B, C19o_EN IB-PD 9 CMOS: High-level output voltage VOH 10 CMOS: Low-level output voltage VOL 11 CMOS: C19o output rise time (18pF) TR 12 CMOS: C19o output fall time (18pF) 13 Min. Typ.‡ Max. Units Notes 300 uA VI = VDD 90 uA VI = 0V V IOH = 8 mA 0.4 V IOL = 4 mA 1.8 3.3 ns 18 pF load TF 1.1 1.4 ns 18 pF load LVPECL: Differential output voltage IVOD_LVPECLI 1.30 V Note 2 14 LVPECL: Offset voltage VOS_LVPECL V Note 2 15 LVPECL: Output rise/fall times 16 CML: Differential output voltage 17 CML: Offset voltage (Also referred to as common mode voltage) 18 CML: Output rise/fall times 2.4 Vcc1.38 Vcc1.27 Vcc1.15 TRF 260 ps Note 2 IVOD_CMLI 0.70 V Note 3 V Note 3 ps Note 3 VOS_CML Vcc0.58 Vcc0.54 120 TRF Vcc0.50 † : Voltages are with respect to ground unless otherwise stated. ‡ :Typical figures are for design aid only: not guaranteed and not subject to production testing. Note: Supply voltage and operating temperature are as per Recommended Operating Conditions Note 1: The ILVPECL current is determined by termination network connected to LVPECL outputs. More than 25% of this current flows outside the chip and it does not contribute to the internal power dissipation. Note 2: Note 3: LVPECL outputs terminated with ZT = 50 Ω resistors biased to VCC -2V (see Figure 6) CML outputs terminated with ZT = 50 Ω resistors connected to low impedance DC bias voltage source (see Figure 7) 14 Zarlink Semiconductor Inc. ZL30406 Data Sheet AC Electrical Characteristics† - Output Timing Parameters Measurement Voltage Levels Sym CMOS‡ LVPECL CML Units VT-CMOS VT-LVPECL VT-CML 0.5VDD 0.5VOD_LVPECL 0.5VOD_CML V Characteristics 1 Threshold Voltage 2 Rise and Fall Threshold Voltage High VHM 0.7VDD 0.8VOD_LVPECL 0.8VOD_CML V 3 Rise and Fall Threshold Voltage Low VLM 0.3VDD 0.2VOD_LVPECL 0.2VOD_CML V Timing Reference Points V HM VT V LM All Signals tIF, tOF tIR, t OR Figure 12 - Output Timing Parameter Measurement Voltage Levels AC Electrical Characteristics† - C19i Input to C19o and C77o Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 C19i to C19o delay tC19D 6.7 ns 2 C19i to C77oA delay tC77D -4 ns Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i V T-CMOS (19.44 MHz) tC19D C19o V T-CMOS (19.44 MHz) t C77D C77oA (77.76 MHz) V T-LVPECL Note: All output clocks have nominal 50% duty cycle. Figure 13 - C19i Input to C19o and C77o Output Timing 15 Zarlink Semiconductor Inc. ZL30406 Data Sheet AC Electrical Characteristics† - C19i Input to OC-CLKo Output Delay Timing (CML) Characteristics Sym. Min. Typ.‡ Max. Units 1 C19i to OC-CLKo(19) delay tOC-CLK19D 3.2 ns 2 C19i to OC-CLKo(38) delay tOC-CLK38D 3.0 ns 3 C19i to OC-CLKo(77) delay tOC-CLK77D 2.7 ns 4 C19i to OC-CLKo(155) delay tOC-CLK155D 2.4 ns Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. V T-CMOS C19i (19.44 MHz) tOC-CLK19D OC-CLKo(19) V T-CML (19.44 MHz) tOC-CLK38D OC-CLKo(38) V T-CML (38.88 MHz) tOC-CLK77D V T-CML OC-CLKo(77) (77.76 MHz) tOC-CLK155D OC-CLKo(155) (155.52 MHz) V T-CML Note: All output clocks have nominal 50% duty cycle. Figure 14 - C19i Input to OC-CLKo Output Timing 16 Zarlink Semiconductor Inc. ZL30406 Data Sheet AC Electrical Characteristics†- C77 Clocks Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 C77oA to C77oB tC77D-AB 100 ps 2 C77oA to C77oC tC77D-AC 100 ps 3 C77oA to C77oD tC77D-AD 100 ps Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C77oA V T-LVPECL t C77D-AB V T-LVPECL C77oB t C77D-AC V T-LVPECL C77oC tC77D-AD C77oD V T-LVPECL Note: All output clocks have nominal 50% duty cycle. Figure 15 - C77oB, C77oC, C77oD Outputs Timing 17 Zarlink Semiconductor Inc. ZL30406 Data Sheet Performance Characteristics - Functional- (VCC = 3.3V ±10%; TA = -40 to 85°C) Characteristics 1 Pull-in range 2 Lock Time Min. Max. ±1000 Units Notes ppm 300 ms Performance Characteristics: Output Jitter Generation - GR-253-CORE conformance - (VCC = 3.3V ±10%; TA = 40 to 85°C) GR-253-CORE Jitter Generation Requirements Interface (Category II) 1 2 Jitter Measurement Filter OC-48 STS-48 12 kHz - 20 MHz OC-12 STS-12 12 kHz - 5 MHz ZL30406 Jitter Generation Performance Equivalent limit in time domain Typ.† Max.‡ 0.1 UIpp 40.2 - 16.9 psP-P 0.01UIRMS 4.02 1.3 2.1 psRMS 0.1 UIpp 161 - 9.0 psP-P 0.01UIRMS 16.1 0.7 1.3 psRMS Limit in UI Units † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF Performance Characteristics: Output Jitter Generation - ETSI EN 300 462-7-1 conformance - (VCC = 3.3V ±10%; TA = -40 to 85°C) EN 300 462-7-1 Jitter Generation Requirements Interface 1 STM-16 Jitter Measurement Filter 1 MHz to 20 MHz 5 kHz to 20 MHz 2 STM-4 250 kHz to 5 MHz ZL30406 Jitter Generation Performance Limit in UI 0.1 UIpp 0.5UIpp 0.1 UIpp 0.5 UIpp 1 kHz to 5 MHz - Equivalent limit in time domain Typ.† Max.‡ 40.2 - 12.6 psP-P - 1.0 1.5 psRMS 201 - 17.1 psP-P - 1.3 2.2 psRMS 161 - 5.8 psP-P - 0.46 0.9 psRMS 804 - 29.8 psP-P - 2.4 3.2 psRMS † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF 18 Zarlink Semiconductor Inc. Units ZL30406 Data Sheet Performance Characteristics: Output Jitter Generation - G.813 conformance (Option 1 and 2) - (VCC = 3.3V ±10%; TA = -40 to 85°C) G.813 Jitter Generation Requirements Interface Jitter Measurement Filter ZL30406 Jitter Generation Performance Limit in UI Equivalent limit in time domain Typ.† Max.‡ 40.2 - 12.6 psP-P - 1.0 1.5 psRMS 201 - 17.1 psP-P - 1.3 2.2 psRMS 161 - 5.8 psP-P - 0.46 0.9 psRMS 804 - 29.8 psP-P - 2.4 3.2 psRMS 40.2 - 16.9 psP-P - 1.3 2.1 psRMS 161 - 9.0 psP-P - 0.7 1.3 psRMS Units Option 1 1 STM-16 1 MHz to 20 MHz 0.1 UIpp 0.5 UIpp 5 kHz to 20 MHz 2 STM-4 0.1 UIpp 250 kHz to 5 MHz 0.5 UIpp 1 kHz to 5 MHz - Option 2 3 STM-16 0.1 UIpp 12 kHz - 20 MHz 4 STM-4 0.1 UIpp 12 kHz - 5 MHz - † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF 19 Zarlink Semiconductor Inc. Package Code c Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. 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