SLIC Devices Applications of the Zarlink SLIC Devices SLIC Device Dial Pulse Performance Application Note APPLICATION NOTE In a Zarlink SLIC-based line circuit, the opening and closing of the dial switch produces a stream of dial pulses at the loop detector logic output pin (DET). Before it begins decoding the dial pulses, the exchange processor must often eliminate false pulses caused by contact bounce in the dial switch. To accomplish contact debouncing, the processor usually takes several samples during the period of each of the pulses emanating from the DET pin of the SLIC device. If the level at DET does not change for a given number of samples, then the DET level is interpreted as valid. It is necessary that the processor receives an adequate number of samples to accomplish this task. The amount of available time for processor debouncing is reduced when the SLIC device introduces a small amount of delay difference between loop-open and loop-closure detection. This delay difference results in what is commonly referred to as dial pulse distortion. The purpose of this application note is to describe and quantify expected dial pulse distortion in a Zarlink SLICbased line circuit. Using the data presented here, the linecard designer can optimize hardware and software for the best possible dial pulse performance. PRIMARY FACTORS AFFECTING DIAL PULSE DISTORTION Figure 1 is a simplified functional diagram showing the essential parts of the SLIC device that determine dial pulse performance. For simplicity, the diagram is only a single-ended representation of the longitudinally balanced, double-ended, two-wire circuit actually implemented. This is a simplified single-ended model where only single pins A/B and HPA/B represent A, B, HPA, and HPB, respectively. The single current amplifier K1 represents the combination of the Line A and Line B power amplifiers that are actually on the chip. If the dial switch shown in Figure 1 is in the closed position, current IL flows through load resistor RL. The DC feed characteristics programmed by RDC1 and RDC2 determine the magnitude of this current that the line current sense amplifier detects as the voltage drop across resistor RSENSE. The current sense amplifier feeds a current out of the RD pin that is 375 (see Note) times smaller than the actual loop current. Voltage VRD, which is proportional to the loop current, is generated across resistor RD. This voltage is compared, internally, to a 1.25 V reference. If VRD is greater than the reference, the DET pin drops to a logic Low, indicating a switch closure. Capacitor CD is connected across RD to filter out any high-frequency noise components that may cause a false switch-closure or switch-open detection. Major dial pulse delays are introduced at the SLIC RD pin as a result of the presence of capacitor CD. Exponential rise and fall times of voltage VRD cause delays between the time of a dial switch operation and the time when the DET output voltage reacts. As illustrated in Figure 2, the amount of time between a dial switch open and a logic High transition on the DET pin is Td open and the time from a dial switch on to a DET logic Low is Td closed. The difference between them (Td open–Td closed) is defined as the amount of dial pulse delay distortion in the system. In addition to the dependence of the dial pulse delays on RD and CD, the delays also depend, to a large extent, on the level of DC current in the telephone line. A lower programmed loop current means less delay from a dial switch open to a logic High at the DET pin. The reason for this can be seen by observing the VRD waveform in Figure 2. When the dial switch goes off, a lower level of loop current means a lower initial VRD voltage that requires less time to decay to the 1.25 V reference level. Conversely, when the dial switch closes, a lower level of loop current means that VRD is charging to a lower level and needs more time to reach the reference level. Note: Refer to the specific data sheet of each SLIC device for the actual value in the off hook detector current threshold. 375 is standard for most SLIC devices. Document ID# 080128 Date: Sep 21, 2007 Rev: C Version: 2 Distribution: Public Document SLIC Devices Figure 1. Application Note Simplified Functional Diagram for SLIC Dial Pulse Performance SLIC Dial Pulse Waveforms Switch Hook Threshold Comparator SLIC + + 1.25 V Reference DET – – VEE IL 375 Line Current Sense Amp RD RD VEE CD IL A/B K1 RRX RSN VRX RSENSE RL RT 400K Closed (Off Hook) Open (On Hook) – Shorting Circuit TX Amp VTX VTX Dial Switch + RDC1 HPA/B Remove for current -feed SLIC devices. CDC CHP + 1/20 – RDC2 RDC + ANTISAT – –2.5 V 2 Zarlink Semiconductor Inc. SLIC Devices Figure 2. Application Note SLIC Dial Pulse Waveforms Switch Closed Switch Open VRD 1.25 V Reference –5 V DET Tdopen Tdclosed Time Equations 1a, 1b, and 2 describe the primary effects of RD, CD, and IL on dial switch delay times and can be used to compute the values of Td open and Td closed shown in Figure 2. I L R D 1900 ; I L < ------------(1a) Td open = R D C D = ln ------------- 365 RD 1900 RD (1b) Td open = 1.65 RD C D ; I ≥ ------------- 365 (2) Td closed = RD CD ln 1 – -------------I L R D Because the voltage swing of VRD is limited to approximately 6.5 V above VEE, Equations 1a and 1b describe Td open. Equation 1a is valid below 6.5 V and Equation 1b is valid at 6.5 V. Of course, these equations are valid only when IL is greater than the loop detection threshold current determined by resistor RD. 365 I L > ---------RD SECONDARY FACTORS Equations 1a, 1b, and 2 only describe the primary causes of the dial pulse delay due to RD, CD, and loop current. However, components CHP, RDC1, RDC2, CDC, and the SLIC device chip itself can create second order effects. These effects, under some line conditions, can be significant. One factor is the shorting circuit in the SLIC device that activates when the voltage between the A and B pins suddenly changes because of a switch hook or a dial switch operation. This circuit helps the SLIC to quickly adapt to new levels of line current and line voltage. The currents flowing through this circuit can influence the dial pulse delay particularly at lower loop current detection threshold settings. Immediately after a dial switch opening, current from the output amplifiers has no other course but to flow through the RSENSE and shorting circuit while charging capacitor CHP. This charge delays the detection of a dial switch opening. After a switch closure, CHP rapidly dumps its small charge through the trigger circuit into the load (not through RSENSE). Therefore, CHP does not introduce delay in the detection of a dial switch closure. Delay in this case results from the charging time of CDC. 3 Zarlink Semiconductor Inc. SLIC Devices Application Note Figure 3 illustrates these effects by showing the response of VRD with and without capacitor CD connected. The VRD waveform produced with CD disconnected is an unfiltered representation of the actual current being delivered by the SLIC power amplifiers. In Figure 3, the dial switch goes from closed to open at t=0. Inspection of the CD=0 curve shows that the CHP charging current begins at t=0 and lasts for approximately 1.2 ms. VRD will take longer to decay to the 1.25-V threshold level when CD is connected. This causes Td open to increase slightly. When the loop goes from switch open to switch closed, the output amplifiers try to deliver the programmed current. The amplifiers cannot do this immediately because of the charging of CDC with a time constant τdc determined by RDC1, RDC2, and CDC. The loop current rises with the same time constant to its final value. In this case, when CD is connected, Td closed will depend mainly on the delay caused by RD and CD, and on the delay caused by τdc. Figure 3. Typical Response at SLIC RD Pin (RD = 51.1 kΩ) 10 Switch closed CD=0.01 µF VRD (V) CD=0 1.25-V Reference Switch open 0 1 2 3 4 50 t (ms) 4 Zarlink Semiconductor Inc. 51 52 53 54 SLIC Devices Application Note The graphs of Figure 4a through Figure 4h show the typical dependence of dial pulse delays, Td closed and Td open, on loop current. Curves for two sets of RD and CD values are included for resistance feed and for current feed devices. The curves shown are valid only for Le7957X/Le79M57X resistance feed SLIC devices and for Le7942, Le79555, and Le7953X/Le79M53X current feed SLIC devices intended for –48 V battery operation. These curves can be used to estimate dial pulse distortion for most circuit configurations and line conditions. (These curves may also apply to other Zarlnk SLIC devices with similar gains and scaling constants. Consult individual data sheets for these parameters.) As a reference, the ideal delay caused by RD and CD (described by Equation 2) is shown on each graph. For example, assume the following conditions: Loop current, IL = 40 mA RDC1 = RDC2 = 20 kΩ CDC = 0.15 µF CHP = 0.33 µF RD = 51.1 kΩ CD = 0.01 µF R DC1 R DC2 –6 τ dc = ----------------------------------- C DC = 1000 • 0.15 • 10 R DC1 + R DC2 –6 = 1.5 • 10 = 1.5 ms Td closed (from Figure 4a) = 0.75 ms Td open (from Figure 4b) = 1.35 ms Dial pulse distortion = Td open – Td closed = 1.35 ms – 0.75 ms = 0.6 ms 5 Zarlink Semiconductor Inc. SLIC Devices Figure 4. Application Note Typical Dependence of Td closed and Td open on Loop Current 1 τdc =1.5 ms τdc =1.0 ms τdc =0.068 ms Td closed 0.5 (ms) 0 15 35 55 Loop Current, IL (mA) Plot of Equation 2 RD =51.1 kΩ CD = 0.01 µF Figure 4a. Td closed versus IL for Various τdc (Resistance Feed Devices) 2 0.47 µF 0.33 µF 0.22 µF CHP Td open 1 (ms) 0 15 35 55 Loop Current, IL (mA) Plot of Equations 1a and 1b RD =51.1 kΩ CD =0.01 µF Figure 4b. Td open versus IL for Various CHP (Resistance Feed Devices 6 Zarlink Semiconductor Inc. SLIC Devices Application Note 2 Td closed 1 (ms) τdc =1.5 ms τdc =1.0 ms τdc =0.068 ms 0 15 35 55 Loop Current, IL (mA) Plot of Equation 2 RD =36.5 kΩ CD =0.015 µF Figure 4c. Td closed versus IL for Various τdc (Resistance Feed Devices) 2 Td open 1 (ms) 0 15 35 55 Loop Current, Il (mA) Plot of Equations 1a and 1b RD =36.5 kΩ CD =0.015 µF Figure 4d. Td open Versus IL (Resistance Feed Devices) 7 Zarlink Semiconductor Inc. SLIC Devices Application Note 1 τdc =1.5 ms τdc =1.0 ms τdc =0.068 ms Td closed 0.5 (ms) 0 3 5 55 Loop Current, IL (mA) Plot of Equation 2 RD =51.1 kΩ CD =0.01 µF Figure 4e. Td closed versus IL for Various τdc (Current Feed Devices) 2 0.47 µF 0.33 µF 0.22 µF CHP Td open 1 (ms) 0 35 55 Loop Current, IL (mA) Plot of Equations 1a and 1b RD =51.1 kΩ CD =0.01 µF Figure 4f. Td open versus IL for Various CHP (Current Feed Devices) 8 Zarlink Semiconductor Inc. SLIC Devices Application Note 2 Td closed (ms) 1 τdc =1.5 ms τdc =1.0 ms τdc =0.068 ms 0 35 55 Loop Current, IL (mA) Plot of Equation 2 RD =36.5 kΩ CD =0.015 µF Figure 4g. Td closed versus IL for Various τdc (Current Feed Devices) 2 Td open (ms) 1 0 35 55 Loop Current, IL (mA) Plot of Equations 1a and 1b RD =36.5 kΩ CD =0.015 µF Figure 4h. Td open Versus IL (Current Feed Devices) 9 Zarlink Semiconductor Inc. SLIC Devices Application Note COMPONENT RECOMMENDATIONS For optimum linecard performance, it is recommended that the following guidelines be considered when selecting values for RD, CD, τdc, and CHP. Component Value Range Comments RD Less than or equal to 51 kΩ Values greater than 51 kΩ may lead to unacceptable switch hook detection delays. CD 0.01 µF Ensures high frequency noise rejection. (Other values can be used, depending on system requirements.) Higher values may lead to: 1. τdc (see Note 1) 0.05 to 1.5 ms Low DC loop stability margins, particularly with complex AC impedance synthesis networks 2. Increased Td closed. Lower values may increase the idle channel noise in the antisaturation region. Higher values lead to increased Td open. CHP 0.22 to 0.47 µF Lower values lead to an increase of longitudinal voltage generation and possible reduction of DC feed control loop stability margins. Note: 1. τ dc To ensure adequate DC control loop stability margins: C HP ≥ ------------5000 10 Zarlink Semiconductor Inc. ™ For more information about all Zarlink products visit our Web Site at: www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. 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