CCD Delay Line Series MN38663S NTSC-Compatible CCD Video Signal Delay Element Overview The MN38663S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 680.5 and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38663S samples the input using the supplied clock signal with a frequency of three times the NTSC color signal subcarrier frequency (3.579545 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. When the switch input is "H" level, the MN38663S disables the threefold-frequency circuit and samples the input with the image sensor drive frequency (9.545454 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Features Pin Assignment XIC 1 20 XIV VSS3 2 19 PCOUT & VCOIN VDD3 3 18 –VBB VINC1 4 17 VSS2 N.C. 5 16 VDD2 VINVC 6 15 VINVY VGC1 7 14 SW VO1C 8 13 VINC2 VDD1 9 12 VGC2 VSS1 10 11 VO2Y ( TOP VIEW ) SOP020-P-0300 Single 4.4 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38663S for signal processing Applications Video cameras 1 MN38663S CCD Delay Line Series VINVC L VINC1 H Charge input block L L analog shift register H analog shift register Booster circuit Voltage generator Voltage generator 602-stage analog shift register 3-stage VGC2 7 Mode switch 78.5-stage 12 VGC1 SW VSS3 2 14 VDD3 Charge input block H 4 3 Clamp circuit Bias circuit 6 17 V SS2 16 V DD2 9 10 VSS1 VDD1 Block Diagram Charge detector Resampling output amplifier 8 VO1C L H VINVY L 15 Charge input block H VINC2 H 13 Charge input block L XIV 20 L 78.5-stage analog shift register H 602-stage analog shift register 3-stage analog shift register Charge detector Resampling output amplifier L L H øS driver H H 1/3rd frequency divider ø1 driver øR driver øSH driver VCO H Phase comparator Timing adjustment VSS 19 ø2 driver Substrate bias generator L H PCOUT & VCOIN 2 Waveform adjustment block –VBB L L 18 XIC 1 Waveform amplifier adjustment block 11 VO2Y CCD Delay Line Series MN38663S Pin Descriptions Pin No. 1 Symbol XIC Pin Name 9.545454 MHz clock input Function Description 2 VSS3 GND (3) Ground for clock multiplier circuit 3 VDD3 Power supply (3) Power supply for clock 4 VINC1 multiplier circuit 5 N.C. 6 VINVC Camera signal input (1) No connection Video signal input (C) 7 VGC1 Output gate connection (1) 8 VO1C Signal output (1C) 9 VDD1 Power supply (1) 10 VSS1 GND (1) Ground for analog circuits 11 VO2Y Signal output (2Y) Output pin for signal fed 12 VGC2 Output gate connection (2) 13 VINC2 Power supply (2) 14 SW 15 VINVY 16 VDD2 Power supply (2) 17 VSS2 GND (2) Ground for digital circuits other 18 –VBB Substrate connection Negative voltage pin 19 PCOUT&VCOIN Output pin for signal fed to pin 4 or pin 6 Power supply for analog circuits to pin 13 or pin 15 Camera/video mode switch Video signal input (Y) Power supply for digital circuits other than frequency multiplier than frequency multiplier Phase comparator output and voltage controlled oscillator input 20 XIV 3.579545 MHz clock input Notes 1: Always connect VDD1, VDD2, and VDD3 to the same voltage. 2: Always connect VSS1, VSS2, and VSS3 to ground. 3 MN38663S CCD Delay Line Series Electrical Characteristics VDD=4.4V, Vckv=0.3VP-P (sine wave), fckv=3.579545MHz (Converted to 10.738635 MHz internally) Vckc=0.3VP-P (sine wave), fckc=9.545454MHz, Vin=0.5VP-P (sine wave), Ta=25˚C Parameter Power supply current (Video signal I/O) Power supply current (Camera signal I/O) Signal bandwidth (Video signal I/O) Signal bandwidth (Camera signal I/O) Insertion gain Symbol IDDV IDDC BWV BWC Conditions Average current for 4.4-V power supply when SW is "L" level supply when SW is "H" level –3 dB for 200 kHz value when SW is "L" level –3 dB for 200 kHz value when SW is "H" level fsig=200kHz Total harmonic distortion THD fsig=200kHz Signal-to-noise ratio S/N Signal output (VP-P)/noise output (rms) NCV1 Clock leak (C) NCC Clock leak (V2) NCV2 typ max 30 48 28 46 3.0 4.2 2.7 3.7 1 4 7 1 4 50 56 MHz 3.579545-MHz component output/main output signal when SW is "L" level 9.545454-MHz component output/main output signal when SW is "H" level 10.738635-MHz component output/main % dB –40 dB –15 –10 dB –15 –10 dB –37 dB output signal when switch signal is "L" level CT fsig=200kHz Delay (Video signal I/O) τDV When SW is "L" level 63.40 Delay (Camera signal I/O) τDC When SW is "H" level 63.42 VO pin output impedance ZO VBINC dB –50 Crosstalk Input bias voltage Unit mA Average current for 4.4-V power IG Clock leak (V1) min Applicable to signal input pins VINC1 and VINC2 2.20 µs 350 700 Ω 2.50 2.80 V Input bias voltage VBINY Applicable to signal input pin VINC1 2.10 2.40 2.70 V Input clamp voltage VCLIN Applicable to signal input pin VINVY 1.90 2.20 2.50 V Output bias voltage VBOC 1.30 2.30 3.30 V Output bias voltage VBOY 1.35 2.35 3.35 V Output clamp voltage VCLO 1.05 2.05 3.05 V Substrate voltage –VBB 4 Applicable to signal output pins VO1C and VO2Y when SW is "H" level Applicable to signal output pin VO1C when SW is "L" level Applicable to signal output pin VO2Y when SW is "L" level –2.5 V CCD Delay Line Series MN38663S Application Circuit Example + 4.4V – 10m L Charge input block H H Mode switch 78.5-stage L analog shift register H L Booster circuit 0.01µF VGC1 12 VGC2 Voltage generator Voltage generator 602-stage analog shift register 3-stage analog shift register Charge input block 0.01µF 7 2 14 SW VSS3 VDD3 3 9 0.1µF Clamp circuit Bias circuit Signal input VINVC 6 – + 0.47µF Signal input VINC1 4 – + 0.47µF 17 VSS2 16 VDD2 0.1µF 10 VSS1 VDD1 0.1µF 4.4V or GND Charge detector Resampling output amplifier L 8 VO1C Signal output (1C) H Signal input VINVY 15 – + 0.47µF Signal input VINC2 13 – + 0.47µF Clock input XIV 20 XIC 1000pF Charge input block H H 78.5-stage analog shift register Charge input block L H 602-stage analog shift register 3-stage analog shift register Charge detector Resampling output amplifier L L H 11 VO2Y Signal output (2Y) øS driver H 1000pF Clock input L L H 1 1/3rd frequency divider Waveform amplifier adjustment block L L Waveform adjustment block ø1 driver øR driver øSH driver VCO H Phase comparator Timing adjustment ø2 driver 0.01µF Substrate bias generator –VBB 18 PCOUT & VCOIN 19 L H 0.01µF 1000pF 820Ω Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18. 5 MN38663S CCD Delay Line Series Package Dimensions (Unit:mm) SOP020–P–0300 12.60±0.20 20 11 +0.10 0.15 -0.05 7.70±0.30 5.50±0.20 1.10±0.20 0 to 10° 0.30min. 1.27 0.40±0.10 SEATING PLANE 6 0.10±0.10 (0.6) 1.90max. 10 1.50±0.20 1