SLIC Devices Applications of the SLIC Devices Introduction to the SLIC Product Family Application Note SLIC FAMILY FUNCTIONAL DESCRIPTION Zarlink’s SLIC device family has grown and includes device operating characteristics and options not previously available. Current offerings also include new choices of power management and DC feed control to address needs of major telephony markets. Although certain features may be unique to a specific SLIC device type, all Zarlink SLICs are based on and contain the same functional blocks. The following sections describe, in detail, the operation of each of these blocks. Two-Wire Interface The function of the two-wire interface is to provide DC current and to send voice signals to a telephone apparatus connected to the linecard with a two-wire line. The two-wire interface also receives the returning voice signals from the telephone transmitter. The typical two-wire interface (see Figure 1) consists of two current mode line-driver amplifiers, line-voltage sensing circuits with AC/DC pass separation, and a loop-current sensing circuit. The current mode amplifiers driving the A(TIP) and B(RING) pins are controlled by two input signals, ILI and IMI. ILI controls the longitudinal (common mode) current, and IMI controls the metallic (differential) current. The two-wire currents are: I AX = K 1 ( I LI + I MI ) and I BX = K 1 ( I LI – I MI ) Where: K1 is the internal current mode amplifier gain. IMI is equal to the current into the Receive Summing Node (RSN), which is the terminating point for the external networks controlling two-wire impedance, receive gain, battery feed, and metering gain (in metering versions). These networks are described in detail later. ILI controls the longitudinal line current to obtain the optimum common mode DC operating point for the current mode amplifiers. The voltage sense signal (VACMET) that goes to the signal transmission block is the AC metallic component of the A and B voltages. Two voltage sense signals (|VDCMET| and VLONG) go to the power feed controller block. VDCMET is the DC metallic component of the A and B voltages. VLONG is the longitudinal component of the A and B voltages. An external capacitor (CHP), connected between HPA and HPB, separates the AC and DC components of the metallic voltage. Because the time constant could be too long during polarity reversal or pulse dialing, the two-wire interface can have a shorting circuit that decreases the time constant during these events. The loop-current sensing circuit produces a current (ID) that is proportional to the magnitude of the loop current and is output to the RD pin. An external resistor and filter capacitor connected to RD converts this current to a filtered voltage for use by the off-hook detector. Note: This describes the two-wire interface for most of Zarlink’s SLIC devices. Minor differences may exist on certain device types, but all follow this general format and operation. Signal Transmission Figure 2 provides more detail of the SLIC transmission path. This path is split between the signal transmission block and the two-wire interface block. The AC line voltage is sensed by differential amplifiers between the A and HPA leads, and between the HPB and B leads. The outputs of these amplifiers are equal to the AC metallic components of the line voltages. These voltages are summed and buffered by the op amp GTX. GTX in dB is specified in each data sheet under two- to four-wire gain accuracy. For metering applications, GTX is typically –6.02 dB to avoid overload during metering signal transmission. Longitudinal voltages are rejected by the differential amplifiers and only affect VTX to the extent of the longitudinal balance specification. The balance return signal on VTX exhibits 180° phase shift with respect to VRX. This allows the two-wire AC input impedance to be programmed by means of an external impedance that is connected between RSN and VTX (see Figure 2). This impedance may be a complex R-C network and should be K 1 times the desired two-wire input impedance minus K1 times the fuse resistors. This means resistors become K1 times larger and capacitors become K1 times smaller. Note that any external stray capacitance between VTX and RSN must be included in ZT when precise computations for output impedance, gain, transhybrid loss, or return loss are being made. Z T = K 1 • G TX ( Z 2WIN – 2R F ) Where: Z2WIN = desired two-wire impedance Document ID# Rev: Distribution: 080284 Date: Oct 10, 2007 B Version: 2 Public Document SLIC Devices TIP RF A(TIP) Σ + K1 VREG RHP Shorting Circuit 2 HPA IL = ILI • K1 + IMI + – RS/2 Protection IM = IMI • K1 A Current Amplifier VREG Current Sensing IL + IM VREG Application Note ILI Absolute Value |ISENSE A| + GTX VACMET – + RLOOP – Absolute Value 1 VDCMET CHP + VLONG 1/2 HPB ILOOP = IM – + + RHP Shorting Circuit 2 Protection RING Current Sensing RF – B Current Amplifier IL − IM RS/2 Σ + – BGND ID + GTX K1 B(RING) I LOOP -----------------292 VREG – IMI + Absolute Value ILI |ISENSE B| Figure 1. Two-Wire Interface (Typical) The four-wire output is found on the VTX terminal, and the four-wire input terminal is VRX (see Figure 2b). Both of these ports are referenced to analog ground (AGND). V TX - [ V RX G 24 = --------VA Because the fuse resistors are outside the feedback loops, they influence the effective gains. These gains are as follows: G 42L Z -----TK1 = 0 ] = --------------------------------ZT 2R F + ----------------K 1 G TX V TX ( Z L + 2R F ) ZT - [ E G = 0 ] = – --------- ---------------------------------------------G 44L = --------V RX Z RX ZT Z L + 2R F + ---------------K 1 G TX VA ZL K1 ZT - [ E G = 0 ] = – --------- • --------------------------------------------------------= --------V RX Z RX Z T + K 1 G TX ( Z L + 2R F ) 2 Zarlink Semiconductor Inc. SLIC Devices RF Application Note IL+IM A TIP + RHP GTX 2 HPA IL/K1 25K (typ) – Tel Line VLBIAS 1 ZL VTR – + + CHP 1/2 + + EG VTX – + HPB RHP GTX 2 ZT – IM /K1 IL − IM RF RSN RING ZRX VRX ZM VMG B a. Detailed Model RF TIP VA ZT -------------------2K 1 G TX ZT − ----------------------2Z RX G TX 25 ZL VTR VM + Tel Line GTX – + EG VM – 25 RF RING VTX VB ZT -------------------2K 1 G TX ZT + ----------------------2Z RX G TX V A – V B V = ------------------- M 2 b. Simplified Model (AC Only for Conceptual Purposes) Figure 2. SLIC Transmission Model 3 Zarlink Semiconductor Inc. VRX SLIC Devices The dynamic performances of K1 (the current amplifier gain) and GTX (the transmit voltage amplifier gain) are modeled by the following S-domain transfer functions: by RHP and CHP attenuates frequencies above 1.2 Hz. The loop current is equal to K1 times the current into the Receive Summing Node (RSN), which is equal to the voltage on RDC divided by RDC1 + RDC2. The values of the programming resistors, R DC1 and R DC2 , should be kept somewhat equal in order to minimize the size of CDC. 1 K 1 ( S ) = K 1 --------------------------------------------------------------------------------------–8 1 + 1.15 • 10 • [ R S + Z AB ( S ) ] • S In constant current feed versions, the battery feed circuit produces a voltage at the RDC pin whose magnitude is equal to 2.5 V, and whose sign depends on the feed polarity desired (negative for normal polarity and positive for reverse polarity). The net result is a constant current feed with the feed current given by the following equation: G TX 1 G TX ( S ) = -----------------------------------• -----------------------------------–7 1 1 + --------------------------- 1 + 4.5 • 10 S R HP C HP S Where: K1 ZAB GTX RHP RS Application Note = Current amplifier DC gain = Load between the A and B pins = Two- to four-wire transmit path midband gain = Internal resistance, typically 424K = Current sensing resistance 2.5K 1 I FEED = ------------------------------R DC1 + R DC2 For example, if K1 is 1000 and a loop current of 40 mA is desired: These functions are useful for the prediction of system return loss and echo cancellation performance. The value of K1 can be found in each device’s data sheet referred to as the current gain. GTX in dB is specified in each data sheet under two- to four-wire gain accuracy. CHP sets the low frequency limit of the voice band response. 2.5 • 1000- = 62.5K R DC1 + R DC2 = -----------------------40 In this example, values of RDC1 and RDC2 of 31.25K could be used. For resistance feed versions, the battery feed produces a voltage at the RDC pin whose magnitude is equal to (50 – |VDCMET|)/20, and whose sign depends on the feed polarity desired (negative for normal polarity and positive for reverse polarity). The net result is an apparent open circuit voltage of 50 V and a feed resistance, RFEED, equal to 20(RDC1 + RDC2)/K1; thus, the feed resistance is programmable, but the apparent open circuit voltage is not. Including the fuse resistors RF, the total feed resistance is then: The transmission circuit also contains a longitudinal feedback circuit to shunt longitudinal signals to a DC bias voltage (VLBIAS) which comes from the power feed controller. Longitudinally, the SLIC devices typically appear as 25 Ω resistors from A and B to VLBIAS. The longitudinal feedback does not affect metallic signals. In metering versions, metering signals are injected by adding an additional current into summing point RSN through an external impedance, ZM. 20 ( R DC1 + R DC2 ) R FEED = 2R F + -----------------------------------------K1 Power Feed Controller The power feed controller has three sections: (1) the battery feed circuit; (2) the polarity reversal circuit; and (3) the bias circuit. These are shown in Figure 3. For example, if K1 = 1000, and a feed resistance of 840 Ω is desired using 20 Ω fuse resistors: 1000 ( 840 – 2 • 20 ) R DC1 + R DC2 = ------------------------------------------------ = 40K 20 In this example, values of RDC1 and RDC2 of 20K could be used. The battery feed circuit regulates the amount of DC current and voltage supplied to the telephone over a wide range of loop resistance. The polarity reversal circuit provides the capability to reverse the loop current for pay telephone keypad disable and other applications. The bias circuit provides a reference voltage, which is offset from the subscriber line voltage. The reference voltage can control the switched mode regulator (switching regulator versions only, described later), which minimizes SLIC power consumption by providing the minimum supply voltage needed by the line drivers for proper operation. The reference voltage also can control the switching point for automatic battery switching SLIC devices. All SLIC devices have an anti-saturation guard that prevents the output amplifiers from saturating under long loop high resistance conditions, which maintains AC transmission by preventing clipping. Some of the SLIC devices implement multiple anti-saturation regions that may track the battery voltage or may operate at pre-determined fixed thresholds. Battery-independent anti-saturation noise performance is normally identical to that of normal loop feed, however, on some devices, anti-saturation that tracks the battery voltage may provide an additional path for battery-referenced noise entering the transmission path. VDCMET is the DC component of the voltage between A and B. When CHP is 0.33 µF, the low-pass filter formed 4 Zarlink Semiconductor Inc. SLIC Devices Application Note put amplifiers, until (for most devices) it is equal to twice VLBIAS. As an example, most switching regulator SLICs have two anti-saturation regions. In these SLICs, when the VAX to V BX voltage reaches a threshold of approximately 30 V (exact voltage depends on SLIC version), the Anti-sat 1 region of operation is entered. In this region, the feed synthesis loop gain is greatly increased, thereby reducing the output resistance to a much lower value. The output voltage then rises at a slower rate with increasing loop resistance, thereby keeping the amplifier out of saturation. All transmission specifications are met in the Anti-sat 1 region. Power Management The operation of the power-feed controller in most Zarlink SLIC devices results in the A pin maintaining a fairly constant voltage below Battery Ground, while the voltage on the B pin varies depending on the DC resistance of the loop. This means that as the loop length decreases, the voltage dropped across the B current amplifier and the corresponding power dissipation increases. Zarlink has implemented a number of techniques to take advantage of this characteristic to minimize the on-chip and in some cases, total system power dissipation. If the line voltage increases further to greater than approximately 5 to 15 V (exact voltage depends on SLIC version) below VBAT, the SLIC goes into the Anti-sat 2 region where the loop gain is further increased and the output resistance decreased. In this region, the voltage rises very slowly, with increasing loop resistance, and the DC feed of the SLIC looks almost like a constant voltage source. The transmission specifications in the Anti-sat 2 region may be somewhat degraded. Switching Regulator The first technique is to implement a switching regulator function on-chip with a few external components (see Figure 4). The power-feed controller generates a reference voltage VREF, which is the minimum voltage required to feed the output line amplifiers and is equal to twice VLBIAS. The switching regulator adjusts VREG, the operating voltage for the output amplifiers, to equal VREF. The efficiency of the switching regulator (>80%) minimizes both the on-chip power dissipation and the system power dissipation. This is particularly important for short loops operating at high currents, which otherwise cause high power dissipation. Some of the SLIC devices implement a battery-dependent anti-sat scheme, where a pin (CAS pin) on the SLIC is provided to filter noise that may originate from the battery source. The size of the CCAS capacitor connected to the CAS pin affects the amount of filtering, and therefore affects VBAT PSRR performance. Load lines and equations describing all regions of operation are provided in each device data sheet. To obtain polarity reversal, the input decoder and control circuit send a signal that reverses the sign of the voltage on the RDC pin. During reversal, sense resistors R HP are shunted to reduce the time constant formed by RHP and CHP. This allows the polarity reversal time to be controlled only by CDC and its parallel combination of RDC1 and RDC2. A typical polarity transition time is 1.5 ms. In the previous example for a resistance feed version SLIC, R D C 1 and R D C 2 were computed to be 20K. The value of CDC should then be 0.15 µF. A 250 to 300 kHz clock is required at input CHCLK to operate the switching regulator. The switch control tells the switch to disconnect the L pin from VBAT at the beginning of each CHCLK cycle, and connect it for a time that depends upon the difference between VREF and VREG. During this time, the current through the inductor decreases. A comparator senses when V REG falls below VREF and the inductor is again switched to VBAT. The result is that the average value of VREG is always held equal to the value of VREF. The filter capacitor, CFIL, between VREG and BGND smooths out the ripple caused by the inductor switching action. The longitudinal control loop operates by deriving an internal reference voltage VLBIAS. This voltage is given by: The regulator is a high-gain feedback circuit, and therefore requires the stabilization network formed by RCH, CCH1, and CCH2 between VREG and CHS. – ( VDCMET + BIAS ) V LBIAS = ----------------------------------------------------------2 The design and layout of the external switching regulator circuitry is very important. Fast switching currents can occur in the catch diode, D1, and in the VBAT filter capacitor, CBAT. These must be low inductance components with short leads. Capacitor CFIL must have low effective series resistance at high frequencies. A stable, voltage-insensitive capacitor, such as a metallized polyester type, should be used. The additional BIAS is added to provide enough “headroom” for the amplifiers to always operate in the linear region. The value of BIAS varies depending on the SLIC type. Any longitudinal voltages appearing on the line are shunted to VLBIAS via a 25 Ω resistance. Normal transmission performance is maintained provided the resulting current is less than the specified longitudinal current capability. The VREF output is fed to the switching regulator (switching regulator SLICs only), which adjusts VREG, the voltage supplying the line out- The connections from the diode to the L pin, from CBAT to the VBAT pin, and from the diode to CBAT must all be short, low-inductance connections. The L pin is subject to very fast voltage transients as the switch turns on 5 Zarlink Semiconductor Inc. SLIC Devices Application Note the switching-regulator SLIC devices in a system should be synchronized to a common clock to prevent intermodulation products and crosstalk in the voice band. For systems that include coding, the clock should be synchronous to the sampling frequency. and off, so all of the connections to this pin must be isolated from sensitive signals by means of traces connected to BGND. All of the external components in the regulator circuit must have voltage ratings in excess of the maximum battery voltage. In addition, the diode must have a reverse recovery time of less than 4 ns. All IMI = IM/K1 RSN K1 RF IL + IM A TIP RHP VREG VBAT BGND 2 RL HPA CHP HPB RF RDC1 1/20 – RHP I − I L M 2 RING RDC Absolute Value 1 CDC –2.5 V + Tel Line RDC2 Anti-saturation Guard VREG Note + VREF –1 BGND B +1 = Normal –1 = Reverse – BIAS 1/2 VLBIAS Note: The 1/20 operational amplifier is only present in constant resistance feed versions of the SLIC. a. Detailed Model RF A BIAS/2 25 Normal Current Feed Option TIP Tel Line Resistance Feed Option 50 V + See Feed Options at Right RL RF – 25 B RING VAX – VBX Reverse Longitudinal b. Simplified Model Figure 3. SLIC Power Feed Controller 6 Zarlink Semiconductor Inc. 2.5K 1 ------------------------------R DC1 + R DC2 R DC1 + R DC2 -------------------------------K1 20 SLIC Devices BGND Application Note VREG QBAT VREF (Power Feed Controller) CHCLK Switch Control (250–300 kHz) BGND VREG DI VBAT L CHS CQ CBAT CFIL QBAT CCH2 L D6 RCH VBAT CCH1 Figure 4. SLIC Switching Regulator Thermal Management This power management technique offloads thermal energy from the SLIC to an external resistor, RTMG. The circuit configuration is shown in Figure 5. An external resistor is used to share some of the loop current with the B-leg current amplifier, especially on short lines. This limits the on-chip power dissipation and allows a low cost plastic package to be used while reducing external component count compared to the switching regulator solution. The RTMG resistor is normally selected so that with the programmed loop current being fed into a short circuit loop from the nominal battery, all of the loop current is supplied by RTMG. Equations to calcu- late this resistance and the resulting power dissipation in the SLIC and RTMG are provided in the individual data sheets. This feature operates in Normal and Reverse Polarity Feeding states for most SLIC devices. However, some SLIC devices only support thermal management in the Normal Polarity state. Refer to the specific data sheets. 7 Zarlink Semiconductor Inc. SLIC Devices Application Note BGND A(TIP) Thermal Management SLIC ILOOP RLOOP B(RING) VBAT TMG RTMG ISLIC ITMG Battery Notes: 1. A(TIP) lead remains at a relatively constant voltage (a few volts below ground) while B(RING) lead becomes more negative as loop resistance increases. 2. External resistor (RTMG) shares loop current (ILOOP) with SLIC. 3. Internal circuit and RTMG resistor choice ensures maximum loop current is fed through RTMG at shortest loop conditions. 4. The TMG connection is inside the SLIC’s current sense loop, so as more current to the loop is provided through TMG, the current from the B lead amplifier is reduced, as is the SLIC’s power dissipation. 5. The diagram shows scheme functionality. Fault control and other function switching are not shown. Figure 5. Simplified SLIC Thermal Management Battery Switching The third power management technique is battery switching operation. This technique allows both the device and system power dissipation to be minimized. E0 and E1 control the function of the DET output. 1 summarizes the available SLIC operating states for most devices. This solution provides for high on-hook voltage across the line, for on-hook recognition or to ensure operation with MTU’s, while allowing low off-hook power dissipation by switching to a lower battery voltage. Up to three detectors are implemented on-chip to support the necessary signaling functions. The status of these detectors is reported through a single output, DET. Three control signals determine what information is provided at this output. Input Decoder and Control A signal from the state decoder selects between the ring trip comparator and loop detect/ground key (see 1). The E1 input selects between loop and ground key. Finally, the active high E0 input (when the SLIC is so equipped) enables the DET output, which is an open collector with an internal pull-up. The individual device data sheets should be used to determine which control lines are available with a given device/package option and to determine the polarity of E1. The input decoder and control block provides a means for a microprocessor or SLAC™ IC to control such system functions as line activate, OHT, ringing, and polarity reversal. The input decoder and control block has TTLcompatible inputs, which set the operating states of the SLIC. C3–C1 inputs are common to most versions and can select up to eight operating states. Other inputs are available for relay drivers as provided by certain SLICs. 8 Zarlink Semiconductor Inc. SLIC Devices Table 1. Application Note SLIC Decoding and State Description (most devices) Amplifier Output * State Two-Wire State A(TIP) DET Output B(RING) E1/E1 See SLIC Data Sheet Ring Relay Active 0 Open Circuit High-Z High-Z Ring trip Ring trip No 1 Ringing High-Z High-Z Ring trip Ring trip Yes 2 Active Near BGND Near VBAT Loop detector Ground key No 3 OHT (On-Hook TX) Near BGND Near VBAT Loop detector Ground key No 4 Tip Open High-Z Near VBAT Loop detector — No 5 Standby Near BGND Near VBAT Loop detector — No 6 Active Polarity Reversal Near VBAT Near BGND Loop detector Ground key No 7 OHT Polarity Reversal Near VBAT Near BGND Loop detector Ground key No Notes: Open Circuit: When the SLIC is in the Open Circuit state, both the A(TIP) and B(RING) power amplifiers are switched off and present high impedance to the line. The Open Circuit state has the lowest power dissipation. Loop detectors are inoperative in this state. This function is useful for allowing line-powered relays to collapse, denying power to out-of-service lines, as well as allowing clearing of line faults. Ringing: When the SLIC is in the Ringing state, the ring relay driver (RINGOUT) is activated, and the ring-trip detector is readable at DET. Also, the A(TIP) and B(RING) are both open circuits. While the SLIC is in the Ringing state, signal transmission is inhibited. Active: In states where normal, Active operation is indicated, the standard battery convention applies; A(TIP) is near ground and sources current. B(RING) is near VBAT and sinks current. During Active state operation, all signal transmission and loop supervision functions operate, and the off-hook detector or ground-key detector is gated to DET. OHT: The OHT (On-Hook Transmission) operating state is the SLIC’s low-power mode in which the battery feed circuit limits the DC loop current to typically 0.5 (value depends on SLIC version) times the Active state short circuit current limit. In this state, the off-hook detector works normally, and all signal transmission functions operate normally. Previously, this OHT state was designated the Disable state in earlier Zarlink SLIC documentation. Tip Open: When the SLIC is in the Tip Open state, the A(TIP) power amplifier is switched off so that it presents a high impedance to the line. This mode is provided to facilitate ground-start signaling. Standby: The Standby state (on SLICs so equipped; see specific data sheets) is used for supervision purposes only. The A and B amplifiers are completely turned off (similar to the Open Circuit state) and DC feed through the loop is provided by an internal resistive feed network. Loop detect functions operate normally, but signal transmission is not enabled. This allows for monitoring off-hook transitions while maintaining lowest possible power consumption. Active Polarity Reversal: When the SLIC is in Active Polarity Reversal state, the normal battery feed convention is reversed, with B(RING) approaching ground and sourcing current, while A(TIP) approaches battery and sinks current. While A(TIP) and B(RING) are in transition, the off-hook function is meaningless because the loop current must pass through zero. OHT Polarity Reversal: This state is similar to the OHT state, except that the DC feed polarity is reversed. * With no DC loading, on-hook condition 9 Zarlink Semiconductor Inc. SLIC Devices Off-Hook Detector Application Note The value of RD required for a desired off-hook line current threshold is then (see SLIC data sheet for proper numerator value): The first and most important loop monitoring function, provided on all SLIC devices, is off-hook detection. The block diagram of this detector is shown in Figure 6. KS • VT R D = ------------------I THRESH The two-wire interface produces a current equal in magnitude to the loop current divided by KS, and sends it out on the RD pin. An external resistor and capacitor (RD and CD) connects the RD pin to the detector reference. The value of the voltage across resistor RD is the current leaving the RD pin times the value of RD. The off-hook detector outputs a logic Low when this voltage rises above a threshold voltage of typically 1.25 V. where KS = 292 and VT = 1.25 V The value of Cd for a typical on-hook to off-hook time constant of 0.5 ms should satisfy the following relation: R D C D = 0.5 ms Input Decoder and Control C1 Input Decoder C2 C3 Comparator + VCC SHD DET – GKD MUX E0 RTD + ILOOP A(TIP) ILOOP B(RING) E1 VT – Detector Reference (VEE or GND)* I LOOP -------------KS RD Two-Wire Interface CD RD * See SLIC data sheet Figure 6. Signaling Off-Hook Detection 10 Zarlink Semiconductor Inc. SLIC Devices Ground-Key Detector The Ground-Key Detector (see Figure 7) compares the Application Note On some SLIC versions, a ground key filter pin is provided. This allows attenuation of AC longitudinal currents and produces a more reliable detect output. The minimum GKFIL capacitor is 3.3 nF. It forms a low-pass transfer function with an on-chip 36 kΩ resistor. Larger capacitance values can be used to achieve the desired AC rejection. longitudinal control current (ILI) to an internally generated threshold current, ILT. The current flowing in the earth loop is proportional to the longitudinal control current. When the current in the earth loop exceeds the threshold value, the ground-key signal forces the DET output Low when selected by E1. Input Decoder and Control –ILT 36 kΩ C1 Input Decoder C2 C3 VCC SHD DET ILI GKD MUX E0 E1 RTD GKFIL Figure 7. Ground-Key Detector 11 Zarlink Semiconductor Inc. SLIC Devices Ringing Circuit Application Note The capacitors reduce the effective amplitude of the ringing signal by a factor of 1/ 1+j2πfr t. A generalized ringing circuit is shown in Figure 8. In common applications, the circuit can be simplified as shown later. During ringing, the ring relay driver is activated and the A(TIP) and B(RING) leads are placed in the Open Circuit state. The ring feed source is connected by the ring relay to the line through ring feed resistors R1 and R2. R 3 R B1 C RT1 R 4 R B2 C RT2 Where: t = ---------------------------+ ---------------------------R 3 + R B1 R 4 + R B2 For fr = 20 Hz ringing, CRT should be chosen to give a value of t = 50 ms. This reduces the ringing by a factor of 6.4 and allow detection within two ringing cycles. For balanced ringing, the ringing voltage splits between the ground and battery sides. The resistors should be balanced, (i.e., R1 = R2, RB1 = RB2, and R3 = R4). A single capacitor of half the value between DA and DB can replace the capacitors CRT1 and CRT2. When an off-hook condition occurs, the bridging resistors RB1, RB2, R3, and R4, and filter capacitors CRT1 and CRT2 cause the voltage on DB to go positive with respect to DA and the detector (DET) output goes Low. If RLMAX is the maximum line resistance that is to be detected as an off-hook, the bridging resistors should be chosen such that: For unbalanced ringing on the ground side, use equal networks with R1 = R2, RB1 = RB2, R3 = R4, and CRT1 = CRT2. R B1 R B2 ( R LMAX + R FEED ) --------- = -------- = ------------------------------------------R3 R4 ( R LMAX + R 1 ) For unbalanced ringing on the battery side, the following simplification can be made. The positive side of the ringing supply is grounded and R1 is replaced by a short circuit. In this case, the R4, RB2, and CRT2 network can be combined with other channels into a ringer threshold because the voltage on the DA pin is independent of line conditions. Where: R FEED = R 1 + R 2 Ring Relay KR Input Decoder and Control Ring Relay Driver Input Decoder RB1 Ringing Source + RB2 – R2 R1 R3 C1 C2 C3 Comparator DA CRT2 CRT1 – VCC SHD DET + GKD MUX R4 KR RF TIP Tel Line KR RING E0 DB RTD A RF B Figure 8. Ringing Circuit 12 Zarlink Semiconductor Inc. E1 SLIC Devices Ringing SLICs Application Note In the control path, when the line goes off-hook, the SLIC pulls its collector DET output down and enables the DSLAC device serial control data I/O pins, DIN and DOUT (see Figure 10). The microprocessor also recognizes the off-hook and typically sends a response, such as an Active state or ring relay release command, back to the SLIC, via the DSLAC device DIN pin and the C3–C1 data bus. Zarlnk offers some SLICs, such as the Le79R79, which integrate ringing onto the chip. These devices do not require an external ringing source and do not require a ringing relay to switch the ringing signal on or off. In these devices, the same amplifiers that drive the tip and ring leads are used to generate the ringing voltage right on the SLIC device itself. The C4 line also is addressed in the same manner to enable or disable the test relay driver. The E0 and E1 pins are addressed directly by the microprocessor as shown. Ring Relay Driver A ring relay driver is provided on all versions (except ringing SLIC devices) and is active only in the Ringing state. The relay driver configuration varies between parts. Figure 11 shows a detailed schematic of a basic singleline circuit using one Am79M5XX series SLIC and one half of an Am79C02 DSLAC device. The dashed connection lines in the schematic show the wiring of the various relay, DET enabling, and ground-key options available. The TESTOUT, C4, E0, or E1 pins may or may not be present, depending on the version used. For some devices, the driver is an internal transistor with the collector sourced to BGND and the emitter as the driver output. This allows relays connected to a negative supply, typically VBAT, to be operated. A diode to VBAT is integrated into the design. The Metering Filter block represents an external 12 or 16 kHz low-pass or notch filter to reduce the metering level in the transmit path before it can overload the SLAC IC input. A suggested metering filter circuit, shown in Figure 12, is a notch filter centered at 12 or 16 kHz. This filter has enough attenuation at the metering frequency and does not require an additional cancellation circuit. Other versions have the collector of an internal NPN transistor (emitter grounded) brought out to a separate pin. This allows +5 V relays to be used, and in this case, an integral 7 V Zener between the transistor collector and ground suppresses voltages generated when the relay is released. Some of these devices may not have the internal Zener snubber allowing up to 12 V relays to be used, and may require an external catch diode. Consult individual data sheets for exact configurations. It is a common practice to plug linecards into a powered backplane. To assure reliable operation of the linecard, certain precautions must be taken. Monolithic silicon circuits are built with P and N doped regions on a substrate, and rely upon the proper voltages to be applied to these regions to provide isolation and bias of circuit elements. Typically, the substrate is attached to the most negative voltage, which is VBAT at about –48 V. When voltages are applied in the improper order or with unlimited current, large currents may flow through the substrate to devices and conductors, causing damage. This may cause an instant failure of the part, or degradation over a few seconds or even weeks. To assure that no damage happens to the SLIC, the following recommendations should be followed: Test Relay Driver Additional relay drivers are provided on some SLIC devices. Different configurations are available, depending on the specific SLIC type, allowing for direct operation of test relays, or to connect optional test loads. Application Examples The Zarlink SLIC Family offers a high degree of versatility for analog loop-line circuit applications including Central Office, DLC, FITL, and PBX systems. In this section, typical single-channel and multiple-channel applications are described. ■ Ensure that ground is always connected before any of the other power supply voltages. Zarlink SLICs are not sensitive to the order the other supply voltages are applied, as long as ground is connected first. A common practice is to use longer edge fingers on card edge connectors or longer contacts in plug connectors for connections that must be made first. If this method is not practical, a means to switch –5 V (VEE) and –48 V (VBAT) with the application of +5 V and ground eliminates the concern of negative supplies being applied first. This also prevents negative voltages from being applied to pins C3–C1, which can trigger internal trimming Figure 9 shows a detailed schematic of a basic single-line circuit using one SLIC and one-half of an Am79C02 DSLAC™ device. In the receive path, the DSLAC device processes digital PCM voice data into analog signals and inputs them to the SLIC RSN pin through resistor RRX. In the transmit path, the analog output at the SLIC VTX pin is processed by the DSLAC device and output in serial-digital format to the PCM interface. RRX sets the receive gain and RT is used to synthesize the AC two-wire output impedance. Both RT and RRX can be complex to achieve optimized parameters over the voice band. 13 Zarlink Semiconductor Inc. SLIC Devices Application Note internal current from charging the QBAT capacitor, which could damage the part. On nonswitching regulator SLICs, the current limiting prevents transient voltages and currents from causing potential problems. A 1 Ω resistor in series with the VBAT supply should provide the necessary current limiting. A capacitor in the SLIC side of the resistor forms a time constant, which helps limit the rise time. SCR’s. It is possible that +5 V will be connected before ground, but typically this is not an issue. ■ Provide current limiting to the –5 V (VEE) supply at the pc board level. If –5 V is connected before VBAT, there is a conduction path through the substrate to charge the VBAT capacitor, which can cause internal damage. A 2 Ω resistor in series with the –5 V (VEE) supply and the VEE connections of the SLICs should limit current to a safe level. ■ Ensure that all SLIC grounds (BGND, AGND, and DGND) have a voltage difference between them that is less than the maximum specified on the data sheet. If the grounds are connected together on the PC board, this is not a problem, but if they connect to separate pins on the card edge connector, it is possible for one ground connection to occur before the others, causing maximum limits to be exceeded. Maximum BGND with respect to AGND/ DGND is typically ±100 mV to +1 V/–3 V. ■ Add a Zener diode between the SLIC VEE supply and ground. This prevents the VEE bus from pulling outside safe limits during transient application of power through capacitive conduction paths. This Zener conducts in the positive direction to prevent VEE from going positive, and in the reverse (Zener) direction to keep the voltage from becoming too negative. The diode should be placed on the SLIC side of the 2 Ω resistor recommended above. ■ For further details on this subject, please request a copy of the “Telephone Linecard Powering Considerations with Monolithic SLIC Devices” application note. ■ Provide current limiting to the –48 V (VBAT) supply at the pc board level. On switching regulator SLICs, the VBAT voltage rate of rise must be limited as stated on the SLIC data sheet to prohibit excessive Contact any local Zarlink sales office for the availability of additional, more detailed application notes. 14 Zarlink Semiconductor Inc. SLIC Devices Ringer Threshold see “Ringing Circuit” Section +5 V R4 RB1 + High Voltage Ringing Source – R2 Low Voltage DA CHP RF2 A HPA CBX D2 KR VIN1 AGND/ DGND RDC B RDC1 ** CFIL VREG CBAT D1 ** Battery D6 ** RCH ** CQ RRX RDC2 CGKF (optional) QBAT DGND DXA TSCA C3 C31 C2 C21 DXB C1 C4 C11 C41 C51 CS1 TSCB DET CHCLK DCLK CHCLK L VBAT VOUT1 U2 1/2 Le79C02 DSLAC Device CDC GKF BGND FS AGND1 RT RSN TESTOUT D3 2.048 MHz Clock CD (optional) RD RINGOUT KT MCLK PCLK HPB RING ** L VEE1 VCCA1 VEE VCC VTX CAX U3 +5 V/+12 V –5 V RD DB RF1 KR U1 Le7942 SLIC CRT R3 TIP Application Note E1 DRA DRB DIN DOUT PCM Interface CAS CAS Battery Ground CCH2 ** CCH1 ** CHS Microprocessor Interface Digital Ground Analog Ground ** The parts marked by a double asterisk (**) are not needed for 24 V battery operation without using switching regulator. For use without the switcher, delete the noted parts and connect together: VBAT, CHS, QBAT, L, and VREG pins. Figure 9. Single Channel of a Dual Channel Subscriber Line Circuit with Switcher Components 15 Zarlink Semiconductor Inc. SLIC Devices Table 2. Application Note Parts List — Single Channel Subscriber Line System (See Figure 9 for Circuit) U1 Le7942 SLIC*** U2 Le79C02 DSLAC device*** KR, KT Relay, 2C contacts, 1500 V rating L Inductor, 1 mH, 5%** D1 Diode, 100 V, 100 mA, 4 ns** U3 Dual transient suppressor D2, D3, D6 Diode 100 V, 100 mA, 10 ns RF1, RF2 Resistor, fuse, 20 Ω to 50 Ω R2 Resistor, 800 Ω, 3%, 3 W (Ring feed resistor)* RB1 Resistor, 1 MΩ, 1%, 1/4 W R3 Resistor, 825K, 1%, 1/4 W R4 Resistor, 452K, 1%, 1/4 W RCH Resistor, 1.3K, 1%, 1/4 W** RD Resistor, 35.4K, 1%, 1/4 W (sets off-hook threshold)* RT Resistor, 100K, 1%, 1/4 W (sets two-wire impedance)* RRX Resistor, 100K, 1%, 1/4 W (sets two-wire impedance)* RDC1, RDC2 Resistor, 7.14K, 1%, 1/4 W (sets loop current)* RTMG Resistor 1700 Ω, 5%, 2 W (Am7943) CRT1 Capacitor, 0.1 µF, 20%, 100 V CDC Capacitor 0.47 µF, 20%, 10 V CHP Capacitor, 0.33 µF, 20%, 100 V CCAS Capacitor, 0.15 µF, 20%, 100 V CAX, CBX Capacitor, 2200 pF, 20%, 100 V CFIL Capacitor, 0.47 µF, 10%, 100 V, metallized polyester** CBAT Capacitor, 0.47 µF, 20%, 100 V CQ Capacitor, 0.33 µF, 20%, 100 V** CCH1 Capacitor, 0.015 µF, 10%, 50 V, X7R ceramic** CCH2 Capacitor, 560 pF, 10%, 100 V, X7R ceramic** CD Capacitor, 0.01 µF, 20%, 10 V (sets off-hook filtering)* CGKF Capacitor, 3300 pF, 10%, X7R ceramic Notes: * The parts marked by an asterisk (*) are user-programmable. The values shown can be altered to suit the application. ** The parts marked by a double asterisk (**) are not needed for 24 V battery operation without a switcher. *** Obsolete; no longer in production. Please contact your Zarlink sales representative for another solution. 16 Zarlink Semiconductor Inc. SLIC Devices Ringer Threshold see “Ringing Circuit” Section RB1 + R4 High Voltage Ringing – Source R2 DA RF1 A(TIP) KR U3 B(RING) CBX KR RF2 B(RING) +5 V Low Voltage –5 V VEE1 VEE U1 VCC Le7953X/57X CRT SLIC DB RD VTX CAX AGND/ A(TIP) DGND HPA CHP RSN HPB R3 RDC KR RINGOUT KT C3 TESTOUT C2 CFIL RD VIN1 AGND1 RT RDC1 CBAT VBAT D6 RCH CCH1 CCH2 CQ 2.048 MHz Clock CD RRX RDC2 CDC DGND C21 C11 C41 C51 CS1 CHCLK DET PCLK FS VOUT1 U2 1/2 Le79C02 DSLAC Device C31 VREG CHCLK E0 E1 L VBAT D1 MCLK VCCA1 C1 C4 BGND Application Note DCLK DXA TSCA DXB TSCB DRA DRB DIN DOUT QBAT CHS Microprocessor Interface Battery Ground Digital Ground Analog Ground Figure 10. Single Channel of a Dual Channel Subscriber Line Circuit 17 Zarlink Semiconductor Inc. PCM Interface SLIC Devices Table 3. Application Note Parts List — 1/2 of a Dual Channel Subscriber Line System (see Figure 10 for Circuit) U1 Le7953X** or Le7957X SLIC** U2 Le79C02 DSLAC device** KR, KT Relay, 2C contacts, 1500 V rating L Inductor, 1 mH, 5% D1 Diode, 100 V, 100 mA, 4ns U3 Dual transient suppressor D6 Diode 100 V, 100 mA, 10 ns RF1, RF2 Resistor, fuse, 50 Ω* R2 Resistor, 800 Ω, 3%, 3 W (Ring Feed Resistor)* RB1 Resistor, 1 meg, 1%, 1/4 W R3 Resistor, 8.25K, 1%, 1/4 W R4 Resistor, 452K, 1%, 1/4 W RCH Resistor, 1.3K, 1%, 1/4 W RD Resistor, 51.1K, 1%, 1/4 W (sets off-hook threshold)* RDC1, RDC2 (Le7953X) Resistor, 31.25K, 1%, 1/4 W* RDC1, RDC2 (Le7957X) Resistor, 20K, 1%, 1/4 W* RT Resistor, 560K, 1%, 1/4 W* RRX Resistor, 560K, 1%, 1/4 W (sets receive gain)* CRT Capacitor, 0.047 µF, 20%, 100 V CDC Capacitor, 0.15 µF, 10%, 10 V CHP Capacitor, 0.33 µF, 20%, 100 V CAX, CBX Capacitor, 2200 pF, 20%, 100 V CFIL Capacitor, 0.15 µF, 10%, 100 V metallized polyester CBAT Capacitor, 0.47 µF, 20%, 100 V CQ Capacitor, 0.33 µF, 20%, 100 V CCH1 Capacitor, 0.015 µF, 10%, 50 V, X7R ceramic CCH2 Capacitor, 560 pF, 10%, 100 V, X7R ceramic CD Capacitor, 0.01 µF, 20%, 10 V (sets off-hook filtering)* Note: * The parts marked by an asterisk (*) are user-programmable. The values shown can be altered to suit the application. ** Obsolete; no longer in production. Please contact your Zarlink sales representative for another solution. 18 Zarlink Semiconductor Inc. SLIC Devices RB1 Ringing + Source – High Voltage RB2 R2 R1 R4 TIP A KR CHP HPB RF2 CBX KR KR RT RDC CFIL VREG CBAT L RRX –54 V to –70 V CO Battery L PCLK FS VOUT1 RDC1 CDC C3 VMG Metering Injection Circuit, see Figure 13 IN ENA 16 kHz Source U2 1/2 Le79C02 DSLAC Device DXA C31 C21 C11 C41 C51 CS1 CHCLK DCLK C1 +5 V C4 DET CHCLK E0 D1 VIN1 AGND1 C2 BGND 2.048 MHz Clock RDC2 B TESTOUT MCLK DGND1 Metering Filter RINGOUT KT CD RD RSN HPA U3 RING VEE1 VCCA1 VTX AGND/ DGND CAX RF1 –5 V VEE U1 VCC Le79M53X CRT2 or DB Le79M57X SLIC RD R3 +5 V Low Voltage CRT1 DA Application Note E1 TSCA DXB TSCB DRA DRB DIN DOUT VBAT D6 RCH CCH1 CCH2 CQ QBAT CHS Microprocessor Interface Battery Ground Digital Ground Analog Ground Figure 11. Single Channel of a Dual Channel Metering Subscriber Line Circuit 19 Zarlink Semiconductor Inc. PCM Interface SLIC Devices Table 4. Application Note Parts List — 1/2 of a Dual Channel Metering Subscriber Line System (See Figure 11 for Circuit) U1 Le79MXXX SLIC** U2 Le79C02 DSLAC Device** KR, KT Relay, 60 V coil, 2C contacts, 1500 V rating L Inductor, 1 mH, 5% D1 Diode, 100 V, 100 mA, 4 ns U3 Dual transient suppressor D6 Diode 100 V, 100 mA, 10 ns RF1, RF2 Resistor, fuse, 20 Ω R1, R2 Resistor, 400 Ω, 3%, 3 W (Ring Feed resistors)* RB1, RB2 Resistor, 249K, 1%, 1/4 W R3, R4 Resistor, 205K, 1%, 1/2 W RCH Resistor, 1.3K, 1%, 1/4 W RD Resistor, 51.1K, 1%, 1/4 W (sets off-hook threshold)* RT Resistor, 286K, 1%, 1/4 W (sets two-wire impedance)* RRX Resistor, 560K, 1%, 1/4 W (sets receive gain)* RDC1, RDC2 (Le79M53X) Resistor, 31.25K, 1%, 1/4 W (sets 40 mA loop current)* RDC1, RDC2 (Le79M57X) Resistor, 20K, 1%, 1/4 W (sets 800 Ω resistive feed)* CRT1, CRT2 Capacitor, 0.43 µF, 20%, 100 V CDC Capacitor 0.1 µF, 20%, 10 V CHP Capacitor, 0.33 µF, 20%, 100 V CAX, CBX Capacitor, 2.2 pF, 20%, 100 V CFIL Capacitor, 0.47 µF, 10%, 100 V, metallized polyester CBAT Capacitor, 0.47 µF, 20%, 100 V CQ Capacitor, 0.33 µF, 20%, 100 V CCH1 Capacitor, 0.015 µF, 10%, 50 V, X7R ceramic CCH2 Capacitor, 560 pF, 10%, 100 V, X7R ceramic CD Capacitor, 0.01 µF, 20%, 10 V (sets off-hook filtering)* Note: * The parts marked by an asterisk (*) are user-programmable. The values shown can be altered to suit the application. ** Obsolete; no longer in production. Please contact your Zarlink sales representative for another solution. 20 Zarlink Semiconductor Inc. SLIC Devices CMF2 RMF3 Application Note RMF6 CMF3 – IN (VTX) + RMF4 OUT U5 RMF7 RMF5 RMF8 Figure 12. 16 kHz Metering Notch Filter RSN RMI1 M1 VMG 12/16 kHz, 1 Vrms DMI1 RMI2 +5 V VMG Enable RMI3 RMI4 CMI2 CMI1 Figure 13. Metering Injection Circuit 21 Zarlink Semiconductor Inc. 0 SLIC Devices Application Note Table 5. Parts List for Le79M53X/Le79M57X Metering Notch Filter (See Figure 12 for Circuit) FNOTCH 12 kHz 16 kHz RMF3 Resistor 5.07K 4.0K 1%, 1/4 W* RMF4 Resistor 5.39K 5.58K 1%, 1/4 W* RMF5 Resistor 22.0K 22.0K 1%, 1/4 W* RMF6 Resistor 37.9K 27.9K 1%, 1/4 W* RMF7 Resistor 2.17K 2.25K 1%, 1/4 W* RMF8 Resistor 8.84K 8.84K 1%, 1/4 W* CMF2 Capacitor 1.0 nF 1.0 nF 5%, 10 V* CMF3 Capacitor 1.0 nF 1.0 nF 5%, 10 V* Table 6. Parts List for Metering Injection Circuit (See Figure 13 for Circuit) RMI1 (5.1 V metering) Resistor, 3.62K, 1%, 1/4 W* RMI1 (2.2 V metering) Resistor, 8.33K, 1%, 1/4 W* RMI2 Resistor, 200K, 1%, 1/4 W* RMI3 Resistor, 300K, 1%, 1/4 W* RMI4 Resistor, 300 Ω, 1%, 1/4 W* CMI1 Capacitor, 220 nF, 10%, 10 V* CMI2 (16 kHz metering) Capacitor, 39 nF, 10%, 10 V* CMI2 (12 kHZ metering) Capacitor, 51 nF, 10%, 10 V* M1 N Channel MOS transistor, 2N7000, 2N7002 or equivalent DMI1 Diode, 100 V, 100 mA, 10 ns Note: The parts marked by an asterisk (*) are user programmable. The values shown can be altered to suit the application. 22 Zarlink Semiconductor Inc. SLIC Devices Application Note Shared Ri ng Threshold CRT CTH RRTH2 RSR4 RRTH1 RING BUS DA RR1 RSR1 RFA TIP DB CAD RR RING TO HPB BX TI CBD 3 TEST OUT BGND Cbat TEST IN Vbat K +5 V RR D1 CD CBP1 Agnd1 RDC RDC2 RDC1 TI K TO Vin1 Iref CDC C1, C2 RDO, RYO1,2 BGND Vbat TMG VNEG D0 D1 DET CAS 2 CD21, C31 C41 C51 CD11 CAS CFIL Mclk/E1 Pclk/DCL FS/FSC DXA/DU DRA/DD DIO/S1 Dclk/S0 CS/PG RST PCM/MPI MODE MCLK/E1 PCLK FS DXA DRA DI0 DCLK CS0 (Normally High) RST Vref1 GCI MODE RNEG TIP SLIC1 7 RING TIP RING U2 Am79Q061 QSLAC Vout1 Dgnd RRC CRC RTMG K RREF CTX RT RSN CHP Vbat RFB Vcc RD Vtx AX HPA RR U3 +5 V Vcc U1 RD Am7920 SLIC Agnd SLIC2 Mclk/E1 Pclk/DCL FS/FSC DXA/DU DRA/DD DIO/S1 Dclk/S0 CS/PG RST 7 TIP 7 SLIC3 RING Figure 14. Le7920 SLIC/QSLAC Device Application Circuit 23 Zarlink Semiconductor Inc. E1 DCL FSC DU DD S1 S0 RST SLIC Devices Table 7. Application Note Parts List — 1/4 of a Four Channel Subscriber Line System (see Figure 14 for Circuit) U1 Le7920 U2 Le79Q061 QSLAC™ device** KRR, KTI, KTO Relay, 2C contacts, 1500 V rating D1 Diode, 100 V, 100 mA U3 Teccor PO640SA transient suppressor RF1, RF2 Resistor, fuse, 50 Ω* RR1 Resistor, 400 Ω, 3%, 3 W (Ring Feed Resistor)* RSR1, RRTH1 Resistor, 1 meg, 1%, 1/4 W RSR4 Resistor, 5.5K, 1%, 1/4 W (shared between all 4 SLICs; use 2.2M if not shared) RRTH2 Resistor, 400K, 1%, 1/4 W (shared between all 4 SLICs; use 1.6M if not shared) RTMG Resistor, 1K, 5%, 1/2 W RD Resistor, 37.4K, 1%, 1/4 W (sets off-hook threshold)* RDC1, RDC2 Resistor, 16K, 1%, 1/4 W* RT Resistor, 200K, 1%, 1/4 W* RRC Resistor, 124K, 1%, 1/4 W (sets receive gain)* CRT, CTH Capacitor, 0.068 µF, 20%, 50 V CDC Capacitor, 0.27 µF, 10%, 50 V CHP Capacitor, 0.27 µF, 20%, 100 V CAD, CBD Capacitor, 2200 pF, 20%, 100 V CAS Capacitor, 0.1 µF, 10%, 100 V CBAT Capacitor, 0.01 µF, 20%, 100 V CFIL, CRC, CTX, CBP1 Capacitor, 0.1 µF, 10%, 50 V CD Capacitor, 0.01 µF, 20%, 10 V (sets off-hook filtering)* Note: * The parts marked by an asterisk (*) are user-programmable. The values shown can be altered to suit the application. ** Replaced by the Le58QL061 QLSLAC™ device. 24 Zarlink Semiconductor Inc. RING RING TIPTIP Zarlink Semiconductor Inc. 25 A U2 K2 K2 BAT2 C2 0.01 µF D3 RNEG 10 kΩ D2 D1 NC NC NC NC NC Prot. Rtn CHP 18 nF C1 0.1 µF CBX 2.2 nF A NC TISP 61089 G K1 K1 BAT1 RFB 25 Ω BAT1 RFA 25 Ω CAX 2.2 nF RRT1 515 kΩ RRT2 12 kΩ CRT 1.5 µF VNEG VBAT2 VBAT1 U1 VCC Figure 15. Single Channel Ringing Subscriber Line Circuit AGND/DGND RINGIN B2EN C3 C2 C1 DET E1 VTX RDCR RDC RSN RD RSGL RSGH C3 0.1 µF Am79R79 SLIC BGND RYOUT1 RYOUT2 RYE D2 D1 B(RING) HPB HPA A(TIP) RTRIP2 RTRIP1 +5 V RDCR2 15 kΩ CSLEW 0.33 µF RSLEW 150 kΩ CDCR 10 nF RDCR1 15 kΩ CDC 0.82 µF RDC1 50 kΩ RDC2 50 kΩ RD 66 kΩ RSGL Open RSGH Open CVRX 0.1 µF CB 0.1 µF RBAT2 365 kΩ ROUT1 47 kΩ CVTX 0.1 µF RIN 47 kΩ RM 68 kΩ RBAT1 365 kΩ BAT1 RT 360 kΩ CM 0.01 µF RRX 220 kΩ NC NC NC NC NC IBAT I/O4 I/O3 I/O2 I/O1 C2 C1 VIN VREF VM VOUT U3 VCCD +5 V NC NC IRTA Am79C2031 ASLAC Device IRTB IDC VLBIAS IAB IDIF ISUM AGND VCCA +5 V RIN CMOS RINGIN MCLK MPIINTERFACE INTERFACE MPI PCMINTERFACE INTERFACE PCM RREF 7.87 kΩ IREF MCLK RST INT CS DCLK DI/O DRA TSCA DXB DRB TSCB FS PCLK DXA DGND SLIC Devices Application Note SLIC Devices Table 8. Application Note Parts List – Single Channel Ringing Subscriber Line Circuit D1 1N400X D2 1N400X D3 1N400X C1 0.1 µF, 20%, 100 V Vbat1 dependent C2 0.01 µF, 20%, 100 V Vbat1 dependent C3 0.1 µF, 20%, 10 V Supply decoupling C4 0.1 µF, 20%, 10 V Supply decoupling C5 0.1 µF, 20%, 10 V Supply decoupling CAX 2.2 nF, 20%, 100 V EMI suppression CBX 2.2 nF, 20%, 100 V EMI suppression CRT 1.5 µF, 10%, 10 V Application dependent CHP 18 nF, 20%, 100 V CDC 820 nF, 20%, 5 V Application dependent CDCR 10 nF, 20%, 5 V Application dependent CM 10 nF, 20%, 5 V Application dependent CSLEW 0.33 µF, 20%, 5 V Application dependent CVTX 0.1 µF, 20%, 5 V CVRX 0.1 µF, 20%, 5 V CB 0.1 µF, 20%, 100 V RFA 25 Ω, 2%, 2 W Value and rating application dependent RFB 25 Ω, 2%, 2 W Value and rating application dependent RRT1 515 kΩ, 1%, 1/8 W RRT2 12 kΩ, 1%, 1/8 W RD 66 kΩ, 1%, 1/8 W Application dependent RDCR1 15 kΩ, 1%, 1/8 W Application dependent RDCR2 15 kΩ, 1%, 1/8 W Application dependent RDC1 50 kΩ, 1%, 1/8 W Application dependent RDC2 50 kΩ, 1%, 1/8 W Application dependent RT 360 kΩ, 1%, 1/8 W Application dependent RRX 220 kΩ, 1%, 1/8 W Application dependent RM 68 kΩ, 5%, 1/8 W Application dependent ROUT1 47 kΩ, 1%, 1/8 W Application dependent RIN 47 kΩ, 1%, 1/8 W Application dependent RBAT1 365 kΩ, 1%, 1/8 W RBAT2 365 kΩ, 1%, 1/8 W RREF1 7.87 kΩ, 1%, 1/8 W RNEG 10 kΩ, 10%, 1/4 W RSLEW 150 kΩ, 1%, 1/8 W U1 Le79R79 U2 TISP61089 U3 Le79C2031 26 Zarlink Semiconductor Inc. Application dependent Application dependent SLIC Devices Application Note DOCUMENT REVISION HISTORY Revision A • Originally, this document was printed in the SLIC Introduction chapter of the “Linecard Products for the Public Infrastructure Market Databook” (PID 18503B), pgs. 1-7–1-32. • The document was again released on the "Communication Products CD-ROM” (PID 21812B) as the SLIC Functional Description.” • In this document, the first equation under the Ringing Circuit heading, currently on pg. 12, in the last revision contained the following information: R B2 R B1 ( R LMAX + R FEED ) -------- = -------- = ------------------------------------------R1 R4 R LMAX The equation has been changed to: R B1 R B2 ( R LMAX + R FEED ) --------- = -------- = ------------------------------------------R3 R4 ( R LMAX + R 1 ) Revision A to B • Updated OPNs (Ordering Part Numbers) throughout the document Revision B1 to B2 • Added new headers/footers due to Zarlink purchase of Zarlink on August 3, 2007 27 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE