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CESoP PROCESSORS ZL50115/6/7
PRODUCT PREVIEW
The ZL50117 family of low-density CES-over-Packet processors is a powerful
and flexible method for carrying TDM voice and data traffic, with associated
timing and signaling, across Ethernet, IP, and MPLS networks.
Each device provides a flexible TDM interface with embedded timing solution
that fully meets T1/E1 timing and synchronization standards. With an integrated DPLL, internal jitter buffer memory and FE/GE packet interface, the
ZL50117 processor family reduces BOM (bill of material) and board space and
simplifies access equipment design.
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Programmable multi-protocol
packet encapsulation supports RTP,
UDP, Ethernet VLANs, IPv4, IPv6
and MPLS, PWE3 and MEF Circuit
Emulation standards
Patented hardware/software
techniques for clock recovery and
synchronization
Advanced QoS mechanism allows
traffic prioritization
Extremely low and stable latency,
intrinsic delays of <500 ms
Embedded timing recovers clocks
across packet networks
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Nx64 kbps trunking for traffic
grooming and fractional T1/E1
services
Embedded Timing
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Flexible TDM access interface
supports T1/E1, T3/E3, H.110,
H-MVIP and ST-BUS streams
Carrier-Grade Voice Quality Support
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CESoP Processors Expand Reach
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ZL50115
1 T1 or 1 E1 stream or 1 MVIP/ST-BUS stream at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
(Maximum of 32 DS0 or Nx64 Kbps channels)
ZL50116
2 T1 or 2 E1 streams or 2 MVIP/ST-BUS streams at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps
(Maximum of 64 DS0 or Nx64 Kbps channels)
ZL50117
4 T1 or 4 E1 streams or 1 J2, 1 T3, 1 E3 or 1 STS-1 stream or
4 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS
streams at 8.192 Mbps
Per-port T1/E1 clock recovery for
asynchronous streams
Adaptive clock recovery far
exceeding G.823 for E1 and G.824/
T1.403 for T1 timing
Dual-reference Stratum 3 DPLL
supports TDM H.110 and H-MVIP
master and slave timing operation
Standard Compliant
ITU-T recommendation Y.1413
Applications
Legacy traffic over PSN
TDM over Wi-Fi and WiMAX
3G Wireless Backhaul
IETF PWE3 draft standards
CESoPSN and SAToP
MEF Implementation Agreement for
PDH circuits (8.0)
MPLS Forum CESoMPLS
Implementation Agreement (8.0.0)
Customer Support
Evaluation boards and API are available, supported by Zarlink’s network of
in-house application engineers.
CESoP PROCESSORS ZL50115/6/7
APPLICATION
Access Networks
CES-over-Packet technology allows service providers to
destination, queued based on sequence number, with lost
roll out packet-based access networks, while still providing
packets filled-in to maintain timing integrity.
customers with legacy T1/E1 services.
An on-chip per-stream DCO (Digitally Controlled Oscillator)
The diagram below shows how the ZL50117 low-density
ensures precise synchronization of T1/E1 traffic across the
CESoP processor seamlessly emulates TDM traffic, such as
packet network. Patent-pending software supports adaptive
POTS, T1/E1 and fractional T1/E1, across an IP, MPLS or
or differential timing so the best scheme can be used for a
Ethernet network. With Zarlink’s CESoP processors, a wired,
given application. For added flexibility, the ZL50117 proces-
wireless or optical packet network infrastructure can deliver
sor can be configured to act as the master or slave timing
converged voice and data services.
source using the embedded Stratum 3/4/4E DPLL.
The TDM interface allows the device to be used directly
The ZL50117 device is equipped with on-board memory that
with Codecs and framers in structured CES mode. In un-
compensates for up to 128 ms of PDV (Packet Delay Varia-
structured CES mode, the device interfaces directly to LIUs,
tions) in the network, with external support for up to 128 ms.
providing independent timing recovery for each TDM port.
The device supports up to 128 DS0, 4 T1/E1 or 1 J2.
Zarlink offers the industry’s only end-to-end portfolio of circuit-to-packet devices with densities ranging from 1 to 32
The ZL50117 chip ensures high QoS, and supports four
T1/E1 (32 to 1024 DS0) streams. The single-chip approach
classes of service on packet egress for priority treatment of
eliminates external circuitry, providing a cost-effective system-
time-sensitive traffic. When packets are received from the
level solution that saves board space compared to equivalent
Ethernet network, they are parsed to determine the egress
discrete designs using communications processors.
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Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries is believed to be reliable.
The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice.
ZARLINK, ZL, and the Zarlink logo are trademarks of Zarlink Semiconductor Inc.
© 2004, Zarlink Semiconductor Inc. All Rights Reserved.
Publication Number PP5902
www.ZARLINK.com