5 4 3 2 +5V analog supply 32 bit 66MHz PCI bus Jn3 (64 bit, not used) LT101 9 +5V reference PCI_CLK source select & rate multiplier (x1 or x2) U17, U18 & U20 Clock buffer U19 S_CLK source select P8 RS232 #2 Local bus xtal clock generator Frequency measurement input to 8260 CPM Programmable clock skew generator (U40) S_CLK U30 -12V Address A[2..20] Power inlet from external PSU +5V dc @ 10A PWR +5V Data D[0..31] 3.3V 1.8V +3.3V Off board +3.3V Output frequency select C Clk/Frm A Clk / frm MUX 32-bit 66MHz PCI interface ClkA WAN_CLKi[0..31] MT90880 x32 ClkB Frm A WAN_FRMi[0..31] x32 Frm B nCS_ODXA nCS_ODXB nCS_ODX C WAN_STo[0..31] Local ST inputs WAN_STi[0..31] Local ST outputs Power 10/100Mbps packet i/f Clk Frm External user clock input Clk/Frm B WAN interface 32 streams +12V Control Frm Local TDM interface Frame 32 streams Clk 8.192M Hz clock conditioning ODX-B LControl PS2 B clock Clock & frame outputs Buffer LD[0..15] +1V8 SSRAM SSRAM interface interface U29,31 MT9045 system synchroniser U35 8.192MHz clock conditioning ODX-A Altera 6016A FPGA EPC1441 config device Mode select & JTAG 80-way SIMM connector +2V5 User clock output 16-bit local bus interface ByteBlaster socket RAM_CLK +3V3 U27 Sec Pri Clock inputs MT9045 system synchroniser U35 A clock LA[1..31] Power supply regulators Clock A frequency measurement o/p x1, x2 or x4 xtal freq Synchronous SRAM SIMM card 256k -> 8Mbyte PS1 Control LControl Pri Sec Clock inputs Clk S_CLK C LD[0..15] Clock multiplier (default x2) U22 External S_CLK input SPI to DAC SPI to codec Data Clock B 2.048MH z Clock A 2.048MH z Clock & frame outputs 10/100 Ethernet Extended PPMC connectors Jn 4-6 D LA[1..31] Address Local bus interface 33MHz TCXO SPI Divide by 8 Voltage-contolled oscillator Temperature-compensated oscillator PLX PCI9056 PCI target and arbiter 33MHz xtal oscillator RS232 #1 Divide by 8 16.384M Hz VCXO 14 bit DAC SPI device 1 32 bit 66MHz PCI interface 16.384MHz crystal oscillator, uncompensated 16.384M Hz TCXO 33MHz xtal oscillator External P7 PCI_CLK input 16Mb Flash ROM Configuration EEPROM U3 Chip selects Standard PPMC connectors 256Mb SDR AM PCI_CLK3 Jn2 PCI_CLK2 D PCI_CLK0 Jn1 CPU card PCI_CLK1 M66_EN Wind River PPMC8260 1 16-bit programming bus interface Out MT90869 Octal Digital Switch (ODX) Current monitoring +1.8V Off board +1.8V Clock & frame ODX A Clk In Frm Backplane interface B B Fast Ethernet interface #0 RJ45 with int. magnetics 8.192M Hz clock conditioning ODX-C DM9161 10/100Mbps Ethernet PHY (MII / RMII) J28 (0..15) U26, RN82-RN97 DM9161 J33 (16..31) SPI device 0 Frame Data port Codec data Clock 16-bit programming bus interface Local ST inputs MT90869 Octal Digital 16-bit programming bus interface Control port Handset jack #1 MT92303 dual codec WAN_STo[0..31] WAN_STi[0..31] Backplane interface Handset jack #2 LControl LA[1..31] 25MHz (MII) / 50MHz (RMII) PHY clock LD[0..15] 40-pin sub-D MII socket (P11) A Backplane interface connectors (ODX A) WAN stream terminations LControl RJ45 with int. magnetics J8 (16..31) STi, STo, CLK & FRM available Local stream logic analyser headers (2 off) LA[1..31] Fast Ethernet interface #1 J10 (0..15) WAN logic analyser headers (8 off) LD[0..15] 40-pin sub-D MII socket (P12) LSTo[0..31] & LSTi[0..31] Codec data 10/100Mbps Ethernet PHY (MII / RMII) Switch (ODX) Local ST outputs Out Clock & frame Clk ODX B In Backplane interface Frm MT90869 Octal Digital Switch (ODX) Backplane interface connectors (ODX B) ODX C J9 (0..15) A J7 (16..31) Local ST bus interface Zarlink Semiconductor Cheney Manor UK Swindon Title Local interface connectors (ODX C) C 2001, 2002 Copyright Zarlink Semiconductor J38 (0..15) MT90880 Lab Evaluation Board V1R1 : Block diagram J37 (16..31) Size Document Number Rev 1.0 C385ACS29 Date: 5 4 3 2 Tuesday, May 28, 2002 Sheet 1 1 of 21 5 4 3 1 Notes INDEX D 2 PAGE DESCRIPTION 1. Refer to Zarlink document "MT90880 Lab Test Card Layout Guidelines" (document number C385ACS35) for details of physical PCB layout. 1 Block diagram 2 Unused gates and index 2. Adhere to recommendations in Davicom data sheet DM9161-DS-P03 regarding the layout and ground/power plane arrangements for U12 & U13 3 Power supply regulators and MT90880 power pins 4 66MHz PCI, system & TDM clocks 5 FPGA - Clock & frame pulse steering 6 MT90880 WAN data streams 7 WAN streams logic analyser connectors 8 MT90880 lLocal data streams & connectors, ODX C 9 ODX A & B (WAN) backplane header connections 10 ODX A & ODX B (WAN) - Power, control & JTAG 11 ODX C (local) power, control & JTAG 12 PCI bus interfaces and connectors 13 PCI to local (control) bus interface 14 FPGA - Local bus interface 15 100Mbit fast ethernet interface #0 and clock gen 16 100Mbit fast ethernet interface #1 17 Synchronous static RAM interface 18 MT90880 : JTAG, reset & test 19 Extended PMC interface connectors 20 Dual codec interface 21 8.192MHz clock conditioning circuits D 3. ’DNF’ denotes a component that is not populated C B C +3V3 U50F 13 U50E 12 11 74LCX04 R247 U50D 10 9 74LCX04 0R 1 8 74LCX04 R249 2 U20A 74LCX04 0R 11 10 A R248 R234 0R 0R 13 R251 0R 12 R252 R241 8 11 U18D 74LCX00 10 R244 +3V3 0R 9 0R R245 0R R238 0R R239 0R R242 0R U21D 74LCX125 12 D Q 9 11 CLK Q 8 A B 15 G U49B Y0 Y1 Y2 Y3 12 11 10 9 14 13 A B 15 G Y0 Y1 Y2 Y3 12 11 10 9 74VHC139 13 10 CLR SD C 2001, 2002 Copyright Zarlink Semiconductor Zarlink Semiconductor Swindon UK MT90880 Lab Evaluation Board V1R1 : Unused gates and index U38B 74LCX74 0R 4 Cheney Manor Title Size A Date: 5 0R 14 13 B 12 12 R243 0R 74VHC139 13 U20F 74LCX04 0R 13 4 U24B R250 U20E 74LCX04 R240 3 U20B 74LCX04 U9F 74LCX04 R233 0R 3 Document Number C385ACS29 Tuesday, May 28, 2002 2 Rev 1.0 Sheet of 2 1 21 A 2 +5V to -12V inverter 0.25A max load 2 OUT 1 TAB 1 C240 L13 47µH + GND LT1764-1V8 GND 0R01 5 SENSE 3 1 C237 10µF + GND + 2 C239 10µF 6.3V TAB AD25 E23 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 P11 P12 EXT_3V3 4 OUT SHDN C236 10µF 6.3V 47µF 16V R172 IN + C320 10µF TP30 +1V8 +1.8V -12V U31 FB C242 100nF D25 AF25 C232 10µF 6.3V 2 REF R171 0R + GND 3 0R01 3 EXT_1V8 5 4 C241 10µF 3V3 CN1 3.96mm header + External variable MT90880 supply +3V3 +5V C319 100nF R216 100R R168 330R R176 Opt DNF 0Vin 2 + 2 SW9 C+K T101MH SPDT + CN3 SENSE - 3 +5V to +12V switching module 1A max load R217 330R 1 Vin Vout GND C284 1000nF PT5041C 2 3 J115 C286 + 1000nF 1 2 C285 100µF 63V C258 A MT3 MT4 MT5 MT6 MT7 MT8 MT9 MT10 MT11 MT12 MT13 MT14 C238 10µF + 100nF C246 +12V TP34 +12V PS2 TP44 TAG 1 VDD_IO_BK 1 J114 + 1 2 AUX +5V + AUX +12V 100nF C276 5 R175 Opt DNF 100nF C275 3 4 10µF 16V DNF A Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : Power supply regulators & MT90880 power PCB mountings Size B C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 B External +3V3 logic supply 100nF C271 1 100nF C245 Sense 1 2 +3V3 SHDN + CN2 POWER - 7 MT2 R174 Opt DNF 100nF +5V ON/OFF 6 MT1 C255 + 100nF C274 R246 0R 8 PWR1 DIN 8 socket + C315 470µF 50V 4 100nF C263 J116 + 3 R173 Opt DNF 10µF C243 STBY +5V ON G2RL1E VDD_CORE_BK 2 100nF C262 3 1 100nF C261 + C253 100nF C326 470µF 50V DNF 11 12 13 100nF C260 + LED16 Vout PS1 PT6501C Vout Vout 100nF C273 1 8 1 14 4 5 Vin Vin Vin Vadj 4 5 6 C CN4 3.96mm header +3V3 10µF C259 POWER 2 Power inlet +5Vdc @ 10A 7 2 6 3 GND GND GND GND LED15 1 B PMLL4448 FS1 10A (T) D10 C325 C314 470µF 50V 470µF 50V DNF 7 8 9 10 4 3 ZD1 SMCJ5.0A TP33 3V3 +5V to +3V3 switching module 8A max load +5V 100nF C272 VCC RL1 P13 P14 P15 P16 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15 T16 100nF C282 4 8 SHDN + 3 V+ LX 5 GND LT1764-1V8 TP31 -12V D9 10BQ040 SENSE 100nF C252 SHDN L14 10µH J113 IDD_CORE 100nF C251 1 OUT 4 D 100nF C281 V+ 22µF 6.3V C U30 7 MAX765 6 C235 100nF VDD_CORE_BK 100nF C269 IN + R169 0R01 R170 2 C231 10µF 6.3V A J112 1 2 3 100nF C250 U29 B 100nF C268 TP28 +5V +5V + TP27 +1.8V TP26 +5V MT90880 Core Pwr A : On board B : Off board 100nF C249 MT90880 1.8V Core regulator VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO A1VDD VDD_IO VDD_IO A2VDD VDD_IO VDD_IO GND VDD_IO GND Power pins VDD_IO GND VDD_IO GND VDD_IO GND VDD_IO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 100nF C267 TAB TP29 GND C234 MT90880 Core current metering GND 3 AA22 AA5 AB13 AB14 AB21 AB22 AB5 AB6 E13 E14 E21 E22 E5 E6 F22 F5 M5 N22 N5 P22 P5 R22 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE 100nF C280 LT1764-2V5 MT90880 AA3 E2 F24 H23 J3 L1 M26 P23 R2 V3 W22 Y26 100nF C248 GND 10µF 6.3V EXT_1V8 C229 10µF 6.3V 100nF C266 SHDN + + 100nF C279 SENSE 5 100nF C265 1 U1G J111 IDD_IO 100nF C278 D 4 VDD_IO_BK 100nF C264 C230 OUT IN R167 0R01 100nF C277 2 +2V5 TP25 +2.5V U27 B 2 1 +5V J110 1 EXT_3V3 2 3 3V3 A MT90880 I/O Pwr A : On board B : Off board +5V to +2.5V linear regulator 1 100nF C247 3 100nF C233 4 2 1 5 3 2 Document Number C385ACS29 Tuesday, May 28, 2002 Rev 1.0 Sheet 1 3 of 21 5 4 3 2 1 +3V3 3V3 C210 100nF U50A R131 0R External PCI clock, 3.3V +3V3 1 2 R263 100R J82 PINHDR3x1 74LCX04 D 1 XT5 CFPS-73 33.00MHz 1 EN U19 1 REF OE 5 2 6 REFx4 GND 4 U18C 5 REF CLKOUT CY2305 74LCX00 8 2 1 6 9 R137 10k 10 3 CLKA2 2 CLKA4 GND 8 CLKA1 CLKA3 74LCX00 3 O/P 74LCX00 VDD 5 R133 24R U50B J84 1 2 3 A A : Force 66MHz (2x ext) Open : Force 33MHz (1x ext) B 3 R134 24R PCI_CLK1 PCI_CLK3 +VS 1 EN XT6 CFPS-73 16.3840MHz (Uncompensated) 3 O/P GND D 12 D Q 9 11 CLK Q 8 13 10 CLR SD 5 6 U16B 74LCX74 74LCX04 O/P 7 3 14 2 R146 3k3 3 1 U21A 74LCX125 8 +VS O/P C223 100nF 8 5 6 5 U20C 74LCX04 GND 6 4 3 U21B 74LCX125 7 R151 0R REF U22 CY2303 REFIN GND 2 OUT INPUT 2 5 TRIM TEMP 3 GND REF REFx2 5 REFx4 6 R148 14 C222 100nF R147 24R DNF 1 S_CLK 8 12 O/P C318 1000nF 8 3 1 J88 CLK Source 1 0 00 01 10 11 - Standard 33MHz - TXCO 33MHz - External - Disabled 13 GND 7 XT8 IQVCXO-173 16.384MHz (Socketted) R149 24R DNF Fit one only, default REFx2 for 66MHz 4 2 A B 1 G A R153 R154 3k3 3k3 Y0 Y1 Y2 Y3 J86 Controlled 16.384MHz source A B A : VCXO 1 2 3 R150 10k 2 D Q 5 3 CLK Q 6 1 4 CLR SD U23A 74LCX74 Controlled crystal oscillator (voltage or temperature) TP23 4.096MHz 14 +VS C224 100nF O/P 8 TCXO_16.384MHz GND 66MHz MT90880 Clock Generator 4 5 6 7 TP21 8.192MHz B : TCXO 1 GND TAG U24A 2 3 C217 1000nF 3V3 TP22 16.384MHz 11 U21C 74LCX125 8 B VC TP47 +3V3 VIN +VS 1 24R VOUT C218 10nF C219 100nF 4 Open : Disabled U20D 74LCX04 1 TP20 PTAT 2.1mV/K R215 100R 7 VDD OE 6 1 2 3 4 CLK DIN CS/LD DOUT 7 XT10 IQTCXO-251 16.384MHz (Socketted) 12 D Q 9 11 CLK Q 8 13 10 CLR SD CONT_4-096MHz U23B 74LCX74 A Zarlink Semiconductor 74VHC139 Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : 66MHz PCI, system & TDM clocks Size B C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 C TP19 DAC GND TAG 5 TP18 Test point XT9 IQTCXO-251 33.00MHz (socketted) U34 C215 100nF + U33 LM78L05A/SO U32 LT1019ACS8-5 GND C221 100nF +5V B 6 LTC1658 VOUT +3V3 2 2 1 8 +VS C220 100nF GND J124 C216 100nF R144 33R 1 EN C214 10µF 16V R143 33R +12V 4 1 ORD_4-096MHz C213 100nF 2 TP17 VCXO control +VS R145 3k3 R152 100R U16A 74LCX74 SPI_CLK SPI_DIN nSPI_CS1 XT7 CFPS-73 33.00MHz 9 6 CLR SD 4 R139 3k3 TP15 Test point 7 +3V3 R264 100R Q 1 4 TP14 4.096MHz PCI_CLK2 R138 24R TP16 DAC Vref P8 CLK R135 24R PCI_M66EN External MT90880 clock, 3.3V Q 3 +3V3 C 33MHz_DISABLE D 5 U50C 4 R142 10k 74LCX04 B : M66EN controls 2 PCI_CLK0 4 33/66MHz PCI Clock Generator +3V3 PCI Bus Freq A B : TCXO GND 2 1TCXO_16.384MHz 2 3 B Open : Disabled J83 PCI_DISABLE U18B J81 A : Uncompensated XO 6 PCI Clock disable 1 3 REFx2 REFIN R136 10k +VS R140 1k DNF Omit to enable 3 C212 100nF 4 U18A VDD CY2303 1 2 3 PCI source select Ext Int +3V3 8 TP12 8.192MHz Ordinary 16.384MHz source C211 100nF U17 7 GND GND GND GND TP42 TAG R130 3k3 2 3 6 7 R132 100R TP13 Test point 1 2 P7 3 2 Document Number Rev 1.0 C385ACS29 Tuesday, May 28, 2002 Sheet 1 4 of 21 5 4 C130 C131 C128 100nF 100nF 10µF +3V3 3 J50 Capture status A +3V3 1 2 SEC PRI J140 ODE A control FPGA Disable +3V3 4 R45 3k3 1 R44 +VS R41 10k EN 3 O/P B_2-048MHz A_2-048MHz GND XT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 CFPS-73 20MHz 20MHz nFOo_A TP4 A_CLK 2.048MHz 3V3 F8o_A C1-5o_A CONT_4-096MHz 2 D Q 5 3 CLK Q 6 1 4 C2o_A +3V3 CLR SD TP5 Lock A C19o_A R50 10k U8A 74LCX74 C U6F VSS TMS TCK RST TCLR TRST SECOOR TDI SEC TDO PRI PRIOOR VDD IDDQ OSCo FS1 OSCi FS2 VSS TEST F16o RSEL Clock A FOo MS1 RSP MS2 TSP VDD F8o IC C1.5o IC VDD NC LOCK VSS C2o PCCi C4o HOLDOVER C19o VDD FLOCK C6o VSS C16o TM C8o 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 C12 A12 K2 K19 ODE_A J56 ODX A frame i/p sel. 3 nFOo_A 2 F8o_A 1 U14 1 2 W12 (Sheet 21) 1 EN R55 Omit 3 O/P A_2-048MHz B_2-048MHz GND XT3 2 CFPS-73 20MHz B R54 1k 3V3 TP7 B_CLK 2.048MHz nFOo_B F8o_B ORD_4-096MHz 12 D Q 9 11 CLK Q 8 13 10 CLR SD C144 C145 C146 C147 C143 100nF 100nF 100nF 100nF 10µF TP8 Lock B +3V3 U8B 74LCX74 R58 10k +3V3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A C149 C150 C151 C152 C148 100nF 100nF 100nF 100nF 10µF + C19o_A nC16o_A C8o_A C6o_A CODEC_nC4i C2o_A C1-5o_A 9 10 11 12 13 14 15 16 1 TP36 TAG FS1_B FS2_B FS1_A FS2_A 11 10k R51 1k J57 User clock eb. 3 Enable 2 1 Auto R52 1k WAN_CLKi0 WAN_CLKi1 WAN_CLKi2 WAN_CLKi3 WAN_CLKi4 WAN_CLKi5 WAN_CLKi6 WAN_CLKi7 WAN_CLKi8 WAN_CLKi9 WAN_CLKi10 WAN_CLKi11 WAN_CLKi12 WAN_CLKi13 WAN_CLKi14 WAN_CLKi15 WAN_CLKi16 WAN_CLKi17 WAN_CLKi18 WAN_CLKi19 WAN_CLKi20 WAN_CLKi21 WAN_CLKi22 WAN_CLKi23 WAN_CLKi24 WAN_CLKi25 WAN_CLKi26 WAN_CLKi27 WAN_CLKi28 WAN_CLKi29 WAN_CLKi30 WAN_CLKi31 Open : Disable R53 47k J59 User clock 2/n8 3 2Mbps 2 Auto 1 RN63 10k J60 Sync A i/p freq select 2 1 4 2 2 1 Freq. 0 0 19.44MHz 0 1 8kHz 1 0 1.544MHz 1 2 1 1 1 2.048MHz (Dflt) 3 4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 R57 47k Open : 8Mbps 1 3 2 J61 Sync B i/p freq select 1 2 3 4 8 7 6 5 FPGA_CLK_SEL FPGA_CLK_EN RN64 10k TP9 Holdover B C8o_B C8o_A +3V3 FP8i W12 C8i C16o C8o V13 FP16o W14 FP8o V14 J51 ODX B clock o/p sel. 3 C16o 2 1 C8o D 3 2 1 ODX B FP16o FP8o J53 ODX B fr o/p sel. 201 176 161 171 169 Streams-3T in_fp_a in_fp_b in_ck_a in_ck_b WAN_FRMi[0..31] 24 172 179 user_clock user_ck_en User_Clk_2_n8 136 91 109 133 57 89 107 126 59 87 105 124 61 85 103 122 71 83 101 120 69 81 99 118 67 75 97 116 65 73 93 114 clko0 clko1 clko2 clko3 clko4 clko5 clko6 clko7 clko8 clko9 clko10 clko11 clko12 clko13 clko14 clko15 clko16 clko17 clko18 clko19 clko20 clko21 clko22 clko23 clko24 clko25 clko26 clko27 clko28 clko29 clko30 clko31 fpo0 fpo1 fpo2 fpo3 fpo4 fpo5 fpo6 fpo7 fpo8 fpo9 fpo10 fpo11 fpo12 fpo13 fpo14 fpo15 fpo16 fpo17 fpo18 fpo19 fpo20 fpo21 fpo22 fpo23 fpo24 fpo25 fpo26 fpo27 fpo28 fpo29 fpo30 fpo31 137 92 113 134 58 90 108 127 60 88 106 125 64 86 104 123 72 84 102 121 70 82 100 119 68 76 98 117 66 74 94 115 odx_rs_n ode_a ode_b ode_c 159 49 48 160 WAN_FRMi0 WAN_FRMi1 WAN_FRMi2 WAN_FRMi3 WAN_FRMi4 WAN_FRMi5 WAN_FRMi6 WAN_FRMi7 WAN_FRMi8 WAN_FRMi9 WAN_FRMi10 WAN_FRMi11 WAN_FRMi12 WAN_FRMi13 WAN_FRMi14 WAN_FRMi15 WAN_FRMi16 WAN_FRMi17 WAN_FRMi18 WAN_FRMi19 WAN_FRMi20 WAN_FRMi21 WAN_FRMi22 WAN_FRMi23 WAN_FRMi24 WAN_FRMi25 WAN_FRMi26 WAN_FRMi27 WAN_FRMi28 WAN_FRMi29 WAN_FRMi30 WAN_FRMi31 C nODX_RST ODE_A ODE_B ODE_C B WAN_CLKi[0..31] SW2 Synchroniser B mode A_2-048MHz J62 CES measurement freq select 3 2 1 Altera-EPF6016AQC208-1 J63 SRTS Frame Pulse Select 2.048MHz clock A 8.192MHz 9045 A output FREQ_MEASURE J134 CES/SRTS select 1 3 5 IN_FP_A 3 2 1 IN_FP_B Frame pulse A Frame pulse B R218 47k 2 4 6 SRTS_INT R181 0R P5 R253 100R U9E 74LCX04 10 10k IN_FP_A +3V3 8 7 6 5 U14 F1A +3V3 1 2 3 4 RESET ODE BORS LORS W13 IN_FP_B 10k 10k (C8o_B via clock A ’sec’ input) U9B 74LCX04 4 3 R47 MT90869 Clocks J54 ODX A frame o/p sel. R49 1 2 3 4 +3V3 U9A 74LCX04 2 8 7 6 5 4 3 2 1 FP8o PCCi RSEL MS2 MS1 SW3 User output clock frequency select FP16o R48 8 7 6 5 SW1 Synchroniser A mode MT9045AN + FP8o V14 3 2 1 U5F C12 A12 K2 K19 J55 ODX B frame i/p sel. 3 nFOo_B 2 1 F8o_B R46 (Sheet 21) +3V3 + VSS TMS RST TCK TRST TCLR TDI SECOOR SEC TDO PRI PRIOOR VDD IDDQ FS1 OSCo FS2 OSCi TEST VSS Clock B F16o RSEL FOo MS1 RSP MS2 TSP VDD F8o IC C1.5o IC VDD NC LOCK VSS C2o PCCi C4o HOLDOVER C19o VDD FLOCK C6o VSS C16o TM C8o R40 10k USER_CLK_IN U36 +VS W14 RN62 10k C6o_A nC16o_A C8o_A 8 7 6 5 4 R56 3k3 FP16o ODX A C8i C8o_B TP6 Holdover A 1 2 3 4 C142 100nF C8o FP8i 1 2 3 4 1 + C16o J52 ODX A clock o/p sel. W13 3 C16o 2 V13 1 C8o C8i_B C8o_A C137 C138 C136 100nF 100nF 10µF SEC PRI MT90869 RESET ODE BORS LORS PCCi RSEL MS2 MS1 n9045_RST +3V3 J58 Capture status B +3V3 R177 +3V3 C8i_A CODEC_nC4i C140 C141 C139 100nF 100nF 10µF J139 Disable ODE B control Clocks MT9045AN CODEC_nFOi FPGA R39 10k 10k R42 10k nODX_RST U35 1k n9045_RST ODE_B +3V3 1 J125 Global ODE control 1 2 8 7 6 5 C134 100nF D R43 Omit 2 1 2 3 + 1 2 3 + C132 C133 C129 100nF 100nF 10µF R182 0R P6 User clock output User clock input 5 TP37 TAG U9D 74LCX04 8 A USER_CLK_IN Zarlink Semiconductor R60 100R R254 100R 1P8W slide switch U9C 74LCX04 6 9 1 R59 100R J134 1 - 2 CES 3 - 4 User clock out 5 - 6 User clock in Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : FPGA - Clock & frame pulse steering Size B Document Number C385ACS29 Rev 1.0 C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Tuesday, May 28, 2002 Sheet 1 5 of 21 5 4 3 2 1 WAN_STi[0..31] WAN_FRMi[0..31] U1A D B WAN_STi0 WAN_STi1 WAN_STi2 WAN_STi3 WAN_STi4 WAN_STi5 WAN_STi6 WAN_STi7 WAN_STi8 WAN_STi9 WAN_STi10 WAN_STi11 WAN_STi12 WAN_STi13 WAN_STi14 WAN_STi15 WAN_STi16 WAN_STi17 WAN_STi18 WAN_STi19 WAN_STi20 WAN_STi21 WAN_STi22 WAN_STi23 WAN_STi24 WAN_STi25 WAN_STi26 WAN_STi27 WAN_STi28 WAN_STi29 WAN_STi30 WAN_STi31 WAN_STo0 WAN_STo1 WAN_STo2 WAN_STo3 WAN_STo4 WAN_STo5 WAN_STo6 WAN_STo7 WAN_STo8 WAN_STo9 WAN_STo10 WAN_STo11 WAN_STo12 WAN_STo13 WAN_STo14 WAN_STo15 WAN_STo16 WAN_STo17 WAN_STo18 WAN_STo19 WAN_STo20 WAN_STo21 WAN_STo22 WAN_STo23 WAN_STo24 WAN_STo25 WAN_STo26 WAN_STo27 WAN_STo28 WAN_STo29 WAN_STo30 WAN_STo31 E9 E10 A10 E11 B12 B13 A14 B15 A16 A17 E16 C18 E17 E18 A22 B22 B23 B24 D22 D26 G24 G25 G26 J25 K24 L25 M24 N25 P26 R26 U26 T22 WAN_STo0 WAN_STo1 WAN_STo2 WAN_STo3 WAN_STo4 WAN_STo5 WAN_STo6 WAN_STo7 WAN_STo8 WAN_STo9 WAN_STo10 WAN_STo11 WAN_STo12 WAN_STo13 WAN_STo14 WAN_STo15 WAN_STo16 WAN_STo17 WAN_STo18 WAN_STo19 WAN_STo20 WAN_STo21 WAN_STo22 WAN_STo23 WAN_STo24 WAN_STo25 WAN_STo26 WAN_STo27 WAN_STo28 WAN_STo29 WAN_STo30 WAN_STo31 MT90880 WAN TDM WAN_FRMi0 WAN_FRMi1 WAN_FRMi2 WAN_FRMi3 WAN_FRMi4 WAN_FRMi5 WAN_FRMi6 WAN_FRMi7 WAN_FRMi8 WAN_FRMi9 WAN_FRMi10 WAN_FRMi11 WAN_FRMi12 WAN_FRMi13 WAN_FRMi14 WAN_FRMi15 WAN_FRMi16 WAN_FRMi17 WAN_FRMi18 WAN_FRMi19 WAN_FRMi20 WAN_FRMi21 WAN_FRMi22 WAN_FRMi23 WAN_FRMi24 WAN_FRMi25 WAN_FRMi26 WAN_FRMi27 WAN_FRMi28 WAN_FRMi29 WAN_FRMi30 WAN_FRMi31 D9 C10 D10 D11 C13 A13 C14 C15 B16 D16 D17 B19 D18 C20 C21 C22 C23 A25 C26 F23 F26 H24 H26 J26 K26 L26 M25 N26 P25 R24 U24 W25 WAN_FRMi0 WAN_FRMi1 WAN_FRMi2 WAN_FRMi3 WAN_FRMi4 WAN_FRMi5 WAN_FRMi6 WAN_FRMi7 WAN_FRMi8 WAN_FRMi9 WAN_FRMi10 WAN_FRMi11 WAN_FRMi12 WAN_FRMi13 WAN_FRMi14 WAN_FRMi15 WAN_FRMi16 WAN_FRMi17 WAN_FRMi18 WAN_FRMi19 WAN_FRMi20 WAN_FRMi21 WAN_FRMi22 WAN_FRMi23 WAN_FRMi24 WAN_FRMi25 WAN_FRMi26 WAN_FRMi27 WAN_FRMi28 WAN_FRMi29 WAN_FRMi30 WAN_FRMi31 WAN_CLKi0 WAN_CLKi1 WAN_CLKi2 WAN_CLKi3 WAN_CLKi4 WAN_CLKi5 WAN_CLKi6 WAN_CLKi7 WAN_CLKi8 WAN_CLKi9 WAN_CLKi10 WAN_CLKi11 WAN_CLKi12 WAN_CLKi13 WAN_CLKi14 WAN_CLKi15 WAN_CLKi16 WAN_CLKi17 WAN_CLKi18 WAN_CLKi19 WAN_CLKi20 WAN_CLKi21 WAN_CLKi22 WAN_CLKi23 WAN_CLKi24 WAN_CLKi25 WAN_CLKi26 WAN_CLKi27 WAN_CLKi28 WAN_CLKi29 WAN_CLKi30 WAN_CLKi31 B9 B10 B11 C12 E12 D13 A15 D15 C16 C17 B18 A20 B20 B21 E19 A23 A24 A26 E24 E26 G22 H22 J24 J23 L24 K23 N24 M22 P24 N23 V26 U22 WAN_CLKi0 WAN_CLKi1 WAN_CLKi2 WAN_CLKi3 WAN_CLKi4 WAN_CLKi5 WAN_CLKi6 WAN_CLKi7 WAN_CLKi8 WAN_CLKi9 WAN_CLKi10 WAN_CLKi11 WAN_CLKi12 WAN_CLKi13 WAN_CLKi14 WAN_CLKi15 WAN_CLKi16 WAN_CLKi17 WAN_CLKi18 WAN_CLKi19 WAN_CLKi20 WAN_CLKi21 WAN_CLKi22 WAN_CLKi23 WAN_CLKi24 WAN_CLKi25 WAN_CLKi26 WAN_CLKi27 WAN_CLKi28 WAN_CLKi29 WAN_CLKi30 WAN_CLKi31 WAN_FRMO WAN_CLKO V23 V22 1 2 U5C U6C WAN_STo0 WAN_STo1 WAN_STo2 WAN_STo3 WAN_STo4 WAN_STo5 WAN_STo6 WAN_STo7 WAN_STo8 WAN_STo9 WAN_STo10 WAN_STo11 WAN_STo12 WAN_STo13 WAN_STo14 WAN_STo15 WAN_STo16 WAN_STo17 WAN_STo18 WAN_STo19 WAN_STo20 WAN_STo21 WAN_STo22 WAN_STo23 WAN_STo24 WAN_STo25 WAN_STo26 WAN_STo27 WAN_STo28 WAN_STo29 WAN_STo30 WAN_STo31 L18 L19 L20 M17 M18 M19 M20 N18 N19 N20 P17 P19 P20 R18 R19 R20 T18 T19 T20 U18 U19 U20 V17 V18 V19 V20 W18 W19 Y20 Y17 Y18 Y19 D LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 LSTi16 LSTi17 LSTi18 LSTi19 LSTi20 LSTi21 LSTi22 LSTi23 LSTi24 LSTi25 LSTi26 LSTi27 LSTi28 LSTi29 LSTi30 LSTi31 Local streams ODX A LSTo0 LSTo1 LSTo2 LSTo3 LSTo4 LSTo5 LSTo6 LSTo7 LSTo8 LSTo9 LSTo10 LSTo11 LSTo12 LSTo13 LSTo14 LSTo15 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 LSTo22 LSTo23 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 LSTo30 LSTo31 A17 A18 A19 B18 B19 B20 C18 C19 C20 D18 D19 D20 E17 E18 E19 E20 F18 F19 F20 G17 G18 G19 G20 H18 H19 H20 J17 J18 J19 J20 K17 K18 WAN_STi0 WAN_STi1 WAN_STi2 WAN_STi3 WAN_STi4 WAN_STi5 WAN_STi6 WAN_STi7 WAN_STi8 WAN_STi9 WAN_STi10 WAN_STi11 WAN_STi12 WAN_STi13 WAN_STi14 WAN_STi15 WAN_STi16 WAN_STi17 WAN_STi18 WAN_STi19 WAN_STi20 WAN_STi21 WAN_STi22 WAN_STi23 WAN_STi24 WAN_STi25 WAN_STi26 WAN_STi27 WAN_STi28 WAN_STi29 WAN_STi30 WAN_STi31 LCSTo0 LCSTo1 LCSTo2 LCSTo3 C17 C16 B16 A16 1 2 3 4 WAN_STo0 WAN_STo1 WAN_STo2 WAN_STo3 WAN_STo4 WAN_STo5 WAN_STo6 WAN_STo7 WAN_STo8 WAN_STo9 WAN_STo10 WAN_STo11 WAN_STo12 WAN_STo13 WAN_STo14 WAN_STo15 WAN_STo16 WAN_STo17 WAN_STo18 WAN_STo19 WAN_STo20 WAN_STo21 WAN_STo22 WAN_STo23 WAN_STo24 WAN_STo25 WAN_STo26 WAN_STo27 WAN_STo28 WAN_STo29 WAN_STo30 WAN_STo31 L18 L19 L20 M17 M18 M19 M20 N18 N19 N20 P17 P19 P20 R18 R19 R20 T18 T19 T20 U18 U19 U20 V17 V18 V19 V20 W18 W19 Y20 Y17 Y18 Y19 LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 LSTi16 LSTi17 LSTi18 LSTi19 LSTi20 LSTi21 LSTi22 LSTi23 LSTi24 LSTi25 LSTi26 LSTi27 LSTi28 LSTi29 LSTi30 LSTi31 Local streams 8 7 6 5 ODX B LSTo0 LSTo1 LSTo2 LSTo3 LSTo4 LSTo5 LSTo6 LSTo7 LSTo8 LSTo9 LSTo10 LSTo11 LSTo12 LSTo13 LSTo14 LSTo15 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 LSTo22 LSTo23 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 LSTo30 LSTo31 A17 A18 A19 B18 B19 B20 C18 C19 C20 D18 D19 D20 E17 E18 E19 E20 F18 F19 F20 G17 G18 G19 G20 H18 H19 H20 J17 J18 J19 J20 K17 K18 LCSTo0 LCSTo1 LCSTo2 LCSTo3 C17 C16 B16 A16 WAN_STi0 WAN_STi1 WAN_STi2 WAN_STi3 WAN_STi4 WAN_STi5 WAN_STi6 WAN_STi7 WAN_STi8 WAN_STi9 WAN_STi10 WAN_STi11 WAN_STi12 WAN_STi13 WAN_STi14 WAN_STi15 WAN_STi16 WAN_STi17 WAN_STi18 WAN_STi19 WAN_STi20 WAN_STi21 WAN_STi22 WAN_STi23 WAN_STi24 WAN_STi25 WAN_STi26 WAN_STi27 WAN_STi28 WAN_STi29 WAN_STi30 WAN_STi31 C 1 2 3 4 8 7 6 5 RN36 10k RN37 10k MT90869 MT90869 WAN_STo[0..31] WAN_STo[0..31] B WAN_CLKi[0..31] C9 A9 C11 A11 A12 D12 B14 D14 E15 B17 A18 A19 C19 A21 D19 D20 E20 D21 C24 E25 F25 G23 H25 J22 K25 K22 L22 L23 M23 R25 U25 W26 WAN_FRMi[0..31] C WAN_STi0 WAN_STi1 WAN_STi2 WAN_STi3 WAN_STi4 WAN_STi5 WAN_STi6 WAN_STi7 WAN_STi8 WAN_STi9 WAN_STi10 WAN_STi11 WAN_STi12 WAN_STi13 WAN_STi14 WAN_STi15 WAN_STi16 WAN_STi17 WAN_STi18 WAN_STi19 WAN_STi20 WAN_STi21 WAN_STi22 WAN_STi23 WAN_STi24 WAN_STi25 WAN_STi26 WAN_STi27 WAN_STi28 WAN_STi29 WAN_STi30 WAN_STi31 WAN_CLKi[0..31] J27 WAN_CLKO_FRMO WAN_FRMO WAN_CLKO A A Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : MT90880 WAN data streams Size B Document Number C385ACS29 Rev 1.0 C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Tuesday, May 28, 2002 Sheet 1 6 of 21 5 4 3 2 1 +3V3 +3V3 WAN_FRMi0 WAN_FRMi1 7 3 VTERM terminating voltage C227 R166 10k 100nF C226 + 1µF 8 TP45 Vterm U26 LT1809CS8 NC + V+ WAN_FRMi2 VTERM 6 SHDN 2 + V+ 4 1 C228 1µF WAN_FRMi3 WAN_FRMi[0..31] R165 10k J94 1 3 WAN_STo0 5 7 WAN_STo1 9 11 WAN_STo213 15 WAN_STo317 19 R225 0R 2 4 6 8 10 12 14 16 18 20 WAN_CLKi0 WAN_CLKi1 WAN_CLKi2 WAN_STi2 WAN_CLKi3 WAN_STi3 J93 R226 0R WAN_FRMO WAN_CLKO WAN_STo4 WAN_FRMi5 WAN_STo5 WAN_FRMi6 WAN_STo6 C WAN_FRMi7 WAN_STo7 J99 1 3 5 7 9 11 13 15 17 19 R227 0R RN82 47k RN84 47k RN86 47k RN88 47k RN90 47k RN92 47k RN94 47k RN96 47k VTERM WAN_STi[0..31] WAN_STo0 WAN_STo1 WAN_STo2 WAN_STo3 WAN_STo4 WAN_STo5 WAN_STo6 WAN_STo7 WAN_STo8 WAN_STo9 WAN_STo10 WAN_STo11 WAN_STo12 WAN_STo13 WAN_STo14 WAN_STo15 WAN_STo16 WAN_STo17 WAN_STo18 WAN_STo19 WAN_STo20 WAN_STo21 WAN_STo22 WAN_STo23 WAN_STo24 WAN_STo25 WAN_STo26 WAN_STo27 WAN_STo28 WAN_STo29 WAN_STo30 WAN_STo31 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 WAN_STo[0..31] LA header HDR4 1 3 WAN_STo12 5 WAN_FRMi13 7 WAN_STo13 9 WAN_FRMi14 11 WAN_STo1413 WAN_FRMi15 15 WAN_STo1517 19 J101 J100 C LA header R228 0R WAN_CLKi[0..31] +3V3 +3V3 1 3 WAN_STo16 5 WAN_FRMi17 7 WAN_STo17 9 WAN_FRMi18 11 WAN_STo1813 WAN_FRMi19 15 WAN_STo1917 19 J103 2 4 6 8 10 12 14 16 18 20 WAN_FRMi16 RN89 47k VTERM WAN_CLKi12 WAN_STi12 WAN_CLKi13 WAN_STi13 WAN_CLKi14 WAN_STi14 WAN_CLKi15 WAN_STi15 J98 HDR5 RN97 47k 2 4 6 8 10 12 14 16 18 20 1 WAN_FRMi[0..31] RN87 47k RN95 47k J95 WAN_FRMO RN85 47k RN93 47k WAN_CLKi10 WAN_STi10 WAN_CLKi11 WAN_STi11 WAN_CLKO RN83 47k RN91 47k D WAN_CLKi9 WAN_STi9 WAN_CLKi16 WAN_STi16 WAN_CLKi17 WAN_STi17 WAN_CLKi18 WAN_STi18 WAN_CLKi19 WAN_STi19 HDR7 J102 LA header +3V3 HDR6 1 3 WAN_STo20 5 WAN_FRMi21 7 WAN_STo21 9 WAN_FRMi22 11 WAN_STo2213 WAN_FRMi23 15 WAN_STo2317 19 J107 2 4 6 8 10 12 14 16 18 20 WAN_FRMi20 WAN_CLKi20 WAN_STi20 WAN_CLKi21 WAN_STi21 WAN_CLKi22 WAN_STi22 WAN_CLKi23 WAN_STi23 J106 1 3 WAN_STo24 5 WAN_FRMi25 7 WAN_STo25 9 WAN_FRMi26 11 WAN_STo2613 WAN_FRMi27 15 WAN_STo2717 19 J105 WAN_FRMi24 CODEC_nFOi 2 4 6 8 10 12 14 16 18 20 WAN_CLKi24 WAN_STi24 WAN_CLKi25 WAN_STi25 WAN_CLKi26 WAN_STi26 WAN_CLKi27 WAN_STi27 2 4 6 8 10 12 14 16 18 20 WAN_CLKi28 WAN_STi28 WAN_CLKi29 WAN_STi29 WAN_CLKi30 WAN_STi30 WAN_CLKi31 WAN_STi31 CODEC_nC4i LA header +3V3 HDR8 1 3 WAN_STo28 5 WAN_FRMi29 7 WAN_STo29 9 WAN_FRMi30 11 WAN_STo3013 WAN_FRMi31 15 WAN_STo3117 19 J109 WAN_FRMi28 LA header WAN_STo[0..31] B J104 J108 WAN_CLKi[0..31] WAN_STi[0..31] 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 WAN_CLKi8 WAN_STi8 +3V3 WAN_FRMi12 WAN_CLKi[0..31] 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 WAN_CLKi4 WAN_STi4 WAN_CLKi5 WAN_STi5 WAN_CLKi6 WAN_STi6 WAN_CLKi7 WAN_STi7 LA header TP43 TAG WAN_FRMi[0..31] B WAN_STi0 WAN_STi1 WAN_STi2 WAN_STi3 WAN_STi4 WAN_STi5 WAN_STi6 WAN_STi7 WAN_STi8 WAN_STi9 WAN_STi10 WAN_STi11 WAN_STi12 WAN_STi13 WAN_STi14 WAN_STi15 WAN_STi16 WAN_STi17 WAN_STi18 WAN_STi19 WAN_STi20 WAN_STi21 WAN_STi22 WAN_STi23 WAN_STi24 WAN_STi25 WAN_STi26 WAN_STi27 WAN_STi28 WAN_STi29 WAN_STi30 WAN_STi31 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 WAN_CLKi[0..31] HDR2 WAN_FRMi4 J97 TERM_2_GND WAN_CLKi[0..31] +3V3 1 3 WAN_STo8 5 WAN_FRMi9 7 WAN_STo9 9 WAN_FRMi10 11 WAN_STo1013 WAN_FRMi11 15 WAN_STo1117 19 J96 WAN_FRMi8 WAN_STi1 LA header 1 2 HDR3 WAN_STi0 WAN_FRMi[0..31] R164 10k D VTERM J92 J97 VCC Closed Open VCC/2 Closed Closed GND Open Closed (Default) +3V3 HDR1 J92 TERM_2_VCC WAN_FRMi[0..31] 1 2 CODEC_nC4i CODEC_nFOi LA header A A Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : WAN streams logic analyser connectors Size B Document Number C385ACS29 Rev 1.0 C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Tuesday, May 28, 2002 Sheet 1 7 of 21 5 4 3 2 1 U7C LSTi[0..31] LSTo[0..31] CSTi0 CSTi1 CSTi2 CSTi3 CSTi4 CSTi5 CSTi6 CSTi7 CSTi8 CSTi9 CSTi10 CSTi11 CSTi12 CSTi13 CSTi14 CSTi15 CSTi16 CSTi17 CSTi18 CSTi19 CSTi20 CSTi21 CSTi22 CSTi23 CSTi24 CSTi25 CSTi26 CSTi27 CSTi28 CSTi29 CSTi30 CSTi31 J28 LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 LSTo[0..31] D U7B U1B C M1 M3 N4 M4 K1 K3 J1 J2 H1 H2 K5 J4 J5 F2 F3 H5 G4 E3 G5 D3 F4 B2 D4 D5 B3 A3 B4 A4 C5 A5 C7 B6 LOC_STi0 LOC_STi1 LOC_STi2 LOC_STi3 LOC_STi4 LOC_STi5 LOC_STi6 LOC_STi7 LOC_STi8 LOC_STi9 LOC_STi10 LOC_STi11 LOC_STi12 LOC_STi13 LOC_STi14 LOC_STi15 LOC_STi16 LOC_STi17 LOC_STi18 LOC_STi19 LOC_STi20 LOC_STi21 LOC_STi22 LOC_STi23 LOC_STi24 LOC_STi25 LOC_STi26 LOC_STi27 LOC_STi28 LOC_STi29 LOC_STi30 LOC_STi31 LOC_STo0 LOC_STo1 LOC_STo2 LOC_STo3 LOC_STo4 LOC_STo5 LOC_STo6 LOC_STo7 LOC_STo8 LOC_STo9 LOC_STo10 LOC_STo11 LOC_STo12 LOC_STo13 LOC_STo14 LOC_STo15 LOC_STo16 LOC_STo17 LOC_STo18 LOC_STo19 LOC_STo20 LOC_STo21 LOC_STo22 LOC_STo23 LOC_STo24 LOC_STo25 LOC_STo26 LOC_STo27 LOC_STo28 LOC_STo29 LOC_STo30 LOC_STo31 N3 M2 P4 L2 L3 K2 L4 L5 K4 G1 H3 G2 F1 G3 E1 H4 D1 D2 C1 C2 B1 A1 E4 C3 A2 C4 D6 E7 B5 C6 D7 E8 FP40B FP80B FP160B C8 A6 D8 C40B C80B C160B B8 A7 B7 ODE A8 Local TDM LSTo0 LSTo1 LSTo2 LSTo3 LSTo4 LSTo5 LSTo6 LSTo7 LSTo8 LSTo9 LSTo10 LSTo11 LSTo12 LSTo13 LSTo14 LSTo15 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 LSTo22 LSTo23 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 LSTo30 LSTo31 LSTo0 LSTo1 LSTo2 LSTo3 LSTo4 LSTo5 LSTo6 LSTo7 LSTo8 LSTo9 LSTo10 LSTo11 LSTo12 LSTo13 LSTo14 LSTo15 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 LSTo22 LSTo23 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 LSTo30 LSTo31 Backplane streams MT90880 local clk + frm ODX C BSTo0 BSTo1 BSTo2 BSTo3 BSTo4 BSTo5 BSTo6 BSTo7 BSTo8 BSTo9 BSTo10 BSTo11 BSTo12 BSTo13 BSTo14 BSTo15 BSTo16 BSTo17 BSTo18 BSTo19 BSTo20 BSTo21 BSTo22 BSTo23 BSTo24 BSTo25 BSTo26 BSTo27 BSTo28 BSTo29 BSTo30 BSTo31 C5 B5 A5 C4 A4 A3 B1 B2 B3 C1 C2 D1 D2 D3 E1 E2 E3 E4 F1 F2 F3 G1 G2 G3 G4 H1 H2 H3 J1 J2 J3 J4 BCSTo0 BCSTo1 BCSTo2 BCSTo3 C14 A15 B15 C15 10k 3 2 1 Disable Open = Enable FPGA 3 2 1 J31 J30 LSTo8 LSTo9 LSTo10 LSTo11 LSTo12 LSTo13 LSTo14 LSTo15 J32 HEADER2x20 J33 LSTi16 LSTi17 LSTi18 LSTi19 LSTi20 LSTi21 LSTi22 LSTi23 J34 LSTi24 LSTi25 LSTi26 LSTi27 LSTi28 LSTi29 LSTi30 LSTi31 J39 FP4oB FP8oB (default) R31 0R DNF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 LSTo22 LSTo23 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 LSTi0 LSTi1 LSTi2 LSTi3 RN99 1 2 3 4 U7F J47 C12 A12 K2 K19 nODX_RST FPGA Disable J138 ODE C control C16o W13 C8o V13 FP16o W14 FP8o V14 RESET ODE BORS LORS Clocks U14 FP8i W12 C8i 1 2 3 4 5 6 LSTi4 LSTi5 LSTi6 LSTi7 1 2 3 4 LSTi8 LSTi9 LSTi10 LSTi11 1 2 3 4 RN103 Local ODX o/p ODX C 47k RN100 8 7 6 5 LSTi16 LSTi17 LSTi18 LSTi19 J40 47k 1 2 3 4 47k 8 7 6 5 LSTi20 LSTi21 LSTi22 LSTi23 1 2 3 4 8 7 6 5 LSTi24 LSTi25 LSTi26 LSTi27 1 2 3 4 47k A17 A18 A19 B18 B19 B20 C18 C19 C20 D18 D19 D20 E17 E18 E19 E20 F18 F19 F20 G17 G18 G19 G20 H18 H19 H20 J17 J18 J19 J20 K17 K18 LCSTo0 LCSTo1 LCSTo2 LCSTo3 C17 C16 B16 A16 CSTo0 CSTo1 CSTo2 CSTo3 CSTo4 CSTo5 CSTo6 CSTo7 CSTo8 CSTo9 CSTo10 CSTo11 CSTo12 CSTo13 CSTo14 CSTo15 CSTo16 CSTo17 CSTo18 CSTo19 CSTo20 CSTo21 CSTo22 CSTo23 CSTo24 CSTo25 CSTo26 CSTo27 CSTo28 CSTo29 CSTo30 CSTo31 MT90869 47k J38 CSTi0 CSTi1 CSTi2 CSTi3 CSTi4 CSTi5 CSTi6 CSTi7 J48 1 47k D C J37 CSTi8 CSTi9 CSTi10 CSTi11 CSTi12 CSTi13 CSTi14 CSTi15 8 7 6 5 RN104 ODX C CSTi[0..31] J43 8 7 6 5 RN102 Local streams LSTo0 LSTo1 LSTo2 LSTo3 LSTo4 LSTo5 LSTo6 LSTo7 LSTo8 LSTo9 LSTo10 LSTo11 LSTo12 LSTo13 LSTo14 LSTo15 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 LSTo22 LSTo23 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 LSTo30 LSTo31 J35 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 LSTo30 LSTo31 HEADER2x20 RN101 A LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 MT90869 MT90880_ODE J142 MT90880 ODE control ODE_C J29 J119 FP_SEL R32 R35 10k 1 2 3 LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 LSTi16 LSTi17 LSTi18 LSTi19 LSTi20 LSTi21 LSTi22 LSTi23 LSTi24 LSTi25 LSTi26 LSTi27 LSTi28 LSTi29 LSTi30 LSTi31 C8o_C B R34 10k BSTi0 BSTi1 BSTi2 BSTi3 BSTi4 BSTi5 BSTi6 BSTi7 BSTi8 BSTi9 BSTi10 BSTi11 BSTi12 BSTi13 BSTi14 BSTi15 BSTi16 BSTi17 BSTi18 BSTi19 BSTi20 BSTi21 BSTi22 BSTi23 BSTi24 BSTi25 BSTi26 BSTi27 BSTi28 BSTi29 BSTi30 BSTi31 J36 1 2 3 4 5 6 MT90880 +3V3 K3 L1 L2 L3 L4 M1 M2 M3 M4 N1 N2 P1 P2 P3 P4 R1 R2 R3 T1 T2 T3 T4 U1 W1 W2 W3 Y1 Y2 U5 V4 W4 Y4 LSTo0 LSTo1 LSTo2 LSTo3 LSTo4 LSTo5 LSTo6 LSTo7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 LSTi16 LSTi17 LSTi18 LSTi19 LSTi20 LSTi21 LSTi22 LSTi23 LSTi24 LSTi25 LSTi26 LSTi27 LSTi28 LSTi29 LSTi30 LSTi31 CSTo[0..31] LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 LSTi16 LSTi17 LSTi18 LSTi19 LSTi20 LSTi21 LSTi22 LSTi23 LSTi24 LSTi25 LSTi26 LSTi27 LSTi28 LSTi29 LSTi30 LSTi31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 L18 L19 L20 M17 M18 M19 M20 N18 N19 N20 P17 P19 P20 R18 R19 R20 T18 T19 T20 U18 U19 U20 V17 V18 V19 V20 W18 W19 Y20 Y17 Y18 Y19 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 TP35 TAG 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 CSTo0 CSTo1 CSTo2 CSTo3 CSTo4 CSTo5 CSTo6 CSTo7 J44 CSTo8 CSTo9 CSTo10 CSTo11 CSTo12 CSTo13 CSTo14 CSTo15 CSTi16 CSTi17 CSTi18 CSTi19 CSTi20 CSTi21 CSTi22 CSTi23 J41 CSTi24 CSTi25 CSTi26 CSTi27 CSTi28 CSTi29 CSTi30 CSTi31 J45 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 CSTo16 CSTo17 CSTo18 CSTo19 CSTo20 CSTo21 CSTo22 CSTo23 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 B J42 CSTo24 CSTo25 CSTo26 CSTo27 CSTo28 CSTo29 CSTo30 CSTo31 J46 HEADER2x20 J49 HEADER2x20 8 7 6 5 A RN105 LSTi12 LSTi13 LSTi14 LSTi15 MT90869 1 2 3 4 47k RN106 8 7 6 5 LSTi28 LSTi29 LSTi30 LSTi31 1 2 3 4 47k Zarlink Semiconductor 8 7 6 5 Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : ODX C (local) - Data streams & connectors Size B C8i_C Document Number C385ACS29 Rev 1.0 C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Tuesday, May 28, 2002 Sheet 1 8 of 21 5 4 3 2 1 U5B U6B CODEC_DSTo D C BSTi0 BSTi1 BSTi2 BSTi3 BSTi4 BSTi5 BSTi6 BSTi7 BSTi8 BSTi9 BSTi10 BSTi11 BSTi12 BSTi13 BSTi14 BSTi15 BSTi16 BSTi17 BSTi18 BSTi19 BSTi20 BSTi21 BSTi22 BSTi23 BSTi24 BSTi25 BSTi26 BSTi27 BSTi28 BSTi29 BSTi30 BSTi31 Backplane streams ODX A BSTo0 BSTo1 BSTo2 BSTo3 BSTo4 BSTo5 BSTo6 BSTo7 BSTo8 BSTo9 BSTo10 BSTo11 BSTo12 BSTo13 BSTo14 BSTo15 BSTo16 BSTo17 BSTo18 BSTo19 BSTo20 BSTo21 BSTo22 BSTo23 BSTo24 BSTo25 BSTo26 BSTo27 BSTo28 BSTo29 BSTo30 BSTo31 C5 B5 A5 C4 A4 A3 B1 B2 B3 C1 C2 D1 D2 D3 E1 E2 E3 E4 F1 F2 F3 G1 G2 G3 G4 H1 H2 H3 J1 J2 J3 J4 BCSTo0 BCSTo1 BCSTo2 BCSTo3 C14 A15 B15 C15 ASTo0 ASTo1 ASTo2 ASTo3 ASTo4 ASTo5 ASTo6 ASTo7 ASTo8 ASTo9 ASTo10 ASTo11 ASTo12 ASTo13 ASTo14 ASTo15 ASTo16 ASTo17 ASTo18 ASTo19 ASTo20 ASTo21 ASTo22 ASTo23 ASTo24 ASTo25 ASTo26 ASTo27 ASTo28 ASTo29 ASTo30 ASTo31 K3 L1 L2 L3 L4 M1 M2 M3 M4 N1 N2 P1 P2 P3 P4 R1 R2 R3 T1 T2 T3 T4 U1 W1 W2 W3 Y1 Y2 U5 V4 W4 Y4 BSTi0 BSTi1 BSTi2 BSTi3 BSTi4 BSTi5 BSTi6 BSTi7 BSTi8 BSTi9 BSTi10 BSTi11 BSTi12 BSTi13 BSTi14 BSTi15 BSTi16 BSTi17 BSTi18 BSTi19 BSTi20 BSTi21 BSTi22 BSTi23 BSTi24 BSTi25 BSTi26 BSTi27 BSTi28 BSTi29 BSTi30 BSTi31 Backplane streams ODX B BSTo0 BSTo1 BSTo2 BSTo3 BSTo4 BSTo5 BSTo6 BSTo7 BSTo8 BSTo9 BSTo10 BSTo11 BSTo12 BSTo13 BSTo14 BSTo15 BSTo16 BSTo17 BSTo18 BSTo19 BSTo20 BSTo21 BSTo22 BSTo23 BSTo24 BSTo25 BSTo26 BSTo27 BSTo28 BSTo29 BSTo30 BSTo31 BSTo0 BSTo1 BSTo2 BSTo3 BSTo4 BSTo5 BSTo6 BSTo7 BSTo8 BSTo9 BSTo10 BSTo11 BSTo12 BSTo13 BSTo14 BSTo15 BSTo16 BSTo17 BSTo18 BSTo19 BSTo20 BSTo21 BSTo22 BSTo23 BSTo24 BSTo25 BSTo26 BSTo27 BSTo28 BSTo29 BSTo30 BSTo31 C5 B5 A5 C4 A4 A3 B1 B2 B3 C1 C2 D1 D2 D3 E1 E2 E3 E4 F1 F2 F3 G1 G2 G3 G4 H1 H2 H3 J1 J2 J3 J4 BCSTo0 BCSTo1 BCSTo2 BCSTo3 C14 A15 B15 C15 D C BSTo[0..31] K3 L1 L2 L3 L4 M1 M2 M3 M4 N1 N2 P1 P2 P3 P4 R1 R2 R3 T1 T2 T3 T4 U1 W1 W2 W3 Y1 Y2 U5 V4 W4 Y4 BSTi0 BSTi1 BSTi2 BSTi3 BSTi4 BSTi5 BSTi6 BSTi7 BSTi8 BSTi9 BSTi10 BSTi11 BSTi12 BSTi13 BSTi14 BSTi15 BSTi16 BSTi17 BSTi18 BSTi19 BSTi20 BSTi21 BSTi22 BSTi23 BSTi24 BSTi25 BSTi26 BSTi27 BSTi28 BSTi29 BSTi30 BSTi31 ASTo[0..31] ASTi0 ASTi1 ASTi2 ASTi3 ASTi4 ASTi5 ASTi6 ASTi7 ASTi8 ASTi9 ASTi10 ASTi11 ASTi12 ASTi13 ASTi14 ASTi15 ASTi16 ASTi17 ASTi18 ASTi19 ASTi20 ASTi21 ASTi22 ASTi23 ASTi24 ASTi25 ASTi26 ASTi27 ASTi28 ASTi29 ASTi30 ASTi31 CODEC_DSTi MT90869 MT90869 BSTi[0..31] ASTi[0..31] J7 BSTi16 BSTi17 BSTi18 BSTi19 BSTi20 BSTi21 BSTi22 BSTi23 J8 B ASTi16 ASTi17 ASTi18 ASTi19 ASTi20 ASTi21 ASTi22 ASTi23 J10 ASTi0 ASTi1 ASTi2 ASTi3 ASTi4 ASTi5 ASTi6 ASTi7 J17 ASTi8 ASTi9 ASTi10 ASTi11 ASTi12 ASTi13 ASTi14 ASTi15 J25 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 ASTo0 ASTo1 ASTo2 ASTo3 ASTo4 ASTo5 ASTo6 ASTo7 J13 ASTi24 ASTi25 ASTi26 ASTi27 ASTi28 ASTi29 ASTi30 ASTi31 J18 ASTo8 ASTo9 ASTo10 ASTo11 ASTo12 ASTo13 ASTo14 ASTo15 J21 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 ASTo16 ASTo17 ASTo18 ASTo19 ASTo20 ASTo21 ASTo22 ASTo23 J9 BSTi0 BSTi1 BSTi2 BSTi3 BSTi4 BSTi5 BSTi6 BSTi7 J14 ASTo24 ASTo25 ASTo26 ASTo27 ASTo28 ASTo29 ASTo30 ASTo31 J15 BSTi8 BSTi9 BSTi10 BSTi11 BSTi12 BSTi13 BSTi14 BSTi15 J22 HEADER2x20 J23 J26 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 BSTo0 BSTo1 BSTo2 BSTo3 BSTo4 BSTo5 BSTo6 BSTo7 J11 BSTi24 BSTi25 BSTi26 BSTi27 BSTi28 BSTi29 BSTi30 BSTi31 J16 BSTo8 BSTo9 BSTo10 BSTo11 BSTo12 BSTo13 BSTo14 BSTo15 J19 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 BSTo16 BSTo17 BSTo18 BSTo19 BSTo20 BSTo21 BSTo22 BSTo23 B J12 BSTo24 BSTo25 BSTo26 BSTo27 BSTo28 BSTo29 BSTo30 BSTo31 J20 HEADER2x20 J24 HEADER2x20 HEADER2x20 A A Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : ODX A & B (WAN) backplane headers Size B Document Number C385ACS29 Rev 1.0 C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Tuesday, May 28, 2002 Sheet 1 9 of 21 5 4 +1V8 3 2 +3V3 U6A LD[15..0] +3V3 VDD_PLL 100nF C66 100nF C71 100nF C65 100nF C70 100nF C64 U12 100nF C78 nCS_ODXA nDS ODX_RnW B11 A11 C11 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 D5 C6 A6 D7 C7 B7 C8 B8 A8 D9 B9 A9 D10 C10 A10 100nF C83 100nF C77 100nF C82 100nF C76 100nF C81 100nF C75 100nF C80 + 10µF C74 100nF C73 10µF C72 + U17 U13 U11 U8 U4 N17 N4 M12 M11 M10 M9 L12 L11 L10 L9 100nF C79 C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RN38 10k U6D VDD_CORE_ODXA ODX A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 100nF C69 L1 10µH Power pins A1 D4 D8 D13 D17 H4 H17 J9 J10 J11 J12 K9 K10 K11 K12 100nF C63 R28 0R 100nF C68 + 10µF C62 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO U6E +1V8 100nF C67 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 VDD_IO_ODXA D VDD_CORE_ODXA VDD_IO_ODXA K1 N3 V1 V5 Y7 Y11 Y14 U16 T17 P18 K20 D14 B12 A7 B4 1 CS D0 DS D1 R/W D2 Processor D3 interface D4 A0 D5 A1 D6 A2 D7 A3 D8 A4 D9 A5 D10 A6 D11 A7 D12 D13 A8 A9 D14 A10 D15 A11 ODX A A12 A13 A14 DTA LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 V10 Y9 W9 V9 U9 Y8 W8 V8 W7 V7 U7 Y6 W6 V6 Y5 W5 RN42 10k RN44 10k 8 7 6 5 1 2 3 4 8 7 6 5 8 7 6 5 1 2 3 4 1 2 3 4 D12 A14 B13 C13 B14 TMS TCK TDI TDO TRST Y12 Y13 NC NC A2 A20 B6 B10 B17 C3 C9 D16 IC IC IC IC IC IC IC IC TP48 U2 U3 V2 V3 V11 V12 V15 V16 W10 W11 W15 W16 W17 W20 Y3 Y10 Y15 Y16 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 RN39 10k D RN40 10k RN41 10k RN43 10k RN45 10k MT90869 1 A13 JTAG ODX A IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC GND TAG nDTA_ODXA C MT90869 MT90869 +1V8 +3V3 U5A LD[15..0] +3V3 A 100nF C88 nCS_ODXB nDS 100nF C93 100nF C87 100nF C92 100nF C86 100nF C91 ODX_RnW 100nF C100 100nF C105 100nF C99 100nF C104 100nF C98 100nF C103 100nF C97 100nF C102 + 10µF C96 + 100nF C101 U17 U13 U11 U8 U4 N17 N4 M12 M11 M10 M9 L12 L11 L10 L9 100nF C95 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 10µF C94 ODX B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RN46 10k U5D VDD_CORE_ODXB Power pins A1 D4 D8 D13 D17 H4 H17 J9 J10 J11 J12 K9 K10 K11 K12 100nF C85 U12 L2 10µH 100nF C90 VDD_PLL + R29 0R 10µF C84 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO U5E +1V8 100nF C89 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 VDD_IO_ODXB B VDD_CORE_ODXB VDD_IO_ODXB K1 N3 V1 V5 Y7 Y11 Y14 U16 T17 P18 K20 D14 B12 A7 B4 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 B11 A11 C11 D5 C6 A6 D7 C7 B7 C8 B8 A8 D9 B9 A9 D10 C10 A10 D0 CS D1 DS R/W D2 Processor D3 interface D4 A0 D5 A1 D6 A2 D7 A3 D8 A4 D9 D10 A5 A6 D11 A7 D12 A8 D13 A9 D14 D15 A10 A11 A12 ODX B A13 A14 DTA V10 Y9 W9 V9 U9 Y8 W8 V8 W7 V7 U7 Y6 W6 V6 Y5 W5 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 RN50 10k RN52 10k 8 7 6 5 8 7 6 5 8 7 6 5 1 2 3 4 1 2 3 4 1 2 3 4 D12 A14 B13 C13 B14 TMS TCK TDI TDO TRST Y12 Y13 NC NC A2 A20 B6 B10 B17 C3 C9 D16 IC IC IC IC IC IC IC IC JTAG ODX B IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC U2 U3 V2 V3 V11 V12 V15 V16 W10 W11 W15 W16 W17 W20 Y3 Y10 Y15 Y16 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 RN47 10k RN48 10k B RN49 10k RN51 10k RN53 10k MT90869 A13 nDTA_ODXB MT90869 A LA[31..1] Zarlink Semiconductor Cheney Manor Swindon UK Title MT90869 MT90880 Lab Evaluation Board V1R1 : ODX A & ODX B (WAN) - Pwr, ctrl & JTAG Size B C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Document Number Rev C385ACS29 Tuesday, May 28, 2002 1.0 Sheet 1 10 of 21 5 4 3 2 1 D D +1V8 +3V3 LD[15..0] +3V3 B 100nF C108 100nF C109 100nF C110 100nF C113 100nF C114 100nF C115 B11 A11 C11 nCS_ODXC nDS ODX_RnW 100nF C122 100nF C127 U17 U13 U11 U8 U4 N17 N4 M12 M11 M10 M9 L12 L11 L10 L9 100nF C121 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 100nF C126 ODX C 100nF C120 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 100nF C125 A1 D4 D8 D13 D17 H4 H17 J9 J10 J11 J12 K9 K10 K11 K12 + 100nF C119 + Power pins RN54 10k U7D VDD_CORE_ODXC 100nF C124 U12 100nF C107 L3 10µH 100nF C112 R30 0R 10µF C118 VDD_PLL D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 100nF C123 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO 100nF C117 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE 10µF C116 K1 N3 V1 V5 Y7 Y11 Y14 U16 T17 P18 K20 D14 B12 A7 B4 VDD_IO_ODXC C VDD_CORE_ODXC + 10µF C106 U7A 100nF C111 VDD_IO_ODXC +1V8 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 D5 C6 A6 D7 C7 B7 C8 B8 A8 D9 B9 A9 D10 C10 A10 CS D0 DS D1 R/W D2 Processor D3 interface D4 A0 D5 A1 D6 A2 D7 A3 D8 A4 D9 A5 D10 A6 D11 A7 D12 D13 A8 A9 D14 A10 D15 A11 A12 ODX C A13 A14 DTA V10 Y9 W9 V9 U9 Y8 W8 V8 W7 V7 U7 Y6 W6 V6 Y5 W5 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 RN58 10k RN60 10k U7E 8 7 6 5 8 7 6 5 8 7 6 5 1 2 3 4 1 2 3 4 1 2 3 4 D12 A14 B13 C13 B14 TMS TCK TDI TDO TRST Y12 Y13 NC NC A2 A20 B6 B10 B17 C3 C9 D16 JTAG IC IC IC IC IC IC IC IC ODX C IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC U2 U3 V2 V3 V11 V12 V15 V16 W10 W11 W15 W16 W17 W20 Y3 Y10 Y15 Y16 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 RN55 10k RN56 10k C RN57 10k RN59 10k RN61 10k MT90869 A13 nDTA_ODXC MT90869 B LA[31..1] MT90869 A A Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : ODX C (local) power, control & JTAG Size B Document Number C385ACS29 Rev 1.0 C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Tuesday, May 28, 2002 Sheet 1 11 of 21 5 RN31 10k 1 2 3 4 nMON nPRES2 RN34 10k PCI_TCK GND C48 10µF + +5V +5V nPCI_INTB nPCI_INTD nPRES1 C50 10nF nPRES2 C C53 C55 10µF B C57 10µF C58 10µF 8 7 6 5 nREQ3 nREQ4 nREQ5 nREQ6 1 2 3 4 nSBO R14 4k7 SDONE R15 4k7 nACK64 1 nREQ2 2 3 4 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# PCI_CLK0 8 7 6 5 C47 10µF +12V P9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 8 7 6 5 RN35 10k 4k7 nPCI_INTA -12V 8 7 6 5 RN33 10k 1 2 3 4 R13 8 7 6 5 -12V nPCI_INTB 1 nPCI_INTC 2 nPCI_INTD 3 4 RN32 10k 8 7 6 5 nBUSMODE4 1 nBUSMODE3 2 PCI_TCK 3 4 8 7 6 5 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED VIO RESERVED A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 R16 4k7 +5V nPCI_INTA nPCI_INTC +5V +3V3 RESERVED RESERVED GND RST# CLK +3V3 GND GNT# REQ# GND +3V3 PHE# AD31 AD30 AD29 +3V3 GND AD28 AD27 AD26 AD25 GND +3V3 AD24 C/BE3# IDSEL AD23 +3V3 GND AD22 PCI V2.2 AD21 AD20 AD19 GND DEV 2 +3V3 AD18 AD17 AD16 C/BE2# +3V3 GND FRAME# IRDY# GND +3V3 TRDY# DEVSEL# GND GND STOP# LOCK# +3V3 PERR# RESERVED +3V3 RESERVED SERR# GND +3V3 PAR C/BE1# AD15 AD14 +3V3 GND AD13 AD12 AD11 AD10 GND M66EN AD9 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 C54 + 10µF nPCI_RST +3V3 nGNT2 GND PCI_AD30 +3V3 PCI_AD28 PCI_AD26 GND PCI_AD24 +3V3 PCI_AD22 PCI_AD20 GND PCI_AD18 PCI_AD16 +3V3 PCI_FRAME GND PCI_TRDY GND PCI_STOP +3V3 SDONE nSBO GND PCI_PAR PCI_AD15 +3V3 PCI_AD13 PCI_AD11 GND PCI_AD9 A C60 10µF B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 AD8 AD7 +3V3 AD5 AD3 GND AD1 +3V3 ACK64# +5V +5V C/BE0# +3V3 AD6 AD4 GND AD2 AD0 +3V3 REQ64# +5V +5V A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 PCI_C-BE0 +3V3 PCI_AD6 PCI_AD4 GND PCI_AD2 PCI_AD0 +3V3 nREQ64 +5V +5V TCK GND INTB# PRESENT# INTD# GND PCI_CLK1 GND REQ0# PCI_VIO AD28 AD25 GND AD22 AD19 PCI_VIO FRAME# GND DEVSEL# GND PCI_RSV PAR PCI_VIO AD12 AD9 GND AD6 AD4 PCI_VIO AD2 AD0 GND -12V INTA# INTC# +5V PCI_RSV 3V3AUX GND GNT# +5V AD31 AD27 GND C/BE3# AD21 +5V AD17 GND IRDY# +5V LOCK# PCI_RSV GND AD15 AD11 +5V C/BE0# AD5 GND AD3 AD1 +5V REQ64# 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 nPCI_INTA nPCI_INTC +5V GND +3V3 GND nBUSMODE2 nPCI_RST +3V3 +5V PCI_AD31 PCI_AD27 GND PCI_C-BE3 PCI_AD21 +5V PCI_AD17 GND PCI_IRDY +5V PCI_LOCK PCI_AD30 GND PCI_AD24 +3V3 PCI_AD18 PCI_AD16 GND PCI_TRDY GND PCI_PERR +3V3 PCI_C-BE1 PCI_AD14 PCI_M66EN PCI_AD8 PCI_AD7 +3V3 GND PCI_AD15 PCI_AD11 +5V PCI_C-BE0 PCI_AD5 GND PCI_AD3 PCI_AD1 +5V nREQ64 GND nACK64 GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 + C51 10µF R18 1 DEV 3 +12V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 +12V TRST# TMS TDO TDI GND GND PCI_RSV PCI_RSV PCI_RSV BUSMODE2# 3V3 RST# BUSMODE3# 3V3 BUSMODE4# PME# GND AD30 AD29 GND AD26 AD24 3V3 IDSEL AD23 3V3 AD20 AD18 GND AD16 C/BE2# GND IDSELB TRDY# 3V3 GND STOP# PERR# GND 3V3 SERR# C/BE1# GND AD14 AD13 M66EN AD10 AD8 3V3 AD7 REQB# 3V3 GNTB# PMC_RSV GND PMC_RSV EREADY GND RESETOUT# ACK64# 3V3 GND MONARCH# GND GND +3V3 +3V3 nBUSMODE3 nBUSMODE4 GND PCI_AD29 PCI_AD26 +3V3 PCI_AD23 PCI_AD20 GND PCI_C-BE2 C56 + 10µF C59 + 10µF nPCI_RST PCI_CLK2 +5V GND GND GND R17 51R +3V3 nMON C52 + 10µF +3V3 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 GND C/BE7# C/BE5# GND PAR64 AD62 GND AD60 AD58 GND AD56 AD54 GND AD52 AD50 GND AD48 AD46 GND AD44 AD42 GND AD40 AD38 GND AD36 AD34 GND AD32 PCI_RSV GND PCI_RSV GND GND D GND GND GND GND GND GND GND GND C PCI_AD20 PMC Jn3 +3V3 P3 R2 R1 T1 P2 M4 N3 P1 M3 L4 N1 M1 L3 L2 L1 K3 F1 F2 E1 F3 D1 E3 D2 C1 C2 A1 B1 B2 C3 D4 A2 C4 C5 J1 nPCI_INTA B4 U1D AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PLX PCI 9056 (C Mode) DEV 1 RST# PCLK INTA# C/BE0# C/BE1# C/BE2# C/BE3# N2 K2 G3 E4 FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL PERR# SERR# LOCK# PAR G2 G1 H4 H2 H3 D3 J2 J3 H1 K1 PCI_FRAME PCI_IRDY PCI_TRDY PCI_STOP PCI_DEVSEL REQ0#/GNT# REQ1# REQ2# REQ3# REQ4# REQ5# REQ6# D5 P4 R3 P5 T4 N6 R6 nREQ0 nREQ1 nREQ2 nREQ3 nREQ4 nREQ5 nREQ6 GNT0#/REQ# GNT1# GNT2# GNT3# GNT4# GNT5# GNT6# A3 T2 T3 N5 R4 R5 T5 nGNT0 nGNT1 nGNT2 nGNT3 PME# A6 BD_SEL# CPCISW ENUM# LEDon# PCI9056-PBGA256 R20 10k PCI_C-BE0 PCI_C-BE1 PCI_C-BE2 PCI_C-BE3 B6 T6 P6 N7 nPCI_RST PCI_CLK3 PCI_AD17 PCI_C-BE0 PCI_C-BE1 PCI_C-BE2 PCI_C-BE3 R21 51R PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_PERR PCI_SERR PCI_LOCK PCI_PAR PCI_PERR PCI_SERR R22 51R AE19 AF20 AC19 AD19 PCI_RST# PCI_CLK# PCI_REQ# PCI_GNT# W24 Y23 AB23 AE22 PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# AC25 AE25 AA23 AF26 AC24 AE26 AB20 AD26 AB24 PCI_PAR PCI_FRAME# PCI_TRDY# PCI_IRDY# PCI_STOP# PCI_DEVSEL# PCI_IDSEL# PCI_PERR# PCI_SERR# AF19 Y22 Y25 PCI_INTA# PCI_LOCK# PCI_M66EN nPCI_INTA PCI_LOCK PCI_AD16 +3V3 DEV 0 R23 10k PCI interface J5 M66_AUTO MT90880 PCI_M66EN R24 1k PCI_M66EN T26 T25 R23 T24 T23 V25 U23 V24 AA26 Y24 AA25 AB26 AA24 W23 AB25 AC26 AC23 AD24 AC22 AE24 AC21 AE23 AD22 AF23 AD21 AF22 AE21 AD20 AC20 AF21 AB19 AE20 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 B +3V3 R26 1k A 1k J6 BKM66EN Zarlink Semiconductor A 66MHz operation J5 J6 Auto (PCI_M66EN) Fit Open Force 33MHz Open A Force 66MHz Open B B 2 Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : PCI bus interfaces and connectors Size B Date: 3 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 +3V3 R25 1k R27 4 +3V3 PMC Jn2 C 2001, 2002 Copyright Zarlink Semiconductor 5 GND PCI_RSV GND C/BE6# C/BE4# PCI_VIO AD63 AD61 GND AD59 AD57 PCI_VIO AD55 AD53 GND AD51 AD49 GND AD47 AD45 PCI_VIO AD43 AD41 GND AD39 AD37 GND AD35 AD33 PCI_VIO PCI_RSV PCI_RSV GND PCI_AD19 PMC Jn1 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 +3V3 +3V3 PCI_STOP GND PCI_SERR GND PCI_AD13 PCI_AD10 +3V3 nREQ3 nGNT3 GND EREADY U2A R19 51R C46 + 10µFGND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 51R PCI_AD18 C61 + 10µF + 1 GND 3 5 nPRES1 7 nPCI_INTD 9 GND 11 13 GND 15 17 +3V3 19 PCI_AD28 21 PCI_AD25 23 GND 25 PCI_AD22 27 PCI_AD19 29 +3V3 31 PCI_FRAME 33 GND 35 PCI_DEVSEL 37 GND 39 41 PCI_PAR 43 +3V3 45 PCI_AD12 47 PCI_AD9 49 GND 51 PCI_AD6 53 PCI_AD4 55 +3V3 57 PCI_AD2 59 PCI_AD0 61 GND 63 nPCI_RST PCI connector - 3V3 orientation PCI_AD8 PCI_AD7 +3V3 PCI_AD5 PCI_AD3 GND PCI_AD1 +3V3 nACK64 +5V +5V + C49 + 10µF 10nF B14 GND B15 B16 PCI_CLK1 GND B17 nREQ2 B18 +3V3 B19 PCI_AD31 B20 PCI_AD29 + B21 GND B22 PCI_AD27 B23 PCI_AD25 B24 +3V3 B25 PCI_C-BE3 B26 PCI_AD23 B27 GND B28 PCI_AD21 B29 PCI_AD19 B30 +3V3 B31 PCI_AD17 B32 PCI_C-BE2 B33 GND B34 PCI_IRDY B35 +3V3 B36 PCI_DEVSEL B37 GND + B38 PCI_LOCK B39 PCI_PERR B40 +3V3 B41 PCI_SERR B42 +3V3 B43 PCI_C-BE1 B44 PCI_AD14 B45 GND B46 PCI_AD12 B47 PCI_AD10 + B48 PCI_M66EN B49 2 1 2 3 nREQ64 1 nPRES1 2 EREADY 3 nBUSMODE2 4 8 7 6 5 3 +3V3 RN30 10k 1 2 D PCI_STOP PCI_SERR PCI_PERR PCI_LOCK +3V3 RN29 10k PCI_AD[31..0] PCI_FRAME 1 PCI_TRDY 2 PCI_IRDY 3 PCI_DEVSEL 4 4 +3V3 RN28 10k Document Number C385ACS29 Tuesday, May 28, 2002 Rev 1.0 Sheet 1 12 of 21 5 4 3 2 1 +3V3 +2V5 PLX_VCORE PLX_VRING +3V3 PLX_VIO C7 5 1 2 3 4 1 C45 100nF EN O/P GND 2 2 D Q 5 Q 6 12 D Q 9 3 CLK 11 CLK Q 8 1 4 13 10 CLR SD CLR SD +2V5 N4 M2 E2 B3 PLX_VIO +3V3 + *U51A NC7WZ17P6 1 3 5 J3 U4A 74LCX74 2 4 6 1 2 3 4 Local bus oscillator frequency select Fit one jumper only 6 TP3 Test point *U51B LCLK LCLK 4 R2* 22k 1. All V1R0 and V1R1 boards up to and including S/N 0012 were fitted with PCI 9056-AA66BES devices in position U2. The IDDQEN# line (B7) of the -AA66 silicon is wired directly to +3V3. V1R1 boards from S/N 0013 were fitted with -AD66 versions of the PCI9056 mounted on a sub-board together with the components marked *. This additional logic toggles the IDDQEN# line at power-up in accordance with the PCI9056 ’Blue Book’ revisions 0.91 1 C2* 1000nF C1* 100nF R3* 33k A 3 Zarlink Semiconductor LCLK_SEL Swindon UK MT90880 Lab Evaluation Board V1R1 : PCI to local (control) bus interface Size B C 2001, 2002 Copyright Zarlink Semiconductor Date: 4 Cheney Manor Title NC7WZ17P6 5-6 : XT1 3-4 : XT1/2 1-2 : XT1 / 4 U4B 74LCX74 5 VIO VIO VIO VIO B RN98 10k RN27 10k 3 N9 K13 K4 F13 F4 D9 + 8 7 6 5 3V3 +VS VCORE VCORE VCORE VCORE VCORE VCORE PLX_VCORE +3V3 +3V3 4 R11 3k3 + RN26 10k 3V3 A 93LC56B/P (Socketted) RN25 10k nLBE0 nLBE1 nLBE2 nLBE3 LA1 +3V3 XT1 CFPS-73 16.00MHz PLX_VRING 100nF C15 PMEREQ# 4 100nF C35 D7 A7 D8 DO GND 100nF C44 2.5VAUX CARD_VAUX PRESENT_DET CS 100nF C14 B5 A5 D6 C6 A4 CLK 1 C 100nF C33 TCK TMS TDI TRST# TDO 2 C8 100nF 100nF C43 B9 DI 100nF C13 CCS# 8 3V3 100nF C32 A15 B15 B7 B12 U3 3 +3V3 100nF C12 D16 R220 330R 100nF C31 LCLK MODE1 MODE0 IDDQEN# HOSTEN# RN22 10k PCI9056-PBGA256 100nF C11 N14 R16 P15 T16 +3V3 8 7 6 5 (C Mode) 100nF C30 LBE0# LBE1# LBE2# LBE3# nLRESET 1 2 3 4 VRING VRING VRING VRING VRING VRING VRING VRING VRING VRING VRING VRING VRING A8 B8 C8 1 RN19 10k PLX PCI 9056 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS EECS EESK EEDI/DO U37A 74LCX00 3 ODX_RnW 2 100nF C42 LA29 A10 C10 C9 B10 8 7 6 5 100nF C41 B DREQ0# DREQ1# DACK0# DACK1# +3V3 1 2 3 4 100nF C10 R201 10k LA31 LA30 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 D11 A11 C13 A9 A13 B13 E13 A12 D10 TP2 Test point 0R 10µF C29 3V3 P7 R7 T7 N8 P8 R8 T8 T9 R9 P9 T10 R10 P10 T11 N10 P11 R11 T12 R12 T13 N11 P12 T14 R13 N12 P13 T15 R14 R15 N13 LRESET# USERi/LLOCKi# LSERR# BIGEND# BREQi BREQo BTERM# DMPAF/EOT# USERo/LLOCKo# TP1 R7 D M12 M11 M9 M6 M5 L12 L11 L10 L9 L8 L7 L6 L5 K11 K10 K9 K8 K7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 100nF C40 LA31 LA30 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA[31..1] A16 B14 C11 B11 nLADS nLBLAST nLWR nLREADY VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 10µF C39 RN24 10k LHOLD LHOLDA LINTi# LINTo# E5 E6 E9 E11 E12 F5 F6 F7 F8 F9 F10 F11 F12 G4 G6 G7 G8 G9 G10 G11 G13 H6 H7 H8 H9 H10 H11 J4 J5 J6 J7 J8 J9 J10 J11 J13 K6 RN23 10k (C Mode) D12 A14 P14 C15 C12 RN18 10k 10µF C9 C PLX PCI 9056 ADS# BLAST# LW/R# READY# WAIT# U2C R6 1k 8 7 6 5 8 7 6 5 RN21 10k DP0 DP1 DP2 DP3 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RN20 10k LD0/LAD0 LD1/LAD1 LD2/LAD2 LD3/LAD3 LD4/LAD4 LD5/LAD5 LD6/LAD6 LD7/LAD7 LD8/LAD8 LD9/LAD9 LD10/LAD10 LD11/LAD11 LD12/LAD12 LD13/LAD13 LD14/LAD14 LD15/LAD15 LD16/LAD16 LD17/LAD17 LD18/LAD18 LD19/LAD19 LD20/LAD20 LD21/LAD21 LD22/LAD22 LD23/LAD23 LD24/LAD24 LD25/LAD25 LD26/LAD26 LD27/LAD27 LD28/LAD28 LD29/LAD29 LD30/LAD30 LD31/LAD31 D14 B16 C14 D13 8 7 6 5 D C16 E14 D15 E15 F14 F15 E16 F16 G14 G15 G16 H13 H14 H15 H16 J16 J15 J14 K16 K15 K14 L16 M16 L15 L14 M15 N16 L13 M14 N15 M13 P16 1 2 3 4 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 +3V3 8 7 6 5 LD[15..0] PCI 9056--AD66BES E7 E8 E10 G5 G12 H5 H12 J12 K5 K12 M7 M8 M10 +3V3 U2B LD[15..0] 3 2 Document Number Rev C385ACS29 Tuesday, May 28, 2002 1.0 Sheet 1 13 of 21 3 2 VCCIO_FPGA LA4 LA3 LA2 4 5 10 19 20 21 nLREADY nLBLAST R62 10k 202 nFPGA_RST LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 ld0 ld1 ld2 ld3 ld4 ld5 ld6 ld7 ld8 ld9 ld10 ld11 ld12 ld13 ld14 ld15 Dev_OE Init_Done 178 135 DTA_cs0_n DTA_cs1_n DTA_cs2_n 158 208 180 Altera-EPF6016AQC208-1 la31 la30 la29 LD[15..0] +3V3 VCCINT_FPGA 1 2 3 8 7 6 5 8 26 44 9 27 45 63 79 96 112 131 149 166 183 200 VCCINT VCCINT VCCINT 188 207 187 185 190 193 184 181 80 150 77 46 6 reset_n 41 40 39 38 37 36 35 34 33 32 31 30 29 42 23 22 RN65 1k dclk data0 nStatus Conf_done nConfig msel nCE 199 182 165 147 132 129 128 110 95 78 62 43 25 7 C la3 la2 la1 ready_n blast_n decode_en_n 1 3 5 7 9 DCLK CONF_DONE nCONFIG nSTATUS Data0 ByteBlaster MV 10-Pin Male 0.1" pitch header nCS_ODXA nCS_ODXB nCS_ODXC 1 2 3 4 R265 220R INIT_DONE LED2 0R 0R 0R 0R 0R 0R 0R 0R 0R R194 R195 R196 R197 0R 0R 0R 0R FPGA init done R68 220R LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA31 LA30 LA29 Altera-EPF6016AQC208-1 100nF C168 100nF C167 100nF C166 100nF C165 100nF C164 100nF C163 100nF C162 100nF C161 100nF C160 100nF C159 100nF C158 100nF C177 100nF C176 100nF C175 100nF C174 100nF C173 100nF C172 100nF C171 100nF C170 VCCINT_FPGA 10µF C169 R63 100k VCC2 VCC1 N/C GND 8 7 6 5 DIL 8 - socketted F1B VCCIO_FPGA 100nF C157 DATA DCLK OE nCS FPGA_CLK_EN FPGA_CLK_SEL SPI_DEVSEL MT90880_ODE Do Not Fit : R67, R69, R70, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197 10µF C156 1 2 3 4 C LA18 LA17 LA16 R66 0R R188 R189 R190 R67 R191 R192 R193 R69 R70 Open all switches when using ByteBlaster cable.Remove cable and close switches when EPC1441 is fitted Default population - + 8 7 6 5 Altera-EPC1441 nDTA_ODXA nDTA_ODXB nDTA_ODXC R65 0R +3V3 U10 +3V3 R64 0R D +3V3 SW4 SW DIP-4 J67 user_out0 user_out1 user_out2 user_out3 user_out4 user_out5 user_out6 user_out7 user_out8 user_out9 user_out10 user_out11 user_out12 user_out13 user_out14 user_out15 138 139 140 141 142 143 144 145 146 151 152 153 154 155 156 157 user_in0 user_in1 user_in2 user_in3 user_in4 user_in5 user_in6 user_in7 204 203 197 205 206 186 198 196 LA[31..1] A 2 4 6 8 10 R61 100k nDS B + GND VCC n-c n-c GND 1 2 3 4 nLRESET cs0_n cs1_n cs2_n cs3_n cs4_n d_strb_ex GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 GND0 R183 10k lbe0 lbe1 lbe2 lbe3 ads_n lclk lw_nr lreset_n +3V3 J66 R178 10k 148 VCCINT 130 VCCINT 111 VCCINT 14 13 12 11 15 28 16 17 nLBE0 nLBE1 nLBE2 nLBE3 nLADS LCLK nLWR 5 6 7 8 +3V3 VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO F1C D +3V3 VCCINT_FPGA +3V3 1k 4 3 2 1 nDTA_ODXA nDTA_ODXB nDTA_ODXC +3V3 100nF C155 RN66 +3V3 1 100nF C154 4 100nF C153 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 User outputs SB-nZBT nPRSNT +3V3 User inputs J68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R268 100R RN67 10k 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 B RN68 10k LED3 Bit 15 R202 220R LED4 Bit 14 R203 220R LED5 Bit 13 R204 220R LED6 Bit 12 R205 220R LED7 Bit 11 R206 220R LED8 Bit 10 R207 220R A Zarlink Semiconductor Cheney Manor Swindon UK Title Note : Default FPGA decoding revised from V1R1. These changes were implemented using patch wires on all V1R0 boards, functionally V1R0 and V1R1 boards are therefore compatible. C 2001, 2002 Copyright Zarlink Semiconductor LED9 Bit 9 R208 220R LED10 Bit 8 R209 220R MT90880 Lab Evaluation Board V1R1 : FPGA - Local bus interface Size B Date: 5 4 3 2 Document Number C385ACS29 Tuesday, May 28, 2002 Rev 1.0 Sheet 1 14 of 21 5 4 3 2 +3V3 P12 C330 + C323 10µF C301 100nF C302 100nF 100nF PHY0 MDC MDIO U13 10k AD6 AB9 AF13 AE13 AD13 AF12 M1_RXD0/RM1_RXD0 M1_RXD1/RM1_RXD1 M1_RXD2 M1_RXD3 M0_RXD0/RM0_RXD0 M0_RXD1/RM0_RXD1 M0_RXD2 M0_RXD3 AD9 AE9 AE8 AF8 AE12 AC13 AD12 AC12 AF11 M1_RXDV/RM1_RXDV M1_RXCLK M1_RXER M1_CRS M1_COL M0_RXDV/RM0_RXDV M0_RXCLK M0_RXER M0_CRS M0_COL AF7 AB10 AD8 AC9 AE7 M_MDC M_MDIO M_MINT0 M_MINT1 AF9 AC10 AF6 AE11 21 22 20 19 18 17 16 TXEN TXCLK/ISOL TXD[0] TXD[1] TXD[2] TXD[3] TXER/TXD[4] 43 42 R99 10k PHY1_INT XT1 XT2 R119 3k3 DNF R104 6k8 5 6 7 8 C299 C300 100nF 100nF 100nF + C296 10µF 3k3 4 3 2 1 C306 C307 100nF 100nF 100nF 3 TD- 10k 1CT:1 TX+ 1 TX- PHY0_REFCLK TP51 RMII_0_CLK RX+ RD+ 4 11 12 13 CABLESTS/LINKSTS 14 PWRDWN 10 3V3 10k TP39 TAG 5 RD- 6 RCT 5 RX- 9 75 x4 R98 3k3 100Mbps R100 220R SHIELD C185 Link 100nF FD/Col 0810-1xx1-03 Belmag R101 220R 1 TP38 TAG C308 R102 220R AGND Chassis GND 3V3 10nF 2kV TP40 TAG 1 8 1000pF 2kV 10 RN70 1k Chassis GND PHY0 Mode B 11 11 12 13 U37D 74LCX00 U39C 74LCX125 13 3 3V3 3V3 6 PHY1_REFCLK Open : MII Closed : RMII J123 2 1 5 8 Q D 2 6 Q CLK 3 CLR SD 1 4 U37B 74LCX00 R116 24R C295 +VS 3 O/P EN 1 100nF GND 2 R237 6 9 5 3V3 5 4 U39D 74LCX125 4 U38A RMII_ENABLE 1 U39B 74LCX125 R110 10k 3V3 XT4 CFPS-73 2 74LCX74 4 10k A R115 3k3 10 R269 Omit R118 1k Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : 100Mbit fast ethernet i/f 0 and clock gen AGND Size B C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 C Orng R103 220R LED14 6 7 Grn LED13 1 3 4 12 DM9161 analogue decoupling C305 RX- AGND +3V3_AVDD0 C298 TD+ PHYCLK_50MHZ 1 2 3 4 TP46 REF_CLK 3V3 3 FDX/COL_LED#/OP0 SPEED_LED#/OP1 LINK/ACT_LED#/OP2 10k BK_REFCLK A RX+ J71 U39A 74LCX125 R117 8 R235 PHY1_MII_CLK RN110 TX- TCT 2 4 DM9161 RXDV/TESTMODE RXCLK/SCR/10BTSER RXEN RXD0/PHYAD0 RXD1/PHYAD1 RXD2/PHYAD2 RXD3/PHYAD3 RXER/RXD[4]/RPTR CRS/PHYAD[4] COL/RMII RN109 8 7 6 5 7 1 2 3k3 2 4 6 8 10 TX+ AGND AGND 1CT:1 TP50 MII_CLK B R105 MDC MDIO MDINTR# RESET# PHY0_RXDV 37 PHY0_RXCLK 34 31 PHY0_RXD0 29 PHY0_RXD1 28 PHY0_RXD2 27 PHY0_RXD3 26 PHY0_RXER 38 PHY0_CRS 35 PHY0_COL 36 MT90880 +3V3 24 25 32 40 AGND 8 7 6 5 PHY0_TXEN PHY0_TXCLK PHY0_TXD0 PHY0_TXD1 PHY0_TXD2 PHY0_TXD3 PHY0_TXER Yel 8 23 30 39 41 R97 1k5 1 2 3 4 M0_TXEN/RM0_TXEN M0_TXCLK J72 7 2 4 6 8 M1_TXEN/RM1_TXEN M1_TXCLK 1 3 5 7 9 D P2 Activity +3V3_AVDD0 1 3 5 7 AD10 AB12 PHY0 Address C184 100nF R92 51R DGND DGND DGND AD7 AE6 AF5 AC8 R267 10k C182 R94 R95 C183 100nF 51R 51R 100nF R93 51R 15 33 44 R266 M0_TXD0/RM0_TXD0 M0_TXD1/RM0_TXD1 M0_TXD2 M0_TXD3 RMII/MII interfaces C329 10µF L16 10µH DVDD DVDD DVDD DVDD R96 3k3 +3V3 M1_TXD0/RM1_TXD0 M1_TXD1/RM1_TXD1 M1_TXD2 M1_TXD3 REF_CLK 100nF AGND AGND AGND MII_HEADER 0 PHY1_TXD0 AD11 PHY1_TXD1 AF10 PHY1_TXD2 AE10 PHY1_TXD3 AC11 AB11 + 100nF 3V3 U1C PHY1_RXDV PHY1_RXCLK PHY1_RXER PHY1_CRS PHY1_COL 100nF C297 10µF + +3V3_AVDD0 PHY_RESET PHY1_RXD0 PHY1_RXD1 PHY1_RXD2 PHY1_RXD3 C304 +3V3 PHY1_TXD[0..3] PHY1_TXEN PHY1_TXCLK C303 11 C324 PHY1_RXD[0..3] C 3V3 DM9161 digital decoupling 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 5 6 46 +3V3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +3V3 1 2 9 +3V3 MDIO MDC RXD3 RXD2 RXD1 RXD0 RXDV RXCK RXER TXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS +3v3 AVDD AVDD AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BGRES BGRESG MDIO MDC PHY0_RXD3 PHY0_RXD2 PHY0_RXD1 PHY0_RXD0 PHY0_RXDV PHY0_RXCLK PHY0_RXER PHY0_TXER PHY0_TXCLK PHY0_TXEN R230 PHY0_TXD0 PHY0_TXD1 1k PHY0_TXD2 PHY0_TXD3 PHY0_COL PHY0_CRS 48 47 Not populated, footprint only D 1 3V3 3 2 Document Number Rev 1.0 C385ACS29 Tuesday, May 28, 2002 Sheet 1 15 of 21 5 4 3 2 1 3V3 C328 C327 10µF + 100nF L15 10µH R72 51R D C178 R73 R74 100nF 51R 51R C179 C180 100nF 100nF 3V3 Activity D 7 3V3 AVDD AVDD AVDD DVDD DVDD DVDD DVDD 1 2 9 48 47 DM9161 RX+ 3 RX- 4 11 12 13 CABLESTS/LINKSTS 14 R81 6k8 + 10k 3V3 1 TXRX+ RD+ PWRDWN 5 RD- 6 RCT 3 5 RX- 75 x4 Grn 10 1000pF 2kV SHIELD 220R RN69 1k R76 3k3 LED11 LED12 100Mbps FD/Col C 8 Orng 10 R80 6 7 9 8 7 6 5 FDX/COL_LED#/OP0 SPEED_LED#/OP1 LINK/ACT_LED#/OP2 R77 220R PHY1 Mode AGND C181 Link 100nF 0810-1xx1-03 Belmag R78 220R AGND R79 220R 3V3 Chassis GND U37C 10 +3V3 C322 TX+ 4 R236 8 C321 10µF B 9 8 7 6 5 100nF RN107 3k3 RN108 1 2 3 4 MII_HEADER 1 Not populated, footprint only 74LCX00 3V3 R86 3k3 +3V3_AVDD1 J70 10k 8 7 6 5 1 2 3 4 B 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TD- 1CT:1 11 XT1 XT2 P11 +3V3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +3V3 3 4 RXDV/TESTMODE RXCLK/SCR/10BTSER RXEN RXD0/PHYAD0 RXD1/PHYAD1 RXD2/PHYAD2 RXD3/PHYAD3 RXER/RXD[4]/RPTR CRS/PHYAD[4] COL/RMII +3V3 +3V3 MDIO MDC RXD3 RXD2 RXD1 RXD0 RXDV RXCK RXER TXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS +3v3 TD+ 1CT:1 J69 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TCT 2 2 TP49 RMII_1_CLK MDIO MDC PHY1_RXD3 PHY1_RXD2 PHY1_RXD1 PHY1_RXD0 PHY1_RXDV PHY1_RXCLK PHY1_RXER PHY1_TXER PHY1_TXCLK PHY1_TXEN PHY1_TXD0 R229 PHY1_TXD1 PHY1_TXD2 1k PHY1_TXD3 PHY1_COL PHY1_CRS 1 1 2 3 4 PHY1_REFCLK 8 2 4 6 8 43 42 PHY1_MII_CLK TX- AGND AGND 1 3 5 7 PHY1_RXER PHY1_CRS PHY1_COL TX+ 7 DGND DGND DGND PHY1_RXD0 PHY1_RXD1 PHY1_RXD2 PHY1_RXD3 AGND 15 33 44 37 34 31 29 28 27 26 38 35 36 C PHY1_RXD[0..3] TXEN TXCLK/ISOL TXD[0] TXD[1] TXD[2] TXD[3] TXER/TXD[4] AGND AGND AGND PHY1_RXDV PHY1_RXCLK 21 22 20 19 18 17 16 5 6 46 TP10 MDC MDIO MDINTR# RESET# BGRES BGRESG PHY1_TXD0 PHY1_TXD1 PHY1_TXD2 PHY1_TXD3 PHY1_TXER 24 25 32 40 8 23 30 39 41 PHY1 U12 MDC MDIO PHY1_INT PHY_RESET PHY1_TXEN PHY1_TXCLK PHY1_TXD[0..3] Yel R71 51R R75 3k3 P1 +3V3_AVDD1 +3V3_AVDD1 +3V3 2 4 6 8 10 PHY1 Address 1 3 5 7 9 C288 C289 C290 C291 100nF 100nF 100nF 100nF + C287 10µF C292 C293 C294 100nF 100nF 100nF AGND R91 10k A A Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : 100Mbit fast ethernet interface #1 Size B C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Document Number C385ACS29 Tuesday, May 28, 2002 Rev 1.0 Sheet 1 16 of 21 5 4 3 2 1 +3V3 C1 10µF nRW0 nOE0 nRAM_CE 0 +3V3 SRAM_CL K nSRAM_ADSC RN2 22R nRW0 nRW1 nRW2 nRW3 1 2 3 4 RN4 22R nOE0 nOE1 nOE2 nOE3 RN17 10k 1 2 3 4 nRAM_CE 0 nRAM_CE 1 nRAM_CE 2 nRAM_CE 3 J2 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 RN7 22R 3 2 1 0 SRAM Chip enable 1 3 5 7 Fit link to enable, minimum 1 device (CE0) Default : All fitted 2 4 6 8 SRAM chip enables RN9 22R RN11 22R RN13 22R RN15 22R C Y2 AB3 RAM_CLK RAM_ADSC# 8 7 6 5 AA2 Y3 AA1 Y5 RAM_RW0# RAM_RW1# RAM_RW2# RAM_RW3# 1 2 3 4 8 7 6 5 AC1 AB2 AA4 AB1 RAM_0E0# RAM_0E1# RAM_0E2# RAM_0E3# 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 Y4 W3 W5 Y1 W2 W1 W4 V2 V5 V1 V4 U3 U2 U1 T3 T2 U5 T1 U4 R3 T5 RAM_A2 RAM_A3 RAM_A4 RAM_A5 RAM_A6 RAM_A7 RAM_A8 RAM_A9 RAM_A10 RAM_A11 RAM_A12 RAM_A13 RAM_A14 RAM_A15 RAM_A16 RAM_A17 RAM_A18 RAM_A19 RAM_A20 RAM_A21 RAM_A22 R187 10k RAM_D0 RAM_D1 RAM_D2 RAM_D3 RAM_D4 RAM_D5 RAM_D6 RAM_D7 RAM_D8 RAM_D9 RAM_D10 RAM_D11 RAM_D12 RAM_D13 RAM_D14 RAM_D15 RAM_D16 RAM_D17 RAM_D18 RAM_D19 RAM_D20 RAM_D21 RAM_D22 RAM_D23 RAM_D24 RAM_D25 RAM_D26 RAM_D27 RAM_D28 RAM_D29 RAM_D30 RAM_D31 AB8 AE5 AC7 AD5 AF4 AE4 AB7 AD4 AF3 AE3 AC6 AF2 AF1 AC5 AD3 AE2 AE1 AC4 AD2 AC3 AD1 AC2 AB4 R1 P3 P2 T4 P1 R5 N1 R4 N2 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 C2 100nF RN1 22R D5 D6 D7 D8 RN3 22R RN5 22R C3 10µF nRW1 nOE1 nRAM_CE 1 D11 D12 D13 D14 RN8 22R nADV D15 D16 D17 D18 RN10 22R D19 D20 D21 D22 RN12 22R RN14 22R C4 10µF C5 100nF +3V3 D31 A2 A3 A4 SRAM_CL K 1 2 3 C317 10µF nADV 1 2 3 O/P 2 delay select +3V3 J130 1F0 1 2 3 J131 1F1 1 2 3 O/P 1 delay select 3 FS 6 7 4F0 4F1 4 5 3F0 3F1 29 30 2F0 2F1 26 27 1F0 1F1 9 16 18 25 2 8 FB REF nADSP VCCN VCCN VCCN VCCN J129 3F1 +3V3 VCCQ VCCQ J128 3F0 1 2 3 U40 17 1 CY7B991V TEST 1 2 3 Fit only if U40 or R200 is omitted! C6 100nF R199 0R 4Q0 4Q1 11 10 3Q0 3Q1 15 14 2Q0 2Q1 20 19 1Q0 1Q1 24 23 GND GND GND GND GND GND J127 RAM_DELAY_FS nRW3 nOE3 nRAM_CE 3 +3V3 A7 A8 A9 A10 A11 A12 A13 A14 C7 10µF nSRAM_ADSC R200 0R A15 A16 A17 A18 A19 A20 Omit when R198 is fitted 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RW0# OE0# RAM_CE0# D0 GND D1 D2 D3 D4 +3V3 D5 D6 D7 D8 GND D9 D10 RW1# OE1# RAM_CE1# D11 D12 D13 D14 ADV# D15 D16 D17 D18 +3V3 D19 D20 D21 D22 GND D23 D24 RW2# OE2# RAM_CE2# D25 GND CLK GND D26 D27 D28 D29 D30 +3V3 D31 A2 A3 A4 ADSP# A5 A6 RW3# OE3# RAM_CE3# A7 A8 A9 A10 GND A11 A12 A13 A14 +3V3 A15 A16 A17 A18 GND ADSC# A19 A20 A21 A22 D C B SIMM 80 12 13 21 22 28 32 B nADSP A5 A6 C310 C311 C312 C313 100nF 100nF 100nF 100nF R198 0R DNF +3V3 Freq select range + 100nF R3 10k S_CLK C309 31 J1 SRAM CLK SRC D25 D26 D27 D28 D29 D30 +3V3 SSRAM clock source D23 D24 nRW2 nOE2 nRAM_CE 2 A[20..2] + D9 D10 RN6 22R MT90880 SSRAM interface C316 10µF D1 D2 D3 D4 + 24R 24R + R1 R2 D0 + 8 7 6 5 U1E D P10 + D[0..31] SSRAM memory card connector SSRAM clock delay generator +3V3 R4 10k R5 10k A A SB-nZBT nPRSNT Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : Synchronous static RAM interface Size A3 C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Document Number C385ACS29 Tuesday, May 28, 2002 Rev 1.0 Sheet 1 17 of 21 4 3 2 1 RN73 10k RN76 10k 8 7 6 5 8 7 6 5 +3V3 RN75 10k +3V3 8 7 6 5 8 7 6 5 +3V3 RN74 10k 8 7 6 5 8 7 6 5 5 D D RN72 10k JTAG_TRST# JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO AC14 AF14 T_MODE0 T_MODE1 AD23 IDDQ B26 AF24 SCLK_AT1 PCLK_AT1 1 D23 2 AC16 VARIANT0 VARIANT1 +3V3 R157 10k RN77 10k 1 2 3 4 J91 1 2 ( 1 : Open) 1 0 T_MODE SW5 SW DIP-4 1 1 : Normal 1 0 : Scan test 0 1 : Board level test 0 0 : PLL test (0 : Closed) 4 T_D status RN81 1k R158 0R SW6 SW DIP-8 SW7 SW DIP-8 B (0 : Closed) 1 2 3 4 5 6 7 8 C225 100nF C RN80 1k +3V3 R184 0R Reset LED1 +3V3 1 2 3 4 1 2 3 4 RN78 1k ( 1 : Open) 1 2 3 4 B J137 Variant Control & JTAG MT90880 nS_RST 8 7 6 5 PLL test o/p J89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 1 2 3 4 14 12 10 8 6 4 2 C AF18 AD17 AE17 AF17 AD16 AC17 AE16 AB16 AF16 AD15 AE15 AF15 AD14 AB15 AE14 AC15 16 15 14 13 12 11 10 9 J90 JTAG header 1 2 3 4 1 2 3 4 AB17 AB18 AC18 AD18 AE18 8 7 6 5 13 11 9 7 5 3 1 PHY_RESET T_D0 T_D1 T_D2 T_D3 T_D4 T_D5 T_D6 T_D7 T_D8 T_D9 T_D10 T_D11 T_D12 T_D13 T_D14 T_D15 S_CLK S_RST# RESOUT# 8 7 6 5 8 7 6 5 B25 D24 C25 S_CLK 8 7 6 5 8 7 6 5 1 2 3 4 1 2 3 4 U1F 1 2 3 4 5 6 7 8 RN71 10k 1 2 3 4 1 2 3 4 R156 33R 16 15 14 13 12 11 10 9 R155 33R nFPGA_RST RN79 1k R160 0R nCODEC_RST U25 MAX811S R161 220R R162 0R n9045_RST VCC A SW8 RESET 3 MR RESET R163 0R 2 nPCI_RST Zarlink Semiconductor GND 1 Cheney Manor Swindon UK Title Reset/+3V3 Monitor MT90880 Lab Evaluation Board V1R1 : MT90880 : JTAG, reset & test Size A Document Number C385ACS29 Rev 1.0 C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 Tuesday, May 28, 2002 2 Sheet of 18 1 21 A 5 4 3 2 +3V3 J74 CPM : TDM i/p ch 1+3 1 3 5 7 9 11 13 15 17 19 D 2 4 6 8 10 12 14 16 18 20 R221 +5V +5V 0R R120 0R DNF SPI_DEVSEL U49A 4 5 6 7 nSPI_CS0 nSPI_CS1 Y0 Y1 Y2 Y3 A B 2 3 G 1 R121 0R 74VHC139 Fit either R231 or R232, not both R231 0R DNF C R222 0R R223 0R R224 0R R232 0R 1 +3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 +3V3 +3V3 L1RSYNC L1TSYNC L1RXD L1TXD L1RXCLK RSVD L3RSYNC L3TSYNC L3RXD L3TXD L3RXCLK VCC VCC SPI_SEL# SPI_CLK SPI_MOSI SPI_MISO RSVD IO_FETHTXCK IO_FETHTXD0 IO_FETHTXD1 IO_FETHTXD2 IO_FETHTXD3 IO_FETHTXEN IO_FETHTXER IO_SMTDX1 IO_SMRXD1 SMSYN1 GND GND SPI_CLK +3V3 +3V3 L2RSYNC L2TSYNC L2RXD L2TXD L2RXCLK CLK4 L4RSYNC L4TSYNC L4RXD L4TXD L4RXCLK VCC VCC RSVD CLK7 I2CSDA I2CSCL IO_FETHRXCLK IO_FETHRXD0 IO_FETHRXD1 IO_FETHRXD2 IO_FETHRXD3 IO_FETHRXDV IO_FETHRER IO_FETHCOL IO_FETHCRS IO_FETHMDIO IO_FETHMDC GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 +3V3 J126 R185 R186 0R INIT_DONE +5V +5V R219 8260_CPM signals R255 0R R256 0R R257 0R R258 0R R259 0R R260 0R R261 0R R262 0R R210 0R R211 0R R212 0R R213 0R R214 0R Default population - +5V +5V + C331 10µF + C332 10µF + C333 10µF + C334 10µF +5V +5V J136 nHRESET A VCC VCC BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 /BWE1 /CS6 /CS8 /CS9 /CS10 VCC MTHR_CLK VCC /IRQ7 /IRQ5 /IRQ4 /IRQ3 /HLTHY GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 +5V +5V +3V3 +3V3 +3V3 +3V3 +5V +5V 2 1 B BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 /BWE0 /BCTL0 /BPOE VCC BA11 BA10 BA9 BA8 VCC /TA /TS /HRESET /DACK1 /DREQ1 /DONE1 /DACK2 /DREQ2 /DONE2 BA20 GND GND J135 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 3V3 3V3 ATMTXD0 ATMTXD1 ATMTXD2 ATMTXD3 ATMTXD4 ATMTXD5 ATMTXD6 ATMTXD7 ATM16_TXD0 ATM16_TXD1 ATM16_TXD2 3V3 3V3 ATM16_TXD3 ATM16_TXD4 ATM16_TXD5 ATM16_TXD6 ATM16_TXD7 GND TXADDR0 TXADDR1 TXADDR2 TXADDR3 TXADDR4 ATMTXPRTY /ATMTEN ATMTSOC ATMTCA ATMCLK GND 3V3 3V3 ATMRXD0 ATMRXD1 ATMRXD2 ATMRXD3 ATMRXD4 ATMRXD5 ATMRXD6 ATMRXD7 ATM16_RXD0 ATM16_RXD1 ATM16_RXD2 3V3 3V3 ATM16_RXD3 ATM16_RXD4 ATM16_RXD5 ATM16_RXD6 ATM16_RXD7 GND RXADDR0 RXADDR1 RXADDR2 RXADDR3 RXADDR4 ATMRXPRTY /ATMRXEN ATMRXSOC ATMRCA GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 +3V3 +3V3 Do Not Fit : R225, R256, R257, R258, R259, R261, R262, R210, R211, R212, R213, R214 U48 9 7 6 5 3 2 4 13 12 14 15 1 B +3V3 +3V3 A Zarlink Semiconductor Size B Date: 4 3 Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : Extended PMC interface connectors PMC Jn5 C 2001, 2002 Copyright Zarlink Semiconductor 5 SRTS_INT O0 CP 10 O1 O2 MR 11 O3 O4 O5 74VHC4040 O6 O7 12 stage divider O8 O9 O10 O11 Fit one only! SRTS int enable PMC Jn5 C Fit : R260 SPI_DO 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 D 0R SPI_DIN J75 SPI_TEST 0R FREQ_MEASURE PMC Jn4 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 Document Number C385ACS29 Tuesday, May 28, 2002 Rev 1.0 Sheet 1 19 of 21 5 4 3 2 1 C186 L4 100µH + +3V3 10µF C191 100nF L7 10µH L8 10µH C199 C200 C201 C202 47pF 47pF 47pF 47pF 3 1 Handset jack #1 C 10µH P4 RJ11 R127 47R L11 10µH R128 47R J79 L12 10µH C208 C209 100nF 47pF ZD9 5V1 C207 ZD8 5V1 47pF ZD7 5V1 C206 ZD6 5V1 47pF C204 100nF C205 R129 1k5 47pF 42 43 MicEar+ EarMic+ L10 10µH 3 SPEAKERP SPEAKERN 1 2 3 4 1 2 3 4 2 3 4 5 1 2 3 4 1 2 3 4 MicEar+ EarMic+ Handset jack #2 HJ_2 B 1 MIC0P MIC0N MICBIAS0 22 23 21 2 3 4 5 HJ_1 L9 3 33 32 26 25 HEADER1x10 J78 1 2 3 4 5 6 7 8 9 10 3 EAR1P EAR1N MIC1P MIC1N ZD5 5V1 R126 1k5 1 GNDP1 GNDP32 1 10µH C203 100nF 31 37 SUB 7 B Serial µPort GNDP0 27 DATA2 DATA1 SCLK CS GNDA 8 9 10 11 SPI_DIN SPI_DO SPI_CLK nSPI_CS0 ZD4 5V1 1 36 35 20 19 3 EAR2P EAR2N MIC2N MIC2P ZD3 5V1 1 17 18 ZD2 5V1 C197 100nF 3 MICBIAS2 MICDETECT2 C196 100nF 1 39 38 15 16 R125 1k5 3 EAR3P EAR3N MIC3P MIC3N PCM 41 J141 Codec links DSTo/Dout/STD DSTi/Din/SRD FOi/FSC/SC2 C4i/DCL/SCK SYSCLK 28 1 2 3 4 5 GNDD 2 4 6 8 R124 47R 1 MICBIAS3 MICDETECT3 MT92303 1 3 5 7 L6 J76 13 14 nCODEC_RST CODEC_DSTo CODEC_DSTi CODEC_nFOi CODEC_nC4i 10µH P3 RJ11 3 44 34 29 6 C193 100nF RESETB C L5 100nF 40 VDDP3 VREF 12 100nF 1 C198 100nF AUXTONE 24 VDDP0 C195 100nF 30 VDDA 2 1 C188 C192 U15 C194 100nF 100nF R123 47R VDDD J77 Aux tone C187 R122 1k5 VDDP21 100nF + 10µF C189 D C190 D TP41 TAG A A Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board V1R1 : Dual codec interface Size B C 2001, 2002 Copyright Zarlink Semiconductor Date: 5 4 3 2 Document Number C385ACS29 Tuesday, May 28, 2002 Rev 1.0 Sheet 1 20 of 21 5 4 3 2 1 +3V3 (Pin 8, U3) L2 C2 10µF C4 100nF + C3 10µF 10µH C5 100nF + L1 10µH Dual section : ODX A & ODX B D D C1 100nF C C6 2p2 C7 2p2 R13 10k R33 10k R3 62k C8 2p2 C9 2p2 1 X1 20 X2 R10 0R R9 10k R8 0R VDD VDD VDD ISEL 2 3 4 10 ICLK1 ICLK2 18 HDR4 B_CLK_OP R31 51R 14 15 12 11 1 2 CLK U2 MK2058-01 SEL0 SEL1 SEL2 GND GND GND GND R14 0R XT2A ECX-5435-24.576M 6 7 8 19 R15 10k C8i_A 17 16 ISET C8o_B 1 2 15 12 11 910k R12 100R 1 2 2 3 4 VDD VDD VDD U1 MK2058-01 SEL0 SEL1 SEL2 9 R32 10k 14 R4 VIN X2 CLK R37 390k HDR2 A_CLK_OP CHGP X1 HDR3 B_CLK_EN R5 0R 9 1 20 R6 10k R30 51R GND GND GND GND ISEL ISET ICLK1 ICLK2 R7 0R 6 7 8 19 18 VIN XT1A ECX-5435-24.576M CHGP 17 16 1 2 C8o_A 100R 5 R29 10 R36 390k 5 R1 910k HDR1 A_CLK_EN R18 10k R17 0R C8i_B R16 10k R19 62k C10 4n7 C C11 4n7 TAG C12 100nF C13 100nF (Pin 5, U3) +3V3 (Pin 1, J88) L3 C15 10µF 10µH C14 100nF C16 100nF + B B R35 10k C17 2p2 C18 2p2 X2 14 15 12 11 R27 10k R28 62k C19 4n7 A R21 0R HDR6 C_CLK_OP C8i_C 1 2 CLK GND GND GND GND X1 R22 10k R34 51R U3 MK2058-01 SEL0 SEL1 SEL2 VIN 1 20 R23 0R VDD VDD VDD ISEL ISET ICLK1 ICLK2 18 CHGP XT3A ECX-5435-24.576M 17 16 9 C8o_C 1 2 R24 100R 2 3 4 10 R38 390k 5 HDR5 C_CLK_EN NOTES 1. Select-on-test capacitors C6, C7, C8, C9, C17 & C18 should be adjusted according to the PCB layout and crystal characteristics to eliminate centering error. Suggested value to suit Ecliptek ECX 5435 and prototype PCB layout is 2.2pF See also Note 2. 910k 6 7 8 19 R20 R26 0R 2. Crystal specification (for 8.192MHz operation) : Frequency : 24.576MHz Initial accuracy at 25°C : ±20ppm Temperature stabiility : ±30ppm Aging : ±20ppm Load capacitance : 14pF Shunt capacitance : 7pF C0/C1 ratio : 250 max Equiv. series resistance : 35 ohms max 3. All component reference designators on this sheet refer to the two additional clock conditioning printed circuit board assemblies which are mounted in the underside of the main board R25 10k Single section : ODX C A TAG C20 100nF Zarlink Semiconductor Cheney Manor Swindon UK Title MT90880 Lab Evaluation Board : 8.192MHz clock conditioning circuits Size B (Corner pin P8) Date: 5 4 3 2 Document Number Rev 1.0 C385ACS29 Tuesday, May 28, 2002 Sheet 1 21 of 21