VP211 Data Sheet

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VP211
Dual 90MHz 6-Bit Analog to Digital Converter
Preliminary Information
DS4476 - 1.1 May 1996
The VP211 is a dual 90MHz 6-bit Analog to Digital
Converter designed for use in consumer satellite receivers
and
decoders,
video
systems,
multimedia
and
communications applications.
Operating from a single +5V supply, the VP211 includes
an on-chip high bandwidth ADC driver amplifier, a 6-bit ADC
and digital I/O that can be interfaced to either +5V or +3V.
The VP211 also has the necessary bias voltages for the
reference resistor chain in the 'flash' architecture of the ADC.
FEATURES
■ 90MHz Conversion Rate
■ TTL Clock/Data Interface
■ 2 Volt Analog Input Range
■ Internal ADC Reference
■ Digital I/O’s compatible with +5V or +3V logic
■ Single 5 Volt Supply
■ Dual ADC System for good channel matching
APPLICATIONS
■ Satellite Decoders
■ Multimedia
■ Communications
CLKIN
1
28
DA5
VCCD
2
27
DA4
DGND
3
26
DA3
VRT
4
25
DA2
COMPA
5
24
DA1
VINA
6
23
DA0
AGND
7
22
OGND
VCCA
8
21
VCCO
VP211
VRM
9
20
DB5
COMPB
10
19
DB4
VINB
11
18
DB3
VRB
12
17
DB2
N.C.
13
16
DB1
N.C.
14
15
DB0
MP28
Fig.1 Pin connections - top view (wide body)
ORDERING INFORMATION
VP211A CG MP1S (Commercial - 28 pin plastic SO)
VCCA
VCCD
VCCO
------------------------------------------------8
2
COMPA
VINA
VRM
VRB
VRT
VINB
COMPB
21
23
24
25
26
27
28
5
6
ADC
DRIVER
6
6-BIT
ADC
+
LATCHES
DATA
OUTPUTS
9
VRB VRM VRT
12
1
CLOCK
DRIVER
OP AMPS
VREF
15
16
17
18
19
20
VRB VRM VRT
4
11
+
ADC
DRIVER
6
6-BIT
ADC
LATCHES
DATA
OUTPUTS
10
3
7
DGND
AGND
22
------------------------------------------------Fig.2 System block diagram
OGND
DA0
DA1
DA2
DA3
DA4
DA5
CLKIN
DB0
DB1
DB2
DB3
DB4
DB5
VP211
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
DC supply voltage (VCCA, VCCD, VCCO)
-0.3 to+7V
Analog input voltage (VIN)
-0.3 to VCC+0.3V
Digital inputs (CLKIN)
VCC
Digital output current (Ioh, Iol, Isc)
-20 to +20mA
Ambient operating temperature (Tamb)
0°C to +70°C
Storage temperature (Tstorage)
-55°C to +125°C
THERMAL RESISTANCES
Junction to case(Θjc)
Junction to ambient(Θja)
32°C/W
84°C/W
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated) Tamb = 25°C, VCCA/D/O = +5V, full temperature range = 0°C to +70°C
DC CHARACTERISTICS All specifications apply to either of the two ADCs
Symbol
Temp.
Test
Level
Min.
Value
Typ.
Max.
-
-
-
6
-
-
Bits
Static performance
Differential non-linearity
DNL
Integral non-linearity
INL
+25°C
Full
+25°C
Full
4
4
4
4
-
-
±0.5
±0.5
±0.5
±0.5
LSB
LSB
LSB
LSB
Full
4
4
4
4
1
4
1
4
1
4
1
4.75
4.75
4.75
14
34
3
260
5.0
5.0
5.0
19
42
11
360
5.25
5.25
5.25
26
51
15
460
V
V
V
mA
mA
mA
mA
mA
mA
mW
Characteristic
Resolution
No missing codes
Power supply
Analog supply voltage
Digital supply voltage
Output supply voltage
Analog supply current
Power dissipation
PD
Analog input
Input range
Input resistance
Input capacitance
Gain variation
Vin
Rin
Cin
GV
Full
+25°C
+25°C
+25°C
5
1
5
4
20k
-
2.0
25k
4.0
-
30k
0.25
V
Ω
pF
dB
Gm
F3dB
Aindc
Vcomp
+25°C
+25°C
+25°C
+25°C
1
5
1
1
3.6
1.8
200
3.9
2.0
0.25
4.1
2.2
dB
MHz
V
V
CLKIN
Input voltage high
Vih
Input voltage low
Vil
Input current high
Iih
Iil
1
4
1
4
1
4
1
4
2.0
–0.2
-
–0.35
-
0.8
1
–0.5
-
V
V
V
V
µA
Input current low
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
Full
1
4
1
4
1
4
1
4
2.4
-
-
3.0
0.4
-400
1
-
Digital supply current
DICC
Output supply current
OICC
Gain matching
Input -3dB bandwidth
Ain input voltage
Comp output
TTL digital outputs
Output voltage high
Voh
Output voltage low
Vol
Output current high
Ioh
Output current low
Iol
Conditions
Guaranteed
Full
Full
Full
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
2
VCCA
VCCD
VCCO
AICC
Units
mA
V
V
V
V
µA
mA
-
Pk to Pk
Fin=300Hz to
20MHz
Fin=15.68MHz
VCCD = 5.25V
Vin = 2.7V
VCCD = 5.25V
Vin = 0.4V
VCCO = 4.75V
Ioh = 400µA
VCCO = 4.75V
Iol = 1mA
VCCO = 4.75V
VCCO = 4.75V
VP211
DC CHARACTERISTICS (cont.)
Symbol
Temp.
Test
Level
Min.
Value
Typ.
Max.
VRB
VRM
VRT
+25°C
+25°C
+25°C
1
1
1
2.367
2.848
3.337
2.5
3.0
3.5
2.671
3.212
3.763
Characteristic
Symbol
Temp.
Test
Level
Min.
Value
Typ.
Max.
Switching performance
Clock high pulse width
Clock low pulse width
Max. conversion rate
Data output setup time
Data output hold time
Aperture delay
Aperture delay matching
Aperture jitter
Tpw1
Tpw0
Fmax
Tsetup
Thold
Tad
Tadδ
Taj
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
4
4
1
4
4
4
4
4
5.7
5.7
90
4
3
2
10
6
6
3
0.25
25
Dynamic performance
Differential non-linearity
Integral non-linearity
Signal to noise ratio
Total harmonic distortion
Effective No. of bits
Crosstalk rejection
Input offset
Error rate
DNL
INL
SNR
THD
ENOB
CTR
Vos
BER
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
4
4
1
4
1
5
1
5
–0.95
31.8
40
5.0
-
5.6
50
±0.5
10e-8
Characteristic
Reference voltage
Vref ladder bottom
Vref ladder middle
Vref ladder top
Units
Conditions
V
V
V
AC CHARACTERISTICS
Units
Conditions
8
8
4
0.5
50
ns
ns
MHz
ns
ns
ns
ns
ps rms
Cload=10pF
Cload=10pF
+1.2
±1
±1
-
LSB
LSB
dB
dBc
bits
dBc
LSB
FCLK =
90.11MHz
FIN =
11.26MHz
NOTES
1. An input voltage of 0.0 volts ±0.5 LSB should nominally correspond to the ‘011111’ to ‘100000’B transition edge.
TEST LEVELS
Level 1 - 100% production tested.
Level 2 - 100% production tested at 25°C and sample tested
at specified temperatures.
Level 3 - Sample tested only.
Level 4 - Parameter is guaranteed by design and
characterisation testing.
Level 5 - Parameter is typical value only.
Input Voltage
Digital Output
2.0 Volt Full Scale
Binary
00
Least positive valid input
000000
01
-
000001
●
●
●
31
-
011111
32
0
100000
33
-
100001
●
●
●
62
-
111110
63
Most positive valid input
111111
Code
Table 1: Output coding
3
VP211
PIN DESCRIPTIONS - 28 Pin Plastic SO Package
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CLKIN
VCCD
DGND
VRT
COMPA
VINA
AGND
VCCA
VRM
COMPB
VINB
VRB
N.C.
N.C.
DB0
DB1
DB2
DB3
DB4
DB5
VCCO
OGND
DA0
DA1
DA2
DA3
DA4
DA5
Description
TTL clock input
Digital voltage supply for ADC’s and input clock
Digital ground
Reference voltage- ladder top
Capacitor compensation - A channel
Analog signal input - A channel
Analog ground
Analog voltage supply for drivers and references
Reference voltage- ladder middle
Capacitor compensation - B channel
Analog signal input - B channel
Reference voltage- ladder bottom
Not connected
Not connected
TTL digital output - channel B - LSB
TTL digital output - channel B - MSB
Output voltage supply for TTL data outputs
Output ground
TTL digital output - channel A - LSB
TTL digital output - channel A - MSB
Table 2: Pin descriptions
ELECTRICAL CHARACTERISTICS DEFINITIONS
Analog Bandwidth
The analog input frequency at which the spectral power
of the fundamental frequency, as determined by FFT analysis
is reduced by 3dB.
Aperture Delay
The delay between the rising edge of the 90MHz clock
signal and the instant the analog input signal is sampled.
Aperture Jitter
The sample to sample variation in aperture delay.
Bit Error Rate (BER)
The number of spurious code errors produced for any
given input sinewave frequency at a given clock frequency. In
this case it is the number of codes occurring outside the
histogram cusp for a 1/2 FS sinewave.
Data Outputs, Set-up and Hold Time
Data output timings are measured from the 50%
threshold to the 50% threshold on the rising edge of the
output clock.
Differential Non-linearity
The deviation in any code width from an ideal 1 LSB step.
4
Effective Number of Bits (ENOB)
This is a measure of a device's dynamic performance
and may be obtained from the SNR or from a sine wave
curve test fit according to the following expressions:
ENOB = SNR-1.76/6.02
or
ENOB = N-log2[rms error (actual)/rms error (ideal)]
where N is the conversion resolution and the actual rms error
is the deviation from an ideal sine wave, calculated from the
converter outputs with a sine wave input.
Integral Non-linearity (INL)
The deviation of the centre of each code from a
reference line which has been determined by a least squares
curve fit.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude to the rms value of
‘noise’ which is defined as the sum of all other spectral
components, including the harmonics, but excluding D.C.
with a full-scale analog input signal.
VP211
Device Description
The VP211 is a dual 90MHz 6-bit ADC system, (see
Fig.2). Included on chip is a high bandwidth ADC driver
amplifier, a 6-bit analog to digital converter, latches and TTL
compatible data outputs. The VP211 also has the necessary
bias voltages for the reference resistor chain in the ‘flash’
architecture of the ADC.
VRM
Analog Input
The analog inputs, (VIN A,B) are A.C. coupled into the
non-inverting input of the ADC driver amplifiers, which
provide the necessary bandwidth, gain, offset and low
impedance required to drive the ADC. The amplifier has
been designed so that an input of 0 volts will produce an
output level equal to the voltage present at the middle of the
ADC resistor chain, VRM (3.00V typ.). This is achieved by an
internal feedback loop within each amplifier which compares
the amplifier output with VRM, (see Fig.3). This voltage will
produce a transition binary code of 011111 to 100000 at the
output of the ADC.
DC SHIFT
COMP_(Q,I)
CCOMP
Fig.3 DC offset internal feedback loop
An on chip band gap voltage reference circuit combined
with two op-amps provides all the necessary bias voltages
for the ADC reference resistor chain, bottom (VRB), middle
(VRM) and top(VRT). VRB, VRM and VRT have been
brought out to pins 12, 9 and 4 respectively and should be
decoupled with 100nF capacitors close to the package pins.
Digital Interface
The TTL data output pins, (DA0-DA5) and (DB0-DB5),
have been optimized to interface with devices in close
proximity to the VP211 and are designed to provide
satisfactory logic levels at speeds up to 90MHz into a fanout
of one and a total load capacitance of 10pF. All data outputs
should have approximately equivalent loading to ensure
proper setup and hold times. For capacitive loads in excess
of 10pF, output buffers are recommended.
ADC Circuit
The VP211 employs a ‘flash’ architecture consisting of a
reference resistor chain, an array of 64 comparators,
encoding logic and a 6-bit latch. The 63 reference levels
generated by the resistor chain are compared with the
analog output signal from the ADC driver amplifier using the
comparator array. This produces a thermometer code which
the encoding logic converts into a 6-bit word.
Clock Interface
The clock signal to the ADC synchronizes the sampling,
conversion and output stages of the device as shown in the
timing diagram (see Fig.4). The output of the ADC driver amp
is sampled when the comparator array is latched on the rising
edge of the input clock. Data is then presented to the TTL data
outputs and latched on the falling edge of the input clock.
Latch
Comparator
τ1
L
C
VIN(A,B)
TO ADC
CC
Reference Voltage
V ref.
ADC DRIVER
AMP
INPUT
SIGNAL
Data Out
Clock to ADC
N-1
N
N+1
VIN(A,B)
Tpw 1
Tpw 0
CLKIN
Data Outputs
N-1
N+1
N
Tsu
TTL
Threshold
THold
Fig.4 System timing diagram
5
VP211
Layout And Grounding
As with all high speed A to D converters, careful
consideration must be given to the PCB layout. High
performance can be obtained from the VP211 by tying all
grounds to a solid low impedance ground plane. Separate
analog and digital ground planes with a single common link
under the device can also be used to help reduce the
amount of digital noise fed back into the analog section of the
converter.
The VP211 should be decoupled with low impedance
100nF ceramic capacitors close to the package pins to avoid
lead inductance effects and the decoupling on supply lines
CLKIN
1.2µH
50R
100n
100n
Cc
Ccomp
VINA
50R
VCCA
47µ
100n
should further be improved by using a 47µF tantalum
capacitor in parallel with a 100nF ceramic capacitor. If VCCA
is derived from VCCD, a small inductor should be used to
reduce digital noise on the analog power supply. Jitter and
noise on clock input pins must be minimised. Long clock
lines should therefore be avoided and all clock lines correctly
terminated. Cross talk of digital signals to the analog inputs
must also be prevented as sampling cross talk produces DC
offsets on the sampled data, for this reason analog inputs
should not be run next to clock or data lines. Device
connections to the ground plane should be as short as
possible.
1
28
2
27
3
26
4
25
5
VP211
24
6
23
7
22
8
21
100n
47µ
100n
100n
Cc
A Channel
Data
50R
100n
VCCD
9
20
10
19
11
18
12
17
13
16
Analog Ground
14
15
Digital Ground
Ccomp
VINB
100n
B Channel
Data
Fig.5 Applications diagram
Application Circuit
Fig.5 shows a typical applications circuit for the VP211.
The supply connections are made using separate low noise
digital and analog power supplies and VCCD is further
isolated from VCCO using a 1.2µH inductor.
The COMPA and COMPB pins must be decoupled to
reduce any ripple at low frequencies which may distort the
ADC driver amplifier output, (see Fig.2.) The decoupling
capacitor value is determined by the required low frequency
performance of the system and can be obtained from the
following equation.
CComp
6
=
75x10- 6
Fin x VRipple
A ripple voltage ≤ 10mV is recommended for good
system performance, e.g. If the analog input frequency Fin=
10KHz a value of 0.75µF is required for CComp.
To ensure effective A.C. coupling at low input
frequencies, the coupling capacitors on pins 6 and 11 can be
calculated from the high pass filter corner frequency
equation,
Fc =
1
2 x π x RC
where
Fc = Lower -3dB corner frequency
(R = Input Resistance, 25K typ. - 20K min)
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