19-2007; Rev 0; 5/01 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier Features ♦ Two Matched 6-Bit, 400Msps ADCs ♦ Excellent Dynamic Performance 36.7dB SINAD at fIN ≈ 125MHz and fCLK ≈ 400MHz ♦ Typical INL and DNL: ±0.25LSB ♦ Channel-to-Channel Phase Matching: ±0.2° ♦ Channel-to-Channel Gain Matching: ±0.04dB ♦ 6:12 Demultiplexer reduces the Data Rates to 200MHz ♦ Low Error Rate: 1016 Metastable States at 400Msps ♦ LVDS Digital Outputs in Two’s Complement Format Ordering Information PART MAX107ECS TEMP. RANGE PIN-PACKAGE -40°C to +85°C 80-Pin TQFP-EP Block Diagram Applications I PRIMARY PORT VSAT Receivers WLANs I ADC I AUXILIARY PORT Test Instrumentation Communications Systems MAX107 REF Q PRIMARY PORT Q ADC Pin Configuration appears at end of data sheet. Q AUXILIARY PORT ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX107 General Description The MAX107 is a dual, 6-bit, analog-to-digital converter (ADC) designed to allow fast and precise digitizing of inphase (I) and quadrature (Q) baseband signals. The MAX107 converts the analog signals of both I and Q components to digital outputs at 400Msps while achieving a signal-to-noise ratio (SNR) of typically 37dB with an input frequency of 125MHz, and an integral nonlinearity (INL) and differential nonlinearity (DNL) of ±0.25 LSB. The MAX107 analog input preamplifiers feature a 400MHz, -0.5dB, and a 1.5GHz, -3dB analog input bandwidth. Matching channel-to-channel performance is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees phase. Dynamic performance is 36.7dB signal-to-noise plus distortion (SINAD) with a 125MHz analog input signal and a sampling speed of 400MHz. A fully differential comparator design and encoding circuits reduce out-ofsequence errors, and ensure excellent metastable performance of only one error per 1016 clock cycles. In addition, the MAX107 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX107 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter’s typical power dissipation is 2.6W. The device is packaged in an 80-pin, TQFP package with exposed paddle, and is specified for the extended (-40°C to +85°C) temperature range. For a higher-speed, 800Msps version of the MAX107, please refer to the MAX105 data sheet. MAX107 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier ABSOLUTE MAXIMUM RATINGS AVCC, AVCCI, AVCCQ and AVCCR to AGND............-0.3V to +6V OVCCI and OVCCQ to OGND ...................................-0.3V to +4V AGND to OGND ................................................... -0.3V to +0.3V P0I± to P5I± and A0I± to A5I± DREADY+, DREADY- to OGNDI ..............-0.3V to OVCCI+0.3V P0Q± to P5Q±, A0Q± to A5Q± DOR+ and DOR- to OGNDQ .................-0.3V to OVCCQ+0.3V REF to AGNDR...........................................-0.3V to AVCCR+0.3V Differential Voltage Between INI+ and INI- ....................-2V, +2V Differential Voltage Between INQ+ and INQ-.................-2V, +2V Differential Voltage Between CLK+ and CLK- ...............-2V, +2V Maximum Current Into Any Pin ...........................................50mA Continuous Power Dissipation (TA = +70°C) 80-Pin TQFP (derate 44mW/°C above +70°C)..................3.5W Operating Temperature Range MAX107ECS .....................................................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead temperature (soldering, 10s) ..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 401.408MHz, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution RES 6 Integral Nonlinearity (Note 1) INL -1 ±0.2 1 LSB Bits Differential Nonlinearity (Note 1) DNL No missing codes guaranteed -1 ±0.25 1 LSB Offset Voltage VOS (Note 2) -1 ±0.25 1 LSB Offset Matching Between ADCs OM (Note 2) -0.5 ±0.1 0.5 LSB 2.4 2.5 2.6 V ±7.5 mV 3.05 V 0.84 Vp-p ANALOG INPUTS (INI+, INI-, INQ+, INQ-) Input Open-Circuit Voltage VAOC Input Open-Circuit Voltage Matching (VINI+ - VIN-) - (VINQ+ - VINQ-) Common Mode Input Voltage Range (Note 3) VCM Full-Scale Analog Input Voltage Range (Note 4) VFSR 0.76 0.8 Input Resistance RIN 1.7 2 kΩ Input Capacitance CIN 1.5 pF TCRIN 150 ppm/°C FPBW-0.5dB 400 MHz 5 Ω Input Resistance Temperature Coefficient Full-Power Analog Input BW Signal + Offset w.r.t. AGND 1.85 REFERENCE OUTPUT 2 Reference Output Resistance RREF Referenced to AGNDR Reference Output Voltage VREF ISOURCE = 500µA 2.45 2.50 _______________________________________________________________________________________ 2.55 V Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 401.408MHz, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLOCK INPUTS (CLK+, CLK-) Clock Input Resistance RCLK Clock Input Resistance Temperature Coefficient TCRCLK CLK+ and CLK- to AGND Minimum Clock Input Amplitude 5 kΩ 150 ppm/°C 500 mVp-p LVDS OUTPUTS (P0I± TO P5I±, P0Q± TO P5Q±, A0I± TO A5I±, A0Q± TO A5Q±, DREADY+, DREADY-, DOR+, DOR-) Differential Output Voltage VOD Change in Magnitude of VOD Between “0” and “1” States ∆VOD Steady-State Common Mode Output Voltage VOC(SS) Change in Magnitude of VOC Between “0” and “1” States ∆VOC 247 1.125 Differential Output Resistance 80 Output Current Short output together 2.5 Short to OGNDI = OGNDQ 25 400 mV ±25 mV 1.375 V ±25 mV 160 Ω mA DYNAMIC SPECIFICATION Effective Number of Bits (Note 8) Signal-to-Noise Ratio (Notes 10, 11) Total Harmonic Distortion (Note 11) fIN = 124.999MHz at -0.5dB FS (Note 9) ENOB fIN = 200.067MHz at -0.5dB FS fIN = 124.999MHz at -0.5dB FS (Note 9) SNR fIN = 200.067MHz at -0.5dB FS fIN = 124.999MHz at -0.5dB FS (Note 9) THD fIN = 200.067MHz at -0.5dB FS fIN = 124.999MHz at -0.5dB FS (Note 9) Spurious-Free Dynamic Range SFDR fIN = 200.067MHz at -0.5dB FS Differential 5.4 5.9 Single-ended 5.9 Differential 5.75 Differential 35 Single-ended 37 37 Differential Differential -49.5 -49.5 Differential -44.5 Differential Differential dB 36.6 Single-ended Single-ended Bits 43 -42 dBc 51 51 dB 45.5 _______________________________________________________________________________________ 3 MAX107 ELECTRICAL CHARACTERISTICS (continued) MAX107 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier ELECTRICAL CHARACTERISTICS (continued) (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 401.408MHz, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) PARAMETER Signal-to-Noise Plus Distortion Ratio SYMBOL CONDITIONS fIN = 124.999MHz at -0.5dB FS (Note 9) SINAD fIN = 200.067MHz at -0.5dB FS Differential MIN TYP 35 36.7 Single-ended MAX 36.7 Differential UNITS dB 36 Two-Tone Intermodulation TTIMD fIN1 = 100.009MHz, fIN2 = 102.067MHz at -7dBFS -55 dBc Crosstalk Between ADCs XTLK fINI = 200.0180MHz, fINQ = 210.0140MHz at -0.5dB FS -70 dB Gain Match Between ADCs GM (Note 12) -0.3 ±0.04 +0.3 dB Phase Match Between ADCs PM (Note 12) -2 ±0.2 +2 deg Metastable Error Rate Less than 1 in 1016 Clock Cycles V POWER REQUIREMENTS Analog Supply Voltage AVCC_ AVCC = AVCCI = AVCCQ = AVCCR 5 ±5% Digital Supply Voltage OVCC_ OVCC I = OVCC Q 3.3 ±10% Analog Supply Current ICC V ICC = AICC R + AICC I + AICC Q + AICC 250 320 mA OICC = OICC I + OICC Q 400 510 mA Output Supply Current OICC Analog Power Dissipation PDISS Common-Mode Rejection Ratio CMRR VIN_+ = VIN_- = ±0.1V (Note 6) Power-Supply Rejection Ratio PSRR AVCC = AVCC I = AVCC Q = AVCC R = +4.75V to +5.25V (Note 7) 2.6 W 40 60 dB 40 57 dB TIMING CHARACTERISTICS Maximum Sample Rate 4 fMAX 400 Msps Clock Pulse Width Low tPWL 1.25 ns Clock Pulse Width High tPWH 1.25 ns Aperture Delay tAD 100 ps Aperture Jitter tAJ 1.5 psRMS 1.5 ns CLK-to-DREADY Propagation Delay tPD1 (Note 13) DREADY-to-DATA Propagation Delay tPD2 (Notes 5, 13) 0 120 _______________________________________________________________________________________ 300 ps Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 401.408MHz, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) PARAMETER SYMBOL DREADY Duty Cycle MAX UNITS (Notes 5, 13) CONDITIONS MIN 47 TYP 53 % LVDS Output Rise-Time tRDATA 20% to 80% (Notes 5, 13) 200 500 ps LVDS Output Fall-Time tFDATA 20% to 80% (Notes 5, 13) 200 500 ps LVDS Differential Skew tSKEW1 Any differential pair <65 Any two LVDS output signals except DREADY <100 ps DREADY Rise-Time tRDREADY 20% to 80% (Notes 5, 13) 200 500 ps DREADY Fall-Time tFDREADY 20% to 80% (Notes 5, 13) 200 500 ps Primary Port Pipeline Delay tPDP 5 Clock Cycles Auxiliary Port Pipeline Delay tPDA 6 Clock Cycles Note 1: INL and DNL is measured using a sine-histogram method. Note 2: Input offset is the voltage required to cause a transition between codes 0 and -1. Note 3: Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input voltage level does not matter. Note 4: The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting algo rithm (e.g. FFT). Note 5: Guaranteed by design and characterization. Note 6: Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-mode voltage expressed in dB. Note 7: Measured with analog power supplies tied to the same potential. Note 8: Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range. Note 9: The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record. Note 10: Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal. The worst case number is presented. Harmonic distortion components two through five are excluded from the noise. Note 11: Harmonic distortion components two through five are included in the total harmonic distortion specification. Note 12: Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input frequency of fIN = 124.999 MHz. Note 13: Measured with a differential probe, 1pF capacitance. _______________________________________________________________________________________ 5 MAX107 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 401.408MHz, differential input at -0.5dB FS, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) 8192-POINT FFT, DIFFERENTIAL INPUT -20 -40 -50 -60 -70 -30 -40 -50 -60 -70 -20 -30 -40 -50 -60 -70 -80 -80 -90 -90 -90 -100 -100 -100 0 20 40 60 80 100 fIN = 200.067MHz AIN = -0.5dB FS -10 AMPLITUDE (dB FS) AMPLITUDE (dB FS) -80 0 40 80 120 160 200 0 240 ANALOG INPUT FREQUENCY (MHz) 60 120 180 ANALOG INPUT FREQUENCY (MHz) TWO-TONE IMD (8192-POINT RECORD), DIFFERENTIAL INPUT SNR vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL INPUT SINAD vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL INPUT 40 MAX107 toc04 fIN1 = 100.009MHz fIN2 = 102.067MHz -20 -1dB FS 35 fIN2 fIN1 -50 AMPLITUDE (dB) -40 -60 -70 -6dB FS 30 -12dB FS 25 -1dB FS 35 -6dB FS 30 -30 40 AMPLITUDE (dB) 0 -10 20 15 MAX107 toc06 ANALOG INPUT FREQUENCY (MHz) MAX107 toc05 AMPLITUDE (dB FS) -30 fIN = 124.999MHz AIN = -0.5dB FS -10 0 MAX107 toc02 fIN = 50.029MHz AIN = -0.5dB FS -20 AMPLITUDE (dB FS) 0 MAX107 toc01 0 -10 8192-POINT FFT, DIFFERENTIAL INPUT MAX107 toc03 8192-POINT FFT, DIFFERENTIAL INPUT 25 -12dB FS 20 15 10 10 5 5 -80 -90 0 40 80 120 160 10M 200 100M 1G 10M 10G 100M 1G ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (Hz) ANALOG INPUT FREQUENCY (Hz) THD vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL INPUT SFDR vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL INPUT FULL-POWER INPUT BANDWIDTH SINGLE-ENDED INPUT -30 AMPLITUDE (dB) -6dB FS -35 -12dB FS -40 -45 0 -6dB FS 10G MAX107 toc09 -1dB FS 50 1 45 40 GAIN (dB) -25 55 MAX107 toc08 60 MAX107 toc07 -20 -12dB FS 35 30 -1 -2 25 -50 -3 20 -1dB FS -55 15 -60 -4 10 10M 100M 1G ANALOG INPUT FREQUENCY (Hz) 6 0 0 -100 AMPLITUDE (dB) MAX107 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier 10G 10M 100M 1G ANALOG INPUT FREQUENCY (Hz) 10G 10M 100M 1G ANALOG INPUT FREQUENCY (Hz) _______________________________________________________________________________________ 10G Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier SINAD vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT fIN = 124.9756MHz fIN = 124.9756MHz 36 32 -42 THD (dB) SINAD (dB) 36 32 28 28 24 24 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 -54 -10 -9 0 -46 -50 -8 -7 -6 -5 -4 -3 -2 -1 0 -10 -9 ANALOG INPUT POWER (dB FS) ANALOG INPUT POWER (dB FS) SFDR vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT SNR vs. TEMPERATURE 45 MAX107 toc13 54 fIN = 124.9756MHz 52 fIN = 124.9756MHz 41 -8 -7 -6 -5 -4 -3 -2 -1 0 ANALOG INPUT POWER (dB FS) SINAD vs. TEMPERATURE 42 MAX107 toc14 SNR (dB) -38 MAX107 toc15 fIN = 124.9756MHz MAX107 toc11 40 MAX107 toc10 40 THD vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT MAX107 toc12 SNR vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT fIN = 124.9756MHz 40 48 46 SINAD (dB) SNR (dB) SFDR (dB) 50 37 33 38 36 44 29 42 40 34 25 -8 -7 -6 -5 -4 -3 -2 -1 0 32 -40 -15 10 35 60 85 -40 35 60 TEMPERATURE (°C) THD vs. TEMPERATURE SFDR vs. TEMPERATURE SNR vs. CLOCK FREQUENCY, DIFFERENTIAL INPUT (-1dB FS) fIN = 124.9756MHz 56 40 fIN = 202.346MHz 38 -54 AMPLITUDE (dB) SFDR (dB) -46 -50 52 48 44 -15 10 35 TEMPERATURE (°C) 60 85 36 34 32 40 -58 85 MAX107 toc18 60 MAX107 toc16 fIN = 124.9756MHz THD (dB) 10 TEMPERATURE (°C) -42 -40 -15 ANALOG INPUT POWER (dB FS) MAX107 toc17 -10 -9 30 -40 -15 10 35 TEMPERATURE (°C) 60 85 400 500 600 700 800 900 CLOCK FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX107 Typical Operating Characteristics (continued) (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 401.408MHz, differential input at -0.5dB FS, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) Typical Operating Characteristics (continued) (AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 401.408MHz, differential input at -0.5dB FS, CL = 1µF to AGND at REF, RL = 100Ω ±1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C) fIN = 202.346MHz 38 fIN = 202.346MHz 34 32 fIN = 101.3925MHz 5.9 ENOB (Bits) AMPLITUDE (dB) -43 36 6.0 MAX107 toc20 -40 MAX107 toc19 40 -46 -49 5.5 -55 400 500 600 700 800 900 5.7 5.6 -52 30 5.8 400 500 CLOCK FREQUENCY (MHz) 600 700 800 4.5 900 4.7 SFDR vs. ANALOG SUPPLY VOLTAGE, DIFFERENTIAL INPUT (-1dB FS) INL vs. DIGITAL OUTPUT CODE fIN = 101.3925MHz 55 5.1 5.3 5.5 DNL vs. DIGITAL OUTPUT CODE 0.40 MAX107 toc23 0.30 MAX107 toc22 57 4.9 ANALOG SUPPLY VOLTAGE (V) CLOCK FREQUENCY (MHz) 0.20 MAX107 toc24 AMPLITUDE (dB) ENOB vs. ANALOG SUPPLY VOLTAGE, DIFFERENTIAL INPUT (-1dB FS) THD vs. CLOCK FREQUENCY, DIFFERENTIAL INPUT (-1dB FS) MAX107 toc21 SINAD vs. CLOCK FREQUENCY, DIFFERENTIAL INPUT (-1dB FS) 0.20 DNL (LSB) 53 INL (LSB) SFDR (dB) 0.10 0 51 0 -0.10 -0.20 49 -0.20 -0.30 47 4.7 4.9 5.1 5.3 8 16 24 32 40 48 56 64 0 16 24 32 40 48 56 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs. TEMPERATURE 2.498 2.494 2.490 270 250 230 210 4.7 4.9 5.1 5.3 ANALOG SUPPLY VOLTAGE (V) 5.5 64 MAX107 toc27 290 300 ANALOG SUPPLY CURRENT (mA) 2.502 310 MAX107 toc26 MAX107 toc25 2.506 4.5 8 ANALOG SUPPLY VOLTAGE (V) 2.510 8 -0.40 0 5.5 ANALOG SUPPLY CURRENT (mA) 4.5 REFERENCE VOLTAGE (V) MAX107 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier 280 260 240 220 200 4.5 4.7 4.9 5.1 5.3 ANALOG SUPPLY VOLTAGE (V) 5.5 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier PIN NAME FUNCTION 1, 20 T.P. Test Point. Do not connect. 2 REF Reference Output 3 AVCCR Analog Reference Supply. Supply voltage for the internal bandgap reference. Bypass to AGNDR with 0.01µF in parallel with 47pF for proper operation. 4 AGNDR Reference, Analog Ground. Connect to AGND for proper operation. 5, 8 AGNDI I-Channel, Analog Ground. Connect to AGND for proper operation. 6 INI- I-Channel, Differential Input. Negative terminal. 7 INI+ I Channel, Differential Input. Positive terminal. 9 AVCCI I-Channel, Analog Supply. Supplies I-channel common-mode buffer, pre-amplifier and quantizer. Bypass to AGNDI with 0.01µF in parallel with 47pF for proper operation. 10 CLK+ Sampling Clock Input 11 CLK- Complementary Sampling Clock Input 12 AVCCQ Q-Channel, Analog Supply. Supplies Q-channel common-mode buffer, pre-amplifier and quantizer. Bypass to AGNDQ with 0.01µF in parallel with 47pF for proper operation. 13, 16 AGNDQ Q-Channel, Analog Ground. Connect to AGND for proper operation. 14 INQ+ Q-Channel, Differential Input. Positive terminal. 15 INQ- Q-Channel, Differential Input. Negative terminal. 17, 18 AGND Analog Ground 19 AVCC Analog Supply. Bypass to AGND with 0.01µF in parallel with 47pF for proper operation. 21 A5Q+ Auxiliary Output Data Bit 5 (MSB), Q-Channel 22 A5Q- Complementary Auxiliary Output Data Bit 5 (MSB), Q-Channel 23 P5Q+ Primary Output Data Bit 5 (MSB), Q-Channel 24 P5Q- Complementary Primary Output Data Bit 5 (MSB), Q-Channel 25 A4Q+ Auxiliary Output Data Bit 4, Q-Channel 26 A4Q- Complementary Auxiliary Output Data Bit 4, Q-Channel 27 P4Q+ Primary Output Data Bit 4, Q-Channel 28 P4Q- Complementary Primary Output Data Bit 4, Q-Channel 29, 35 OVCCQ Q-Channel Outputs, Digital Supply. Supplies Q-channel output drivers and DOR logic. Bypass to OGND with 0.01µF in parallel with 47pF for proper operation. 30, 36 OGNDQ Q-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board for proper operation. _______________________________________________________________________________________ 9 MAX107 Pin Description Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier MAX107 Pin Description (continued) 10 PIN NAME FUNCTION 31 A3Q+ Auxiliary Output Data Bit 3, Q-Channel 32 A3Q- Complementary Auxiliary Output Data Bit 3, Q-Channel 33 P3Q+ Primary Output Data Bit 3, Q-Channel 34 P3Q- Complementary Primary Output Data Bit 3, Q-Channel 37 A2Q+ Auxiliary Output Data Bit 2, Q-Channel 38 A2Q- Complementary Auxiliary Output Data Bit 2, Q-Channel 39 P2Q+ Primary Output Data Bit 2, Q-Channel 40 P2Q- Complementary Primary Output Data Bit 2, Q-Channel 41 A1Q+ Auxiliary Output Data Bit 1, Q-Channel 42 A1Q- Complementary Auxiliary Output Data Bit 1, Q-Channel 43 P1Q+ Primary Output Data Bit 1, Q-Channel 44 P1Q- Complementary Primary Output Data Bit 1, Q-Channel 45 A0Q+ Auxiliary Output Data Bit 0 (LSB), Q-Channel 46 A0Q- Complementary Auxiliary Output Data Bit 0 (LSB), Q-Channel 47 P0Q+ Primary Output Data Bit 0 (LSB), Q-Channel 48 P0Q- Complementary Primary Output Data Bit 0 (LSB), Q-Channel 49 DOR+ Complementary LVDS Out-of-Range Bit 50 DOR- LVDS Out-of-Range Bit 51 DREADY- Complementary Data-Ready Clock 52 DREADY+ Data Ready Clock 53 P0I- Complementary Primary Output Data Bit 0 (LSB), I-Channel 54 P0I+ Primary Output Data Bit 0 (LSB), I-Channel 55 A0I- Complementary Auxiliary Output Data Bit 0 (LSB), I-Channel 56 A0I+ Auxiliary Output Data Bit 0 (LSB), I-Channel 57 P1I- Complementary Primary Output Data Bit 1, I-Channel 58 P1I+ Primary Output Data Bit 1, I-Channel 59 A1I- Complementary Auxiliary Output Data Bit 1, I-Channel 60 A1I+ Auxiliary Output Data Bit 1, I-Channel 61 P2I- Complementary Primary Output Data Bit 2, I-Channel ______________________________________________________________________________________ Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier PIN NAME FUNCTION 62 P2I+ Primary Output Data Bit 2, I-Channel 63 A2I- Complementary Auxiliary Output Data Bit 2, I-Channel 64 A2I+ Auxiliary Output Data Bit 2, I-Channel I-Channel Outputs, Digital Supply. Supplies I-channel output drivers and DREADY circuit. Bypass to OGND with 0.01µF in parallel with 47pF for proper operation. I-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board for proper operation. 65, 72 OVCCI 66, 71 OGNDI 67 P3I- Complementary Primary Output Data Bit 3, I-Channel 68 P3I+ Primary Output Data Bit 3, I-Channel 69 A3I- Complementary Auxiliary Output Data Bit 3, I-Channel 70 A3I+ Auxiliary Output Data Bit 3, I-Channel 73 P4I- Complementary Primary Output Data Bit 4, I-Channel 74 P4I+ Primary Output Data Bit 4, I-Channel 75 A4I- Complementary Auxiliary Output Data Bit 4, I-Channel 76 A4I+ Auxiliary Output Data Bit 4, I-Channel 77 P5I- Complementary Primary Output Data Bit 5, I-Channel 78 P5I+ Primary Output Data Bit 5, I-Channel 79 A5I- Complementary Auxiliary Output Data Bit 5, I-Channel 80 A5I+ Auxiliary Output Data Bit 5, I-Channel Detailed Description The MAX107 is a dual, +5V, 6-bit, 400Msps flash analog-to-digital converter (ADC), designed for high-speed, high bandwidth I&Q digitizing. Each ADC (Figure 1) employs a fully differential, wide bandwidth input stage, 6-bit quantizers and a unique encoding scheme to limit metastable states to typically one error per 1016 clock cycles, with no error exceeding a maximum of 1LSB. An integrated 6:12 output demultiplexer simplifies interfacing to the part by reducing the output data rate to onehalf the sampling clock rate. The MAX107 outputs data in LVDS two’s complement format. When clocked at 400Msps, the MAX107 provides a typical signal-to-noise plus distortion (SINAD) of 36.7dB with a 125MHz input tone. The analog input of the MAX107 is designed for differential or single-ended use with a ±400mV full-scale input range. In addition, the MAX107 features an on-board +2.5V precision bandgap reference, which is scaled to meet the analog input full-scale range. Principle of Operation The MAX107 employs a flash or parallel architecture. The key to this high-speed flash architecture is the use of an innovative, high-performance comparator design. Each quantizer and downstream logic translates the comparator outputs into 6-bit, parallel codes in two’s complement format and passes them on to the internal 6:12 demultiplexer. The demultiplexer enables the ADCs to provide their output data at half the sampling speed on primary and auxiliary ports. LVDS data is available at speeds of up to 200MHz per output port. Input Amplifier Circuits As with all ADCs, if the input waveform is changing rapidly during conversion, effective number of bits (ENOB), signal-to-noise plus distortion (SINAD), and signal-to-noise ratio (SNR) specifications will degrade. The MAX107’s on-board, wide-bandwidth input ampli- ______________________________________________________________________________________ 11 MAX107 Pin Description (continued) MAX107 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier DREADY+/DREADY- MAX107 INI+ I ADC PRE-AMP INI- REF 2kΩ PRIMARY DATA PORT P0I-P5I P0I+/P0I- AUXILIARY DATA PORT A0I-A5I A0I+/A0I- P5I+/P5I- A5I+/A5IAVCC CM BUFFER 10kΩ 1:2 CLK+ REFERENCE CLK10kΩ DOR 2kΩ CM BUFFER REF Q ADC INQ+ PRE-AMP PRIMARY DATA PORT P0Q-P5Q P0Q+/P0Q- AUXILIARY DATA PORT A0Q-A5Q A0Q+/A0Q- P5Q+/P5Q- INQ- REF A5Q+/A5Q- DOR+/DOR- Figure 1. MAX105 Flash Converter Architecture fiers (I&Q) reduce this effect significantly, allowing precise digitizing of fast analog data at high conversion rates. The input amplifiers buffer the input signal and allow a full-scale signal input range of ±400mV (800mVp-p). OVCCI OVCCI Internal Reference The MAX107 features an integrated, buffered +2.5V precision bandgap reference. This reference is internally scaled to match the analog input range specification of ±400mV. The data converter’s reference output (REF) can source up to 500µA. REF should be buffered, if used to supply external devices. P0I+ - P5I+ A0I+ - A5I+ 55Ω 55Ω OVCCI P0I- - P5IA0I- - A5I- LVDS Digital Outputs The MAX107 provides data in two’s complement format to differential LVDS outputs. A simplified circuit schematic of the LVDS output cells is shown in Figure 2. All LVDS outputs are powered from separate I-channel OVCCI and Q-channel OVCCQ (Q-channel) power supplies, which may be operated at +3.3V ±10%. The MAX107 LVDS-outputs provide a typical ±270mV voltage swing around a common mode voltage of roughly 12 MAX107 Figure 2. Simplified LVDS Output Model ______________________________________________________________________________________ Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier MAX107 Table 1. Digital Output Codes Corresponding to a DC-Coupled Single-Ended Analog IN-PHASE INPUTS (INI+, INQ+) INVERTED INPUTS (INI-, INQ-) OUT-OF-RANGE BIT (DOR+, DOR-) OUTPUT CODE > +400mV + VREF AC-coupled to AGND_ 1 011111 +400mV - 0.5LSB + VREF AC-coupled to AGND_ 0 011111 0V + VREF AC-coupled to AGND_ 0 000000/111111 -400mV + 0.5LSB + VREF AC-coupled to AGND_ 0 100000 < -400mV + VREF AC-coupled to AGND_ 1 100000 Table 2. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input IN-PHASE INPUTS (INI+, INQ+) INVERTED INPUTS (INI-, INQ-) OUT-OF-RANGE BIT (DOR+, DOR-) OUTPUT CODE >+200mV + VREF <-200mV + VREF 1 011111 +200mV - 0.25LSB + VREF -200mV + 0.25LSB + VREF 0 011111 0V + VREF 0V + VREF 0 000000/111111 -200mV + 0.25LSB + VREF +200mV - 0.25LSB + VREF 0 100000 <-200mV + VREF >+200mV + VREF 1 100000 +1.2V, and must be differentially terminated at the far end of each transmission line pair (true and complementary) with 100Ω. Out-Of-Range Operation A single output pair (DOR+, DOR-) is provided to flag an out-of-range condition, if either the I or Q channel is out-of-range, where out-of-range is above +FS or below -FS. It features the same latency as the ADCs output data and is demultiplexed in a similar fashion. With a 400MHz system clock, DOR+ and DOR- are clocked at up to 200MHz. Applications Information Single-Ended Analog Inputs The MAX107 is designed to work at full-speed for both single-ended and differential analog inputs without significant degradation in its dynamic performance. Both input channels I (INI+, INI-) and Q (INQ+, INQ-) have 2kΩ impedance and allow for AC- and DC-coupled input signals. In a typical DC-coupled single-ended configuration (Table 1), the analog input signals enter the analog input amplifier stages at the in-phase-input pins INI+/INQ+, while the inverted phase input INI/INQ- pins are AC-coupled to AGNDI/AGNDQ. Singleended operation allows for an input amplitude of 800mVp-p, centered around VREF. Differential Analog Inputs To obtain +FS digital outputs with differential input drive (Table 2), 400mV must be applied between INI+ (INQ+) and INI- (INQ-). Midscale digital output codes occur when there is no voltage difference between INI+ (INQ+) and INI- (INQ-). For a -FS digital output code both in-phase (INI+, INQ+) and inverted input (INI-, INQ-) must see -400mV. Single-Ended to Differential Conversion Using a Balun An RF balun (Figure 3) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX107 for optimum performance. At higher frequencies, the MAX107 provides better SFDR and THD with fully differential input signals over single-ended input signals. In differential input mode, even-order harmonics are suppressed and each input requires only half the signal-swing compared to singleended mode. Clock Input The MAX107 features clock inputs designed for either single-ended or differential operation with very flexible input drive requirements. The clock inputs (AC- or DCcoupled) provide a 5kΩ input impedance to AVCC/2 and are internally buffered with a preamplifier to ensure proper operation of the converter even with smallamplitude sine-wave sources. The MAX107 was ______________________________________________________________________________________ 13 MAX107 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier AGND 50Ω 100pF CLK+, INI+, INQ+ D 0° (500mVp-p clock signal amplitude). To avoid saturation of the input amplifier stage, limit the clock power level to a maximum of +10dBm. 0° B SIGNAL SOURCE A 50Ω 180° 50Ω* 0° AGND C 100pF CLK-, INI-, INQ- Differential Clock (Sine-Wave Drive) The advantages of differential clock drive (Figure 5) can be obtained by using an appropriate balun or transformer to convert single-ended sine-wave sources into differential drives. Refer to Single-Ended Clock Inputs (Sine-Wave Drive) for proper input amplitude requirements. LVDS, ECL and PECL Clock The innovative input architecture of the MAX107 clock also allows these inputs to be driven by LVDS-, ECL- or PECL-compatible input levels, ranging from 500mVp-p to 2Vp-p (Figure 6). 50Ω 50Ω TRANSMISSION LINES AGND AGND 50Ω *TERMINATION OF THE UNUSED INPUT/OUTPUT (WITH 50Ω TO AGND) ON A BALUN IS RECOMMENDED IN ORDER TO AVOID UNWANTED REFLECTIONS. TO 50Ω-TERMINATED SIGNAL SOURCE OR BALUN 100pF CLK+, INI+, INQ+ 100pF CLK-, INI-, INQ- Figure 3. Single-Ended to Differential Conversion Using a Balun 50Ω designed for single-ended, low-phase noise sine-wave clock signals with as little as 500mVp-p amplitude (-2dBm). AGND Figure 5. Differential, AC-Coupled Input Drive (CLK, INI, INQ) Single-Ended Clock (Sine-Wave Drive) Excellent performance is obtained by AC- or DC-coupling a low-phase noise sine-wave source into a single clock input (Figure 4). Essentially, the dynamic performance of the converter is unaffected by clock-drive power levels from -2dBm (500mVp-p clock signal amplitude) to +10dBm (2Vp-p clock signal amplitude). The MAX107 dynamic performance specifications are determined by a single-ended clock drive of -2dBm Timing Requirements 50Ω TRANSMISSION LINES 100pF SIGNAL SOURCE INPUT 100Ω 100pF AGND 50Ω 100pF FROM SIGNAL SOURCE 100pF CLK+, INI+, INQ+ LVDS LINE DRIVER CLK+, INI+, INQ+ CLK-, INI-, INQ- AGND Figure 4. Single-Ended Clock Input With AC-Coupled Input Drive (CLK, INI, INQ) 14 CLK-, INI-, INQ- Figure 6. LVDS Input Drive (CLK, INI, INQ) The MAX107 features a 6:12 demultiplexer, which reduces the output data rate (including DREADY and DOR signals) to one-half of the sample clock rate. The demultiplexed outputs are presented in dual 6-bit two’s complement format with two consecutive samples in the primary and auxiliary output ports on the rising ______________________________________________________________________________________ Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier MAX107 ADC SAMPLE MAX107 ADCs SAMPLE ON THE RISING EDGE OF CLK+ CLKCLK N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 CLK+ DREADYDREADY DREADY+ AUXILIARY DATA PORT N N+2 N+4 N+6 N+8 N+10 PRIMARY DATA PORT N+1 N+3 N+5 N+7 N+9 N+11 NOTE: THE LATENCY TO THE PRIMARY PORT IS FIVE CLOCK CYCLES, THE LATENCY TO THE AUXILIARY PORT IS SIX CLOCK CYCLES. BOTH PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK. tPWH tPWL CLK+ CLKtPD1 DREADY + DREADY tPD2 AUXILIARY PORT DATA PRIMARY PORT DATA Figure 7. Output Timing Relationship Between CLK and DREADY Signals and Primary/Auxiliary Output Ports edge of the data ready clock. The auxiliary data port always contains the older sample. The primary output always contains the most recent data sample, regardless of the DREADY clock phase. Figure 7 shows the timing and data alignment of the auxiliary and primary output ports in relationship with the CLK and DREADY signals. Data in the primary port is delayed by five clock cycles while data in the auxiliary port is delayed by six clock cycles. Typical I/Q Application Quadrature amplitude modulation (QAM) is frequently used in digital communication systems to increase channel capacity. A QAM signal is modulated in both amplitude and phase. With a demodulator, this QAM signal gets downconverted and separated in its inphase (I) and quadrature (Q) components. Both I&Q channels are digitized by an ADC at the baseband level in order to recover the transmitted information. Figure 8 shows a typical application circuit to directly tune L-band signals to baseband, incorporating a direct conversion tuner (MAX2108) and the MAX107 to digitize I&Q channels with excellent phase- and gainmatching. A front-end L-C filter is required for anti-aliasing purposes. ______________________________________________________________________________________ 15 MAX107 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier DREADY+/DREADYFROM PREVIOUS STAGE MAX2108 PRIMARY DATA PORT P0I-P5I QUADRATURE DEMODULATOR NYQUIST FILTER I ADC PRE-AMP AUXILIARY DATA PORT A0I-A5I REF 2kΩ AVCC CM BUFFER 10kΩ 1:2 LO D S P REFERENCE 90° 10kΩ DOR 2kΩ NYQUIST FILTER CM BUFFER PRE-AMP PRIMARY DATA PORT P0Q-P5Q REF Q ADC AUXILIARY DATA PORT A0Q-A5Q DOR+/DOR- Figure 8. Typical I/Q Application Grounding, Bypassing, and Board Layout Grounding and power supply decoupling strongly influence the MAX107’s performance. At 400MHz clock frequency and 6-bit resolution, unwanted digital crosstalk may couple through the input, reference, power supply, ground connections, and adversely influence the dynamic performance of the ADC. In addition, the I&Q inputs may crosstalk through poorly designed decoupling circuits. Therefore, closely follow the grounding and power-supply decoupling guidelines in Figure 9. Maxim strongly recommends using a multilayer printed circuit board (PC board) with separate ground and power supply planes. Since the MAX107 has separate analog and digital ground connections (AGND, AGNDI, AGNDQ, AGNDR, OGNDI, and OGNDQ, respectively). The PC board should feature separate sections designated to analog (AGND) and digital (OGND), connected at only one point. Digital signals should run above the digital ground plane and analog signals should run above the analog ground plane. Keep digital signals far away from the sensitive analog inputs, reference inputs, and clock inputs. High-speed signals, including clocks, 16 analog inputs, and digital outputs, should be routed on 50Ω microstrip lines, such as those employed on the MAX105EV kit. The MAX107 has separate analog and digital powersupply inputs: • AV CC = +5V ±5%: Power supply for the analog input section of the clock circuit. • AVCCI = +5V ±5%: Power supply for the I-channel common-mode buffer, pre-amp and quantizer. • AVCCQ = +5V ±5%: Power supply for the Q-channel common-mode buffer, pre-amp and quantizer. • AVCCR = +5V ±5%: Power supply for the on-chip bandgap reference. • OVCCI = +3.3V ±10%: Power supply for the I-channel output drivers and DREADY circuitry. • OV CC Q = +3.3V ±10%: Power supply for the Q-channel output drivers and DOR circuitry. All supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. For best performance, bypass all power supplies to the appropriate ground with a 10µF tantalum ______________________________________________________________________________________ Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier MAX107 PC BOARD AVCC 10µF 10nF PC BOARD AGND FERRITE-BEAD SUPPRESSORS PC BOARD OVCC OVCCI, OVCCQ 10µF 4 x 10nF 10nF PC BOARD OGND AVCCR OVCCI AVCCR 10nF 47pF OVCCI 47pF AGNDR 10nF OGNDI AGNDR OGNDI AVCCI AVCCI 10nF MAX107 OVCCI 47pF OVCCI 47pF AGNDI OGNDI AVCCQ OVCCQ 10nF OGNDI AGNDI AVCCQ 10nF OVCCQ 47pF 47pF AGNDQ OGNDQ AVCC OVCCQ 10nF AGNDQ OGNDQ AVCC 10nF 47pF OVCCQ 47pF AGND AGND 10nF OGNDQ OGNDQ NOTE: LOCATE ALL 47pF AND 10nF CAPACITORS, WHICH DECOUPLE AVCCI, AVCCQ, AVCCR, OVCCI, AND OVCCQ AS CLOSE AS POSSIBLE TO THE CHIP. IT IS ALSO RECOMMENDED TO CONNECT ALL ANALOG GROUND CONNECTIONS TO A COMMON ANALOG GROUND PLANE AND ALL DIGITAL GROUND CONNECTIONS TO ONE COMMON DIGITAL GROUND PLANE ON THE PC BOARD. A SIMILAR TECHNIQUE CAN BE USED FOR ALL ANALOG AND DIGITAL POWER SUPPLIES. AVCC = AVCCI = AVCCQ = AVCCR = +5V±5% OVCCI = OVCCQ = +3.3V±10% Figure 9. MAX107 Decoupling, Bypassing and Grounding capacitor, to filter power supply noise, in parallel with a 0.1µF capacitor. A combination of 0.01µF in parallel with high quality 47pF ceramic chip capacitor located very close to the MAX107 device filters high frequency noise. A properly designed PC board (see MAX105EV Kit data sheet) allows the user to connect all analog supplies and all digital supplies together thereby requiring only two separate power sources. Decoupling AV CC, AV CCI, AV CCQ and AV CCR with ferrite-bead suppressors prevents further crosstalk between the individual analog supply pins Thermal Management The MAX107 is designed for a thermally enhanced 80pin TQFP package, providing greater design flexibility, increased thermal efficiency and a low thermal junc- ______________________________________________________________________________________ 17 MAX107 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier DIE 80-PIN TQFP PACKAGE WITH EXPOSED PAD BONDING WIRE EXPOXY THERMAL LAND COPPER PLANE, 1oz. EXPOSED PAD COPPER TRACE, 1oz. PC BOARD COPPER TRACE, 1oz. TOP LAYER GROUND PLANE AGND, DGND POWER PLANE GROUND PLANE (AGND) 6 x 6 ARRAY OF THERMAL VIAS THERMAL LAND COPPER PLANE, 1oz. Figure 10. MAX107 Exposed Pad Package Cross-Section tion-case (θjc) resistance of ≈1.26°C/W. In this package, the data converter die is attached to an exposed pad (EP) leadframe using a thermally conductive epoxy. The package is molded in a way, that this leadframe is exposed at the surface, facing the printed circuit board (PC board) side of the package (Figure 10). This allows the package to be attached to the PC board with standard infrared (IR) flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (7.5mm x 7.5mm) does not only guarantee proper attachment of the chip, but can also be used for heat-sinking purposes. Designing thermal vias* into the land area and implementing large ground planes in the PC board design, further enhance the thermal conductivity between board and package. To remove heat from an 80-pin TQFP package efficiently, an array of 6 x 6 vias (≤0.3mm diameter per via hole and 1.2mm pitch between via holes) is required. Note: Efficient thermal management for the MAX107 is strongly depending on PC board and circuit design, component placement, and installation. Therefore, exact performance figures cannot be provided. However, the MAX105EV kit exhibits a typical θja of 18°C/W. For more information on proper design techniques and recommendations to enhance the thermal performance of parts such as the MAX107, please refer to Amkor Technology’s website at www.amkor.com. *Connects the land pattern to internal or external copper planes. 18 Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line is drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX107 are measured using the sine-histogram method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of greater than -1LSB guarantees no missing codes and a monotonic transfer function. Dynamic Parameter Definitions Aperture Jitter and Delay Aperture uncertainties affect the dynamic performance of high-speed converters. Aperture jitter, in particular, directly influences SNR and limits the maximum slew rate (dV/dt) that can be digitized without significant error. Aperture jitter limits the SNR performance of the ADC according to the following relationship: SNRdB = 20 x log10 [1 / (2 x π x fIN x tAJ[RMS])], where fIN represents the analog input frequency and tAJ is the RMS aperture jitter. The MAX107’s innovative ______________________________________________________________________________________ Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier CLK+ tAW ANALOG INPUT THD = 20 x log (V22 + V32 + V4 2 + V52 ) / V12 ) tAD tAJ SAMPLING INSTANT tAW: APERTURE WIDTH tAJ: APERTURE JITTER tAD: APERTURE DELAY Figure 11. Aperture Timing clock design limits aperture jitter to typically 1.5psRMS. Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N-Bits): where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental to the RMS value of the next largest spurious component, excluding DC offset. Two-Tone Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -7dB full-scale and their envelope peaks at -1dB full-scale. Chip Information TRANSISTOR COUNT: 12,286 SNRMAX[dB] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter (see Aperture Uncertainties). SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency, amplitude, and sampling rate relative to an ideal ADC’s quantization noise. For a full-scale input ENOB is computed from: ENOB = (SINAD - 1.76dB) / 6.02dB ______________________________________________________________________________________ 19 MAX107 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: CLK- Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier 20 61 P2I- 63 A2I- 62 P2I+ 64 A2I+ 65 OVCCI 66 OGNDI 67 P3I- 68 P3I+ 69 A3I- 70 A3I+ 71 OGNDI 72 OVCCI 73 P4I- 74 P4I+ 75 A4I- 76 A4I+ 77 P5I- 78 P5I+ 79 A5I- 80 A5I+ MAX107 Pin Configuration T.P. 1 60 A1I+ REF 2 59 A1I- AVCCR 3 58 P1I+ AGNDR 4 57 P1I- AGNDI 5 56 A0I+ INI- 6 55 A0I- INI+ 7 54 P01+ AGNDI 8 53 P01- AVCCI 9 52 DREADY+ CLK+ 10 51 DREADY- 50 DOR- MAX107 36 37 38 39 40 A2Q+ A2Q- P2Q+ P2Q- A1Q+ OGNDQ A1Q- 41 35 42 20 OVCCQ 19 T.P. 34 AVCC P3Q- P1Q+ 33 43 P3Q+ 18 32 AGND 31 P1Q- A3Q- 44 A3Q+ 17 30 AGND OGNDQ A0Q+ 29 45 OVCCQ 16 28 AGNDQ P4Q- A0Q- 27 46 26 15 A4Q- INQ- P4Q+ P0Q+ 25 P0Q- 47 A4Q+ 48 14 24 13 INQ+ P5Q- AGNDQ 23 DOR+ P5Q+ 49 22 12 A5Q- AVCCQ 21 11 A5Q+ CLK- ______________________________________________________________________________________ Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX107 Package Information