LCD Segment Driver series 80-segment Drivers (20SEG×4COM) No.09044EAT02 BU9796FS ●Description This is LCD segment driver for 80 segment type display. There is a lineup which is suitable for multi function display and is integrated display RAM and power supply circuit for LCD driving with 4 common output type: BU9796FS. ●Features 1) 2wire serial interface 2) Integrated RAM for display data (DDRAM) ： 20 × 4bit (Max 80 Segment) 3) LCD driving port： 4 Common output, 20 Segment output 4) Display Duty: 1/4 duty 5) Integrated Oscillation circuit 6) Integrated Buffer AMP for LCD driving power supply circuit 7) Support 1/2bias, 1/3bias select 8) No external components 9) Low voltage / low power consumption design: 2.5~5.5V ●Applications Telephone, FAX, Portable equipments (POS, ECR, PDA etc.), DSC, DVC, Car audio, Home electrical appliance, Meter equipment etc. ● Absolute Maximum Ratings （Ta=25degree, VSS=0V） Parameter Symbol Limits Unit Remarks VDD VLCD -0.5 ～ +7.0 -0.5 ～ +7.0 V V Allowable loss Pd 0.64 W Power supply LCD drive voltage When use more than Ta=25C, subtract 6.4mW per degree. Input voltage range Operational temperature range Storage temperature range VIN -0.5 ～ VDD+0.5 V Topr -40 ～ +85 degree Tstg -55 ～ +125 degree Power Supply Voltage1 Power Supply Voltage2 *This product is not designed against radioactive ray. ● Recommend operating conditions (Ta=25degree, VSS=0V) Parameter Symbol MIN TYP MAX Unit Remarks Power Supply Voltage1 VDD 2.5 - 5.5 V Power supply Power Supply Voltage2 VLCD 0 - VDD-2.4 V LCD drive voltage * Please use in the range of VDD-VLCD≧ 2.4V www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/11 2009.05 - Rev.A Technical Note BU9796FS ●Electrical Characteristics DC Characteristics (VDD=2.5～5.5V, VLCD=0V, VSS=0V, Ta=-40～85degree, unless otherwise specified) Parameter Limit Symbol MIN TYP MAX Unit Condition “H” level input voltage VIH 0.7VDD - VDD “L” level input voltage VIL VSS - 0.3VDD V “H” level input current IIH - - 1 uA “L” level input current IIL -1 - - uA SEG RON - 3 - kΩ COM RON - 3 - kΩ VLCD supply voltage VLCD 0 - VDD-2.4 V VDD-VLCD≧2.4V Standby current IDD1 - - 5 uA Display off, Oscillation off LCD Driver on resistance V Iload=±10uA Power consumption IDD2 - 12.5 30 uA VDD=3.3V, VLCD=0V, Ta=25degree Power save mode SR = Power save mode1, Power save mode FR = Power save mode1 1/3 bias, Frame inverse Frame frequency fCLK 56 80 104 Hz Power save mode FR = Normal mode MPU interface Characteristics (VDD=2.5～5.5V, VLCD=0V, VSS=0V, Ta=-40～85degree, unless otherwise specified) Parameter Limit Symbol MIN. TYP. MAX. Unit Input rise time tr - - 0.3 us Input fall time tf - 0.3 us us SCL cycle time tSCYC 2.5 - - “H” SCL pulse width tSHW 0.6 - - us “L” SCL pulse width tSLW 1.3 - - us SDA setup time tSDS 100 - - ns SDA hold time tSDH - - ns tBUF 100 1.3 - - us tHD;STA tSU;STA tSU;STO 0.6 0.6 0.6 - - us us us Buss free time START condition hold time START condition setup time STOP condition setup time Condition SDA tf tr t LW t BUF t cyc SCL t HD;STA t SDH tr t HW t SDS SDA t SU;STO t SU;STA Fig. 1 interface timing www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/11 2009.05 - Rev.A Technical Note BU9796FS ●Block Diagram ● Pin Arrangement COM0……COM3 SEG0……SEG19 TEST 2 TEST 1 VSS VDD VLCD COM 3 COM 2 COM 1 COM 0 SEG 19 SEG 18 SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 OSCIN SEG 6 SEG 7 SDA SCL SEG 5 SEG0 SEG 4 Segment driver SEG 1 common driver SEG 3 LCD voltage generator SEG 2 VDD ＋ － LCD BIAS SELECTOR common counter ＋ － blink timing generator DDRAM VLCD Command Data Decoder Command register OSCIN OSCILLATOR Pow er On Reset serial inter face IF FILTER VSS Fig. 2 block diagram SDA Fig. 3 SCL Pin arrangement ●Terminal description Terminal TEST1 Terminal No. I/O 26 I Test input (ROHM use only) Must be connect to VSS Function TEST2 27 I Test input (ROHM use only) TEST2=”L”: POR circuit enable TEST2=”H”: POR circuit disenable, refer to “Cautions in Power ON/OFF” OSCIN 28 I External clock input Ext clock and Int clock can be changed by command. Must be connect to VSS when use internal oscillation circuit. SDA 30 I/O serial data in-out terminal SCL 29 I serial data transfer clock VSS 25 GND VDD 24 Power supply 23 Power supply for LCD driving VLCD SEG0-19 31,32 1-18 O SEGMENT output for LCD driving COM0-3 19-22 O COMMON output for LCD driving www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/11 2009.05 - Rev.A Technical Note BU9796FS ● Command Description D7 (MSB) is bit for command or data judgment. Refer to Command and data transfer method. C： 0： Next byte is RAM write data. 1： Next byte is command. ○ Display control (DISCTL) MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 C 0 1 P4 P3 P2 P1 P0 Set Power save mode FR Setup Normal mode Power save mode1 Power save mode2 Power save mode3 Set LCD drive waveform Setup Line inversion Frame inversion Set Power save mode SR Setup P4 P3 Reset initialize condition 0 0 1 1 0 1 0 1 ○ P2 Reset initialize condition 0 1 ○ P1 P0 Reset initialize condition Power save mode1 0 0 Power save mode2 0 1 Normal mode 1 0 ○ High power mode 1 1 * Please keep condition VDD-VLCD≧3.0V in High power mode. ○ Mode Set (MODE SET) MSB D7 C D6 D5 D4 D3 D2 D1 LSB D0 1 0 * P3 P2 * * (*: Don’t Care) Set display ON and OFF Setup Display OFF Display ON Set bias level Setup 1/3 Bias 1/2 Bias www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. P3 Reset initialize condition 0 1 ○ P3 Reset initialize condition 0 1 ○ 4/11 2009.05 - Rev.A Technical Note BU9796FS ○ Address set (ADSET) MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 C 0 0 P4 P3 P2 P1 P0 The range of address can be set as 00000 to 10011(2). ○ Set IC Operation (ICSET) MSB D7 D6 D5 D4 D3 D2 D1 C 1 1 0 1 * P1 LSB D0 P0 (*: Don’t Care) Set software reset execution Setup P1 No operation Software Reset execute 0 1 Set oscillator mode setup Internal oscillation External clock input P0 Reset initialize condition 0 1 ○ ○ Blink control (BLKCTL) MSB D7 D6 D5 D4 D3 D2 D1 C 1 1 1 0 * P1 LSB D0 P0 (*: Don’t Care) Set blink mode Blink mode (Hz) OFF 0.5 1 2 P1 P0 Reset initialize condition 0 0 1 1 0 1 0 1 ○ ○ All Pixel control (APCTL) MSB D7 C D6 D5 D4 D3 D2 D1 LSB D0 1 1 1 1 1 P1 P0 All display set ON, OFF APON Normal All pixel ON APOFF Normal All pixel OFF www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. P1 Reset initialize condition 0 1 ○ P0 Reset initialize condition 0 1 ○ 5/11 2009.05 - Rev.A Technical Note BU9796FS ●Function description ○ Command transfer method 1byte after Slave Address always becomes command input. MSB (“command or data judge bit”) of command decide to next data is command or display data. When set “command or data judge bit”=‘1’, next byte will be command. When set “command or data judge bit”=‘0’, next byte data is display data. S Slave address A 1 Command A 1 Command A 1 Command A 0 Command A Display Data … P Once it becomes display data transfer condition, it cannot input command. When want to input command again, please generate “START condition” once. ○ Write display and transfer method This device has Display Data RAM (DDRAM) of 50×4=200bit. The relationship between data input and display data, DDRAM data and address are as follows; Slave address S 01111100 Command A 0 0000000 A a b c d e f g h A i j k l m n o p A … P Display Data DDRAM address BIT 04 01 02 03 0 a e i m COM0 1 b f j n COM1 2 c g k o COM2 3 d h l p COM3 SEG0 SEG1 SEG2 SEG3 SEG4 05 SEG5 06 SEG6 07 ・・・ 00 SEG7 2Fh SEG47 30h SEG48 31h SEG49 Data transfer to DDRAM happens every 4bit data. So It will be finished to transfer with no need to wait ACK. ○ Reset initialize condition Initial condition after execute Software Reset is as follows. ・ Display is OFF. ・ DDRAM address is initialized (DDRAM Data is not initialized). ・ Refer to Command Description about initialize value of register. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/11 2009.05 - Rev.A Technical Note BU9796FS ●Cautions in Power ON/OFF This device has “P.O.R” (Power-On Reset) circuit and Software Reset function. Please keep the following recommended Power-On conditions in order to power up properly. Please set power up conditions to meet the recommended tR, tF, tOFF, and Vbot spec below in order to ensure P.O.R operation * It has to set TEST2=”L” to be valid in POR circuit. VDD tF Recommendation condition of tR, tF, tOFF, Vbot (Ta=25℃) tR tOFF tR tF tOFF Vbot Less than Less than More than Less than 1ms 1ms 100ms 0.1V Vbot Fig. 4 Power ON/OFF waveform If it is difficult to meet above conditions, execute the following sequence after Power-On. * It has to keep the following sequence in the case of TEST2=”H”. As POR circuit is invalid status. But it is not able to accept Command input in Power off status, it has to take care that software reset is not perfectly alternative method of POR function. (1) Generate STOP condition VDD SDA SCL STOP condition Fig. 5 (2) (3) (4) Stop condition Generate START condition. Issue slave address Execute Software Reset (ICSET) command www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/11 2009.05 - Rev.A Technical Note BU9796FS ●IO Equivalent Circuit VDD VLCD VSS SDA VSS SCL VSS VDD TEST1 VSS VDD TEST2 VSS VDD OSCIN VSS VLCD SEG/COM VSS Fig. 6 I/O equivalent circuit www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/11 2009.05 - Rev.A Technical Note BU9796FS ●Notes for use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, or the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/11 2009.05 - Rev.A Technical Note BU9796FS (12) No Connecting input terminals In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line. (13) Rush current When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow instantaneously. Therefore, give special condition to power coupling capacitance, power wiring, width of GND wiring, and routing of connections. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/11 2009.05 - Rev.A Technical Note BU9796FS ●Ordering part number B D 9 Part No. 7 9 6 F Part No. S - Package FS: SSOP-A32 E 2 Packaging and forming specification E2: Embossed tape and reel SSOP-A32 <Tape and Reel information> 13.6 ± 0.2 (MAX 13.95 include BURR) 17 Embossed carrier tape Quantity 2000pcs Direction of feed 0.3MIN 5.4±0.2 7.8±0.3 32 Tape 1 E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 16 0.11 1.8±0.1 0.15 ± 0.1 0.36 ± 0.1 0.1 0.8 1pin (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 11/11 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.05 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. 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