Si5327 A N Y - F REQUENCY P R E C I S I O N C LOCK M ULTIPLIER /J I T T E R A TTENUATOR Features Generates any frequency from 2 kHz to 808 MHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs with jitter generation as low as 0.5 ps rms (12 kHz–20 MHz) Integrated loop filter with selectable loop bandwidth (4 to 525 Hz) Meets OC-192 GR-253-CORE jitter specifications Rev. 1.0 1/13 Copyright © 2013 by Silicon Laboratories CKOUT1– CKOUT1+ NC GND NC VDD 1 27 SDI NC 2 26 A2_SS INT_LOS1 3 25 A1 LOS2 4 VDD 5 XA 6 XB 7 GND 8 20 NC NC 9 19 NC 24 A0 GND Pad 23 SDA_SDO 22 SCL 21 CKSEL LOL CKIN1– GND 10 11 12 13 14 15 16 17 18 CKIN1+ The Si5327 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5327 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 808 MHz. The two outputs are divided down separately from a common source. The Si5327 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5327 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5327 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5327 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. 36 35 34 33 32 31 30 29 28 RST NC Description Pin Assignments CKOUT2– Synchronous Ethernet Optical modules Wireless repeaters/ wireless backhaul Data converter clocking xDSL PDH clock synthesis Test and measurement Broadcast video CKIN2– CKOUT2+ Dual clock outputs with programmable signal format (LVPECL, LVDS, CML, CMOS) SONET/SDH OC-48/OC-192/STM16/STM-64 line cards ITU G.709 and custom FEC line cards GbE/10GbE, 1/2/4/8/10G Fibre Channel line cards CKIN2+ CMODE Applications Ordering Information: See page 54. VDD Dual clock inputs with manually controlled hitless switching Free run and VCO freeze modes Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236) LOL and LOS alarm outputs I2C or SPI programmable Single 1.8, 2.5, 3.3 V supply Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS compliant RATE Si5327 Si5327 Functional Block Diagram Xtal or Refclock CKIN1 ÷ N31 CKIN2 ÷ N32 Hitless Switching Mux ® DSPLL Xtal/Refclock Loss of Signal/ Frequency Offset Loss of Lock CKOUT1 ÷ N2_LS CKOUT2 ÷ N1_HS ÷ N2 VDD (1.8, 2.5, or 3.3 V) Control Signal Detect I2C/SPI Port GND Clock Select Rate Select Device Interrupt 2 ÷ N1_LS Rev. 1.0 Si5327 TABLE O F C ONTENTS 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7. Pin Descriptions: Si5327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11. Si5327 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Rev. 1.0 3 Si5327 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature TA Supply Voltage during Normal Operation VDD Test Condition Min Typ Max Unit –40 25 85 C 3.3 V Nominal 2.97 3.3 3.63 V 2.5 V Nominal 2.25 2.5 2.75 V 1.8 V Nominal 1.71 1.8 1.89 V Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated. SIGNAL + Differential I/Os VICM , VOCM V VISE , VOSE SIGNAL – Single-Ended Peak-to-Peak Voltage (SIGNAL +) – (SIGNAL –) Differential Peak-to-Peak Voltage VID,VOD VICM, VOCM t SIGNAL + VID = (SIGNAL+) – (SIGNAL–) SIGNAL – Figure 1. Differential Voltage Characteristics 80% CKIN, CKOUT 20% tF tR Figure 2. Rise/Fall Time Characteristics 4 Rev. 1.0 Si5327 Table 2. DC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit IDD LVPECL Format 622.08 MHz Out Both CKOUTs Enabled — 251 279 mA LVPECL Format 622.08 MHz Out 1 CKOUT Enabled — 217 243 mA CMOS Format 19.44 MHz Out Both CKOUTs Enabled — 204 234 mA CMOS Format 19.44 MHz Out 1 CKOUT Enabled — 194 220 mA Disable Mode — 165 — mA 1.8 V ± 5% 0.9 — 1.4 V 2.5 V ± 10% 1 — 1.7 V 3.3 V ± 10% 1.1 — 1.95 V CKNRIN Single-ended 20 40 60 k Single-Ended Input Voltage Swing (See Absolute Specs) VISE fCKIN < 212.5 MHz See Figure 1. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 1. 0.25 — — VPP Differential Input Voltage Swing (See Absolute Specs) VID fCKIN < 212.5 MHz See Figure 1. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 1. 0.25 — — VPP Supply Current1 CKINn Input Pins2 Input Common Mode Voltage (Input Threshold Voltage) Input Resistance VICM Notes: 1. 2. 3. 4. Current draw is independent of supply voltage. No under- or overshoot is allowed. LVPECL outputs require nominal VDD ≥ 2.5 V. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. Rev. 1.0 5 Si5327 Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit CKOVCM LVPECL 100 load line-to-line VDD –1.42 — VDD –1.25 V Differential Output Swing CKOVD LVPECL 100 load line-to-line 1.1 — 1.9 VPP Single Ended Output Swing CKOVSE LVPECL 100 load lineto-line 0.5 — 0.93 VPP Differential Output Voltage CKOVD CML 100 load line-to-line 350 425 500 mVPP CKOVCM CML 100 load line-to-line — VDD-0.36 — V CKOVD LVDS 100 load line-to-line 500 700 900 mVPP Low Swing LVDS 100 load line-to-line 350 425 500 mVPP CKOVCM LVDS 100 load line-to-line 1.125 1.2 1.275 V CKORD CML, LVPECL, LVDS — 200 — Output Voltage Low CKOVOLLH CMOS — — 0.4 V Output Voltage High CKOVOHLH VDD = 1.71 V CMOS 0.8 x VDD — — V Output Clocks (CKOUTn)3,5 Common Mode Common Mode Output Voltage Differential Output Voltage Common Mode Output Voltage Differential Output Resistance Notes: 1. 2. 3. 4. Current draw is independent of supply voltage. No under- or overshoot is allowed. LVPECL outputs require nominal VDD ≥ 2.5 V. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6 Rev. 1.0 Si5327 Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Drive Current (CMOS driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally) CKOIO ICMOS[1:0] = 11 VDD = 1.8 V — 7.5 — mA ICMOS[1:0] = 10 VDD = 1.8 V — 5.5 — mA ICMOS[1:0] = 01 VDD = 1.8 V — 3.5 — mA ICMOS[1:0] = 00 VDD = 1.8 V — 1.75 — mA ICMOS[1:0] = 11 VDD = 3.3 V — 32 — mA ICMOS[1:0] = 10 VDD = 3.3 V — 24 — mA ICMOS[1:0] = 01 VDD = 3.3 V — 16 — mA ICMOS[1:0] = 00 VDD = 3.3 V — 8 — mA VDD = 1.71 V — — 0.5 V VDD = 2.25 V — — 0.7 V VDD = 2.97 V — — 0.8 V VDD = 1.89 V 1.4 — — V VDD = 2.25 V 1.8 — — V VDD = 3.63 V 2.5 — — V 2-Level LVCMOS Input Pins Input Voltage Low Input Voltage High VIL VIH Notes: 1. 2. 3. 4. Current draw is independent of supply voltage. No under- or overshoot is allowed. LVPECL outputs require nominal VDD ≥ 2.5 V. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. Rev. 1.0 7 Si5327 Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 3-Level Input Pins4 Input Voltage Low VILL — — 0.15 x VDD V Input Voltage Mid VIMM 0.45 x VDD — 0.55 x VDD V Input Voltage High VIHH 0.85 x VDD — — V Input Low Current IILL See Note 4 –20 — — µA Input Mid Current IIMM See Note 4 –2 — +2 µA Input High Current IIHH See Note 4 — — 20 µA VOL IO = 2 mA VDD = 1.71 V — — 0.4 V IO = 2 mA VDD = 2.97 V — — 0.4 V IO = –2 mA VDD = 1.71 V VDD –0.4 — — V IO = –2 mA VDD = 2.97 V VDD –0.4 — — V LVCMOS Output Pins Output Voltage Low Output Voltage Low Output Voltage High Output Voltage High VOH Notes: 1. 2. 3. 4. Current draw is independent of supply voltage. No under- or overshoot is allowed. LVPECL outputs require nominal VDD ≥ 2.5 V. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 8 Rev. 1.0 Si5327 Table 3. AC Specifications (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Reference Clock Input Pin XA (XB with cap to GND) Input Resistance XARIN RATE = M, ac coupled — 12 — k Input Voltage Swing XAVPP RATE = M, ac coupled 0.5 — 1.2 VPP 0.5 — 2.4 VPP 0.002 — 710 MHz 40 — 60 % 2 — — ns — — 3 pF Differential Reference Clock Input Pins (XA/XB) Input Voltage Swing XA/XBVPP RATE = M CKINn Input Pins Input Frequency CKNF Input Duty Cycle (Minimum Pulse Width) CKNDC Input Capacitance CKNCIN Input Rise/Fall Time CKNTRF 20–80% See Figure 2 — — 11 ns Output Frequency (Output not configured for CMOS or Disabled) CKOF N1_HS 6 0.002 — 808 MHz Maximum Output Frequency in CMOS Format CKOF — — 212.5 MHz Whichever is smaller (i.e., the 40% / 60% limitation applies only to high frequency clocks) CKOUTn Output Pins Output Rise/Fall (20–80 %) @ 622.08 MHz output CKOTRF Output not configured for CMOS or Disabled See Figure 2 — 230 350 ps Output Rise/Fall (20–80%) @ 212.5 MHz output CKOTRF CMOS Output VDD = 1.71 CLOAD = 5 pF — — 8 ns Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan. Please visit the Silicon Labs Technical Support web page at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. Rev. 1.0 9 Si5327 Table 3. AC Specifications (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Rise/Fall (20–80%) @ 212.5 MHz output CKOTRF CMOS Output VDD = 2.97 CLOAD = 5 pF — — 2 ns Output Duty Cycle Uncertainty @ 622.08 MHz CKODC 100 Load Line-to-Line Measured at 50% Point (Not for CMOS) — — +/-40 ps LVCMOS Input Pins Minimum Reset Pulse Width tRSTMN 1 — — µs Reset to Microprocessor Access Ready tREADY — — 10 ms LVCMOS Output Pins tRF CLOAD = 20pf See Figure 2 — 25 — ns LOSn Trigger Window LOSTRIG From last CKINn to Internal detection of LOSn N3 ≠ 1 — — 4.5 x N3 TCKIN Time to Clear LOL after LOS Cleared tCLRLOL LOS to LOL Fold = Fnew Stable Xa/XB reference — 10 — ms Output Clock Skew tSKEW of CKOUTn to of CKOUT_m, CKOUTn and CKOUT_m at same frequency and signal format CKOUT_ALWAYS_ON = 1 SQ_ICAL = 1 — — 100 ps Phase Change due to Temperature Variation1 tTEMP Max phase changes from –40 to +85 °C — 300 500 ps Rise/Fall Times Device Skew Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan. Please visit the Silicon Labs Technical Support web page at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. 10 Rev. 1.0 Si5327 Table 3. AC Specifications (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit PLL Performance (fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 40 MHz) Lock Time2 tLOCKMP Start of ICAL to of LOL — 1.9 3 s Settle Time2 tSETTLE Start of ICAL to FOUT within 5 ppm of final value — 5.5 6.5 s Output Clock Phase Change tP_STEP After clock switch f3 128 kHz — 200 — ps — 0.05 0.1 dB Jitter Frequency Loop Bandwidth 5000/BW — — ns pk-pk 100 Hz Offset — –80 — dBc/Hz 1 kHz Offset — –110 — dBc/Hz 10 kHz Offset — –113 — dBc/Hz 100 kHz Offset — –117 — dBc/Hz 1 MHz Offset — –125 — dBc/Hz Closed Loop Jitter Peaking JPK Jitter Tolerance JTOL Phase Noise fout = 622.08 MHz CKOPN Subharmonic Noise SPSUBH Phase Noise @ 100 kHz Offset — –80 — dBc Spurious Noise SPSPUR Max spur @ n x F3 (n 1, n x F3 < 100 MHz) — –65 — dBc Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan. Please visit the Silicon Labs Technical Support web page at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. Rev. 1.0 11 Si5327 Table 4. Microprocessor Control (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit I2C Bus Lines (SDA, SCL) Input Voltage Low VILI2C — — 0.25 x VDD V Input Voltage High VIHI2C 0.7 x VDD — VDD V VDD = 1.8V 0.1 x VDD — — V VDD = 2.5 or 3.3 V 0.05 x VDD — — V VDD = 1.8 V IO = 3 mA — — 0.2 x VDD V VDD = 2.5 or 3.3 V IO = 3 mA — — 0.4 V Hysteresis of Schmitt trigger inputs Output Voltage Low 12 VHYSI2C VOLI2C Rev. 1.0 Si5327 Table 4. Microprocessor Control (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Duty Cycle, SCLK tDC SCLK = 10 MHz 40 — 60 % Cycle Time, SCLK tc 100 — — ns Rise Time, SCLK tr 20–80% — — 25 ns Fall Time, SCLK tf 20–80% — — 25 ns Low Time, SCLK tlsc 20–20% 30 — — ns High Time, SCLK thsc 80–80% 30 — — ns Delay Time, SCLK Fall to SDO Active td1 — — 25 ns Delay Time, SCLK Fall to SDO Transition td2 — — 25 ns Delay Time, SS Rise to SDO Tri-state td3 — — 25 ns Setup Time, SS to SCLK Fall tsu1 25 — — ns Hold Time, SS to SCLK Rise th1 20 — — ns Setup Time, SDI to SCLK Rise tsu2 25 — — ns Hold Time, SDI to SCLK Rise th2 20 — — ns Delay Time between Slave Selects tcs 25 — — ns SPI Specifications Rev. 1.0 13 Si5327 Table 5. Jitter Generation (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition1,2,3,4 Min Typ Max GR-253-CORE Unit — 0.5 0.6 4.02 psrms (0.01 UIrms) psrms Measuremen DSPLL BW1 t Filter (MHz) Jitter Gen OC-48 JGEN 0.012–20 111 Hz Notes: 1. 40 MHz fundamental mode crystal used as XA/XB input. 2. VDD = 2.5 V 3. TA = 85 °C 4. Test condition: fIN = 19.44 MHz, fOUT = 156.25 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20–80%), LVPECL clock output. Table 6. Thermal Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient JA Still Air 32 C°/W Thermal Resistance Junction to Case JC Still Air 14 C°/W 14 Rev. 1.0 Si5327 Table 7. Absolute Maximum Ratings* Parameter Symbol Test Condition Min Typ Max Unit DC Supply Voltage VDD –0.5 — 3.8 V LVCMOS Input Voltage VDIG –0.3 — VDD+0.3 V CKINn Voltage Level Limits CKNVIN 0 — VDD V XA/XB Voltage Level Limits XAVIN 0 — 1.2 V Operating Junction Temperature TJCT –55 — 150 ºC Storage Temperature Range TSTG –55 — 150 ºC 2 — — kV ESD MM Tolerance; All pins except CKIN+/CKIN– 150 — — V ESD HBM Tolerance (100 pF, 1.5 k); CKIN+/CKIN– 750 — — V ESD MM Tolerance; CKIN+/CKIN– 100 — — V ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– Latch-up Tolerance JESD78 Compliant *Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Rev. 1.0 15 Si5327 2. Typical Phase Noise Performance Figure 3. Typical Phase Noise (669.326 MHz) Jitter Bandwidth Jitter, RMS SONET_OC48, 12 kHz to 20 MHz 322 fs SONET_OC192_A, 20 kHz to 80 MHz 322 fs SONET_OC192_B, 4 MHz to 80 MHz 105 fs SONET_OC192_C, 50 kHz to 80 MHz 308 fs Brick Wall_800 Hz to 80 MHz 332 fs Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs per Telecordia GR-253-CORE. 16 Rev. 1.0 Si5327 Figure 4. Typical Phase Noise (644.531 MHz) Jitter Bandwidth Jitter, RMS SONET_OC48, 12 kHz to 20 MHz 329 fs SONET_OC192_A, 20 kHz to 80 MHz 328 fs SONET_OC192_B, 4 MHz to 80 MHz 105 fs SONET_OC192_C, 50 kHz to 80 MHz 314 fs Brick Wall_800 Hz to 80 MHz 339 fs Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs per Telecordia GR-253-CORE. Rev. 1.0 17 Si5327 3. Typical Application Circuit C4 1 µF System Power Supply C1 0.1 µF Ferrite Bead C2 0.1 µF VDD = 3.3 V C3 0.1 µF 130 CKIN1– 82 GND PAD CKIN1+ GND VDD 130 0.1 µF CKOUT1+ + 100 – CKOUT1– 82 0.1 µF 0.1 µF Input Clock Sources* Clock Outputs CKOUT2+ VDD = 3.3 V 130 + 100 – CKOUT2– 130 0.1 µF CKIN2+ CKIN2– 82 82 INT_LOS1 Si5327 Interrupt/CKIN1 LOS Indicator LOS2 Option 1: CKIN2 LOS Indicator XA LOL Crystal PLL Loss of Lock Indicator XB VDD 15 k A[2:0] RATE2 Crystal/Ref Clk Rate 15 k 0.1 µF Option 2: Refclk+ XA Serial Port Address SDA Serial Data SCL Serial Clock CKSEL Clock Select I2C Interface 0.1 µF XB Refclk– CMODE Control Mode (L) RST Reset Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. I2C-required pull-up resistors not shown. Figure 5. Si5327 Typical Application Circuit (I2C Control Mode) Note: For an example schematic and layout, refer to the Si5327-EVB User’s Guide. C4 1 µF System Power Supply C1 0.1 µF Ferrite Bead C2 0.1 µF VDD = 3.3 V C3 0.1 µF 130 CKIN1+ 82 82 GND PAD GND VDD 130 0.1 µF CKOUT1+ + 100 – CKOUT1– CKIN1– 0.1 µF 0.1 µF Input Clock Sources* Clock Outputs CKOUT2+ VDD = 3.3 V + 100 130 130 82 82 – CKOUT2– 0.1 µF CKIN2+ CKIN2– INT_LOS1 Si5327 Option 1: XA LOS2 LOL Interrupt/CLKIN1 LOS Indicator CLKIN2 LOS Indicator PLL Loss of Lock Indicator Crystal XB VDD SS 15 k Slave Select RATE2 Crystal/Ref Clk Rate 15 k SDO Serial Data Out SPI Interface 0.1 µF Option 2: Refclk+ SDI XA 0.1 µF Refclk– Control Mode (H) Reset XB CMODE Serial Data In SCLK Serial Clock CKSEL Clock Select RST Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). Figure 6. Si5327 Typical Application Circuit (SPI Control Mode) Note: For an example schematic and layout, refer to the Si5327-EVB User’s Guide. 18 Rev. 1.0 Si5327 4. Functional Description Xtal or Refclock CKIN1 ÷ N31 CKIN2 ÷ N32 Hitless Switching Mux ® DSPLL Xtal/Refclock Loss of Signal/ Frequency Offset Loss of Lock ÷ N1_LS CKOUT1 ÷ N2_LS CKOUT2 ÷ N1_HS ÷ N2 VDD (1.8, 2.5, or 3.3 V) Control Signal Detect I2C/SPI Port GND Clock Select Rate Select Device Interrupt Figure 7. Functional Block Diagram The Si5327 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5327 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 808 MHz. The Si5327 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for each input clock and output clock, so the Si5327 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The Si5327 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. This utility can be downloaded from http://www.silabs.com/timing. The Si5327 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides any frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5327 PLL loop bandwidth is digitally programmable and supports a range from 4 to 525 Hz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5327 supports hitless switching between the two manually controlled synchronous input clocks in compliance with GR-253-CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (maximum 200 ps phase change). The Si5327 monitors both input clocks for loss-of-signal (LOS) and provides a LOS alarm (INT_LOS1 and LOS2) when it detects missing pulses on either input clock. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The Si5327 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. During digital hold, the DSPLL generates an output frequency based on a historical average frequency that existed for a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold. The Si5327 has two differential clock outputs. The electrical format of each clock output is independently programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, the second clock output can be powered down to minimize power consumption. The device input to output skew is not specified. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply. Rev. 1.0 19 Si5327 4.1. External Reference 4.2. Further Documentation An external, high quality clock or a low-cost 40 MHz crystal is used as part of a fixed-frequency oscillator within the DSPLL. This external reference is required for the device to perform jitter attenuation. Silicon Laboratories recommends using a high quality crystal. Specific recommendations may be found in the Family Reference Manual. Consult the Silicon Laboratories Si53xx Any Frequency Precision Clock Family Reference Manual (Si53xx FRM) for detailed information about the Si5327 functions. Additional design support is available from Silicon Laboratories through your distributor. In digital hold, the DSPLL remains locked and tracks the external reference. Note that crystals can have temperature sensitivities. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from http://www.silabs.com/timing. If there is a need to use a reference oscillator instead of a crystal, Silicon Labs does not recommend using MEMS based oscillators. The very low loop BW of the Si5327 means that it can be susceptible to XAXB reference sources that have high wander. Experience has shown that in spite of having low jitter, some MEMs oscillators have high wander, and these devices should be avoided. Contact Silicon Labs for details. Table 8. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table 20 CKOUT_ALWAYS_ON SQ_ICAL Results 0 0 CKOUT OFF until after the first ICAL 0 1 CKOUT OFF until after the first successful ICAL (i.e., when LOL is low) 1 0 CKOUT always ON, including during an ICAL 1 1 CKOUT always ON, including during an ICAL. Use these settings to preserve output-to-output skew Rev. 1.0 Si5327 5. Register Map All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the specified Reset Values may result in undefined device behavior. Registers not listed, such as Register 64, should never be written to. Register 0 2 D7 D6 D5 D4 FREE_RUN CKOUT_ ALWAYS_ ON D3 D0 BYPASS_ REG VCO_ FREEZE SQ_ICAL 4 HIST_DEL[4:0] ICMOS[1:0] 6 8 D1 BWSEL_REG[3:0] 3 5 D2 SFOUT2_REG[2:0] HLOG_2[1:0] 9 SFOUT1_REG[2:0] HLOG_1[1:0] HIST_AVG[4:0] 10 DSBL2_ REG DSBL1_ REG 11 PD_CK2 19 VALTIME[1:0] 20 CK2_ BAD_ PIN PD_CK1 LOCK[T2:0] CK1_ BAD_ PIN LOL_PIN INT_PIN 22 CK_BAD_ POL LOL_POL INT_POL 23 LOS2_MSK LOS1_MSK LOSX_MSK 24 25 LOL_MSK N1_HS[2:0] 31 NC1_LS[19:16] 32 NC1_LS[15:8] 33 NC1_LS[7:0] 34 NC2_LS[19:16] 35 NC2_LS[15:8] 36 NC2_LS[7:0] 40 41 N2_HS[2:0] N2_LS[19:16] N2_LS[15:8] Rev. 1.0 21 Si5327 Register D7 D6 D5 42 D4 D3 D2 D1 D0 N2_LS[7:0] 43 N31[18:16] 44 N31[15:8] 45 N31[7:0] 46 N32[18:16] 47 N32[15:8] 48 N32[7:0] 128 129 LOS2_INT CK2_ACTV_REG CK1_ACTV_REG LOS1_INT LOSX_INT 130 LOL_INT 131 LOS2_FLG 132 PARTNUM_RO[11:4] 135 PARTNUM_RO[3:0] RST_REG REVID_RO[3:0] ICAL 137 FASTLOCK 138 139 22 LOSX_FLG LOL_FLG 134 136 LOS1_FLG LOS2_EN [1:1] LOS2_EN [0:0] LOS1_EN [0:0] Rev. 1.0 LOS1_EN [1:1] Si5327 6. Register Descriptions Register 0. Bit D7 Name Type D6 D5 FREE_ RUN CKOUT_ ALWAYS_ ON R/W R/W R D4 D3 D2 D1 D0 BYPASS_ REG R R R R/W R Reset value = 0001 0100 Bit Name 7 Reserved 6 FREE_RUN 5 Free Run. Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB reference. 0: Disable 1: Enable CKOUT_ CKOUT Always On. ALWAYS_ON This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on and ICAL is not complete or successful. See Table 8 on page 20. 0: Squelch output until part is calibrated (ICAL). 1: Provide an output. Note: The frequency may be significantly off and variable until the part is calibrated. 4:2 Reserved 1 BYPASS_ REG 0 Function Bypass Register. This bit enables or disables the PLL bypass mode. Use only when the device is in digital hold or before the first ICAL. 0: Normal operation 1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing the PLL. Bypass mode does not support CMOS clock outputs. Reserved Rev. 1.0 23 Si5327 Register 2. Bit D7 D6 D5 Name BWSEL_REG [3:0] Type R/W D4 D3 D2 D1 D0 R R R R Reset value = 0100 0010 Bit 7:4 3:0 Name Function BWSEL_REG BWSEL_REG. [3:0] Selects nominal f3dB bandwidth for PLL. See DSPLLsim for settings. After BWSEL_REG is written with a new value, an ICAL is required for the change to take effect. Reserved Register 3. Bit D7 D6 Name Type D5 D4 VCO_FREEZE SQ_ICAL R/W R/W R D3 D2 D1 D0 R R R R Reset value = 0000 0101 Bit Name 7:6 Reserved 5 Function VCO_FREEZE VCO_FREEZE. Forces the part into VCO freeze. This bit overrides all other manual and automatic clock selection controls. 0: Normal operation. 1: Force VCO freeze mode. Overrides all other settings and ignores the quality of all of the input clocks. 4 SQ_ICAL SQ_ICAL. This bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. See Table 8 on page 20. 0: Output clocks enabled during ICAL. 1: Output clocks disabled during ICAL. 3:0 24 Reserved Rev. 1.0 Si5327 Register 4. Bit D7 D6 D5 D4 D3 Name D2 D1 D0 HIST_DEL [4:0] Type R R R R/W Reset value = 0001 0010 Bit Name 7:5 Reserved 4:0 Function HIST_DEL [4:0] HIST_DEL [4:0]. Selects amount of delay to be used in generating the history information used for Digital Hold. See the Si53xx Family Reference Manual for a detailed description. Register 5. Bit D7 D6 Name ICMOS [1:0] Type R/W D5 D4 D3 D2 D1 D0 R R R R R R Reset value = 1110 1101 Bit Name 7:6 ICMOS [1:0] Function ICMOS [1:0]. When the output buffer is set to CMOS mode, these bits determine the output buffer drive strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation. These values assume CKOUT+ is tied to CKOUT-. 00: 8mA/2mA 01: 16mA/4mA 10: 24mA/6mA 11: 32mA/8mA 5:0 Reserved Rev. 1.0 25 Si5327 Register 6. Bit D7 D6 Name Type R D5 D4 D3 D2 D1 SFOUT2_REG [2:0] SFOUT1_REG [2:0] R/W R/W R Reset value = 0010 1101 Bit Name 7:6 Reserved 5:3 Function SFOUT2_REG [2:0] SFOUT2_REG [2:0]. Controls output signal format and disable for CKOUT2 output buffer. 000: Reserved 001: Disable 010: CMOS (Bypass mode not supported) 011: Low swing LVDS 100: Reserved 101: LVPECL 110: CML 111: LVDS Note: LVPECL requires a nominal VDD 2.5 V. 2:0 SFOUT1_REG [2:0] SFOUT1_REG [2:0]. Controls output signal format and disable for CKOUT1 output buffer. 000: Reserved 001: Disable 010: CMOS (Bypass mode not supported) 011: Low swing LVDS 100: Reserved 101: LVPECL 110: CML 111: LVDS Note: LVPECL requires a nominal VDD 2.5 V. 26 Rev. 1.0 D0 Si5327 Register 8. Bit D7 D6 D5 D4 Name HLOG_2[1:0] HLOG_1[1:0] Type R/W R/W D3 D2 D1 D0 R Reset value = 0000 0000 Bit 7:6 Name Function HLOG_2 [1:0] HLOG_2 [1:0]. 00: Normal operation 01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur without glitches or runt pulses. 10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur without glitches or runt pulses. 11: Reserved 5:4 HLOG_1 [1:0]. 00: Normal operation 01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur without glitches or runt pulses. 10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur without glitches or runt pulses. 11: Reserved 3:0 Reserved Register 9. Bit D7 D6 D5 Name HIST_AVG [4:0] Type R/W D4 D3 D2 D1 D0 R R R Reset value = 1100 0000 Bit Name 7:3 HIST_AVG [4:0] Function HIST_AVG [4:0]. Selects amount of averaging time to be used in generating the history information for Digital Hold. See the Si53xx Family Reference Manual for a detailed description 2:0 Reserved Rev. 1.0 27 Si5327 Register 10. Bit D7 D6 D5 D4 D3 Name D2 D1 D0 R R DSBL2_REG DSBL1_REG Type R R R R R/W R/W Reset value = 0000 0000 Bit Name 7:4 Reserved 3 Function DSBL2_REG DSBL2_REG. This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is selected, the NC2_LS output divider is also powered down. 0: CKOUT2 enabled 1: CKOUT2 disabled 2 DSBL1_REG DSBL1_REG. This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is selected, the NC1_LS output divider is also powered down. 0: CKOUT1 enabled 1: CKOUT1 disabled 1:0 Reserved Register 11. Bit D7 D6 D5 D4 D3 D2 Name Type R R R R R R Reset value = 0100 0000 Bit Name 7:2 Reserved 1 PD_CK2 Function PD_CK2. This bit controls the powerdown of the CKIN2 input buffer. 0: CKIN2 enabled 1: CKIN2 disabled 0 PD_CK1 PD_CK1. This bit controls the powerdown of the CKIN1 input buffer. 0: CKIN1 enabled 1: CKIN1 disabled 28 Rev. 1.0 D1 D0 PD_CK2 PD_CK1 R/W R/W Si5327 Register 19. Bit D7 D6 D5 Name Type R R R D4 D3 D2 D1 VALTIME [1:0] LOCKT [2:0] R/W R/W D0 Reset value = 0010 1100 Bit Name 7:5 Reserved 4:3 Function VALTIME [1:0] VALTIME [1:0]. Sets amount of time for input clock to be valid before the associated alarm is removed. 00: 2 ms 01: 100 ms 10: 200 ms 11: 13 seconds 2:0 LOCKT [2:0] LOCKT [2:0]. Sets retrigger interval for one shot monitoring phase detector output. One shot is triggered by phase slip in DSPLL. Refer to the Si53xx Family Reference Manual for more details. To minimize lock time, the value 001 for LOCKT is recommended. 000: 106 ms 001: 53 ms 010: 26.5 ms 011: 13.3 ms 100: 6.6 ms 101: 3.3 ms 110: 1.66 ms 111: .833 ms Rev. 1.0 29 Si5327 Register 20. Bit D7 D6 D5 D4 Name Type D3 D2 CK2_BAD_PIN CK1_BAD_PIN R R R R R/W D1 D0 LOL_PIN INT_PIN R/W R/W R/W Reset value = 0011 1110 Bit Name 7:4 Reserved 3 Function CK2_BAD_PIN CK2_BAD_PIN. The CK2_BAD status can be reflected on the LOS2 output pin. 0: LOS2 output pin tristated 1: CK2_BAD status reflected to output pin 2 CK1_BAD_PIN CK1_BAD_PIN. Either LOS1 or INT (see INT_PIN) status can be reflected on the INT_LOS1 output pin. 0: INT_LOS1 output pin tristated 1: LOS1 or INT (see INT_PIN) status reflected to output pin 1 LOL_PIN LOL_PIN. The LOL_INT status bit can be reflected on the LOL output pin. 0: LOL output pin tristated 1: LOL_INT status reflected to output pin 0 INT_PIN INT_PIN. Reflects the interrupt status on the INT_LOS1 output pin. 0: Interrupt status not displayed on INT_LOS1 output pin. Instead, the INT_LOS1 pin indicates when CKIN1 is bad. If CK1_BAD_PIN = 0, INT_LOS1 output pin is tristated. 1: Interrupt status reflected to output pin. 30 Rev. 1.0 Si5327 Register 22. Bit D7 D6 D5 D4 D3 Name Type R R R R D2 D1 D0 CK_BAD_ POL LOL_POL INT_POL R R/W R/W R Reset value = 1101 1111 Bit Name 7:3 Reserved 2 CK_BAD_ POL Function CK_BAD_POL. Sets the active polarity for the INT_C1B and C2B signals when reflected on output pins. 0: Active low 1: Active high 1 LOL_POL LOL_POL. Sets the active polarity for the LOL status when reflected on an output pin. 0: Active low 1: Active high 0 INT_POL INT_POL. Sets the active polarity for the interrupt status when reflected on the INT_LOS1 output pin. 0: Active low 1: Active high Rev. 1.0 31 Si5327 Register 23. Bit D7 D6 D5 D4 D3 D2 Name D1 D0 LOS2_ MSK LOS1_ MSK LOSX_ MSK Type R R R R R R/W R/W R/W Reset value = 0001 1111 Bit Name 7:3 Reserved 2 LOS2_MSK Function LOS2_MSK. Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOS2_FLG register. 0: LOS2 alarm triggers active interrupt on INT_LOS1 output (if INT_PIN=1). 1: LOS2_FLG ignored in generating interrupt output. 1 LOS1_MSK LOS1_MSK. Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOS1_FLG register. 0: LOS1 alarm triggers active interrupt on INT_LOS1 output (if INT_PIN=1). 1: LOS1_FLG ignored in generating interrupt output. 0 LOSX_MSK LOSX_MSK. Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOSX_FLG register. 0: LOSX alarm triggers active interrupt on INT_LOS1 output (if INT_PIN=1). 1: LOSX_FLG ignored in generating interrupt output. Register 24. Bit D7 D6 D5 D4 D3 D2 D1 Name Type D0 LOL_MSK R R R R R R R R Reset value = 0011 1111 Bit Name 7:1 Reserved 0 LOL_MSK Function LOL_MSK. Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this register do not change the value held in the LOL_FLG register. 0: LOL alarm triggers active interrupt on INT_LOS1 output (if INT_PIN=1). 1: LOL_FLG ignored in generating interrupt output. 32 Rev. 1.0 Si5327 Register 25. Bit D7 D6 Name N1_HS [2:0] Type R/W D5 D4 D3 D2 D1 D0 R R R R R Reset value = 0010 0000 Bit Name 7:5 N1_HS [2:0] Function N1_HS [2:0]. Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider. 000: N1= 4 001: N1= 5 010: N1= 6 011: N1= 7 100: N1= 8 101: N1= 9 110: N1= 10 111: N1= 11 4:0 Reserved Register 31. Bit D7 D6 D5 D4 D3 Name Type D2 D1 D0 NC1_LS [19:16] R R R R R/W Reset value = 0000 0000 Bit Name 7:4 Reserved 3:0 NC1_LS [19:16] Function NC1_LS [19:16]. Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Rev. 1.0 33 Si5327 Register 32. Bit D7 D6 D5 D4 D3 Name NC1_LS [15:8] Type R/W D2 D1 D0 Reset value = 0000 0000 Bit Name 7:0 NC1_LS [15:8] Function NC1_LS [15:8]. Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Register 33. Bit D7 D6 D5 D4 D3 Name NC1_LS [7:0] Type R/W D2 D1 D0 Reset value = 0011 0001 34 Bit Name 7:0 NC1_LS [19:0] Function NC1_LS [7:0]. Sets value for N1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Rev. 1.0 Si5327 Register 34. Bit D7 D6 D5 D4 D3 Name D2 D1 D0 NC2_LS [19:16] Type R R R R R/W Reset value = 0000 0000 Bit Name 7:4 Reserved 3:0 NC2_LS [19:16] Function NC2_LS [19:16]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 00000000000000000011=4 00000000000000000101=6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Register 35. Bit D7 D6 D5 D4 D3 Name NC2_LS [15:8] Type R/W D2 D1 D0 Reset value = 0000 0000 Bit Name 7:0 NC2_LS [15:8] Function NC2_LS [15:8]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] Rev. 1.0 35 Si5327 Register 36. Bit D7 D6 D5 D4 D3 Name NC2_LS [7:0] Type R/W D2 D1 D0 Reset value = 0011 0001 Bit 7:0 Name Function NC2_LS [7:0] NC2_LS [7:0]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20] 36 Rev. 1.0 Si5327 Register 40. Bit D7 D6 Name N2_HS [2:0] Type R/W D5 D4 D3 D2 D1 D0 N2_LS [19:16] R R/W Reset value = 1100 0000 Bit Name 7:5 N2_HS [2:0] Function N2_HS [2:0]. Sets value for N2 high speed divider, which drives N2_LS low-speed divider. 000: 4 001: 5 010: 6 011: 7 100: 8 101: 9 110: 10 111: 11 4 3:0 Reserved N2_LS [19:16] N2_LS [19:16]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2^20 Valid divider values = [2, 4, 6, ..., 2^20] Rev. 1.0 37 Si5327 Register 41. Bit D7 D6 D5 D4 D3 Name N2_LS [15:8] Type R/W D2 D1 D0 D1 D0 Reset value = 0000 0000 Bit 7:0 Name Function N2_LS [15:8] N2_LS [15:8]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2^20 Valid divider values = [2, 4, 6, ..., 2^20] Register 42. Bit D7 D6 D5 D4 D3 Name N2_LS [7:0] Type R/W D2 Reset value = 1111 1001 Bit Name 7:0 N2_LS [7:0] Function N2_LS [7:0]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 = 2^20 Valid divider values = [2, 4, 6, ..., 2^20] 38 Rev. 1.0 Si5327 Register 43. Bit D7 D6 D5 D4 D3 D2 Name D1 D0 N31 [18:16] Type R R R R R R/W Reset value = 0000 0000 Bit Name 7:3 Reserved 2:0 N31 [18:16] Function N31 [18:16]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, 2, 3, ..., 2^19] Register 44. Bit D7 D6 D5 D4 D3 Name N31_[15:8] Type R/W D2 D1 D0 Reset value = 0000 0000 Bit Name 7:0 N31_[15:8] Function N31_[15:8]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, 2, 3, ..., 2^19] Rev. 1.0 39 Si5327 Register 45. Bit D7 D6 D5 D4 D3 Name N31_[7:0] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 0000 1001 Bit Name 7:0 N31_[7:0 Function N31_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, 2, 3, ..., 2^19] Register 46. Bit D7 D6 D5 D4 D3 Name Type N32_[18:16] R R/W Reset value = 0000 0000 Bit Name 7:3 Reserved 2:0 N32_[18:16] Function N32_[18:16]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, 2, 3, ..., 2^19] 40 Rev. 1.0 Si5327 Register 47. Bit D7 D6 D5 D4 D3 Name N32[15:8] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 0000 0000 Bit Name 7:0 N32_[15:8] Function N32[15:8]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, 2, 3, ..., 2^19] Register 48. Bit D7 D6 D5 D4 D3 Name N32[7:0] Type R/W Reset value = 0000 1001 Bit Name 7:0 N32_[7:0] Function N32[7:0]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, 2, 3, ..., 2^19] Rev. 1.0 41 Si5327 Register 128. Bit D7 D6 D5 D4 D3 D2 Name Type D1 D0 CK2_ACTV_REG CK1_ACTV_REG R R R R R R R R Reset value = 0010 0000 Bit Name Function 7:2 Reserved 1 CK2_ACTV_REG CK2_ACTV_REG. Indicates if CKIN2 is currently the active clock for the PLL input. 0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1. 1: CKIN2 is the active input clock. 0 CK1_ACTV_REG CK1_ACTV_REG. Indicates if CKIN1 is currently the active clock for the PLL input. 0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1. 1: CKIN1 is the active input clock. Register 129. Bit D7 D6 D5 D4 D3 Name Type R R R R R D2 D1 D0 LOS2_INT LOS1_INT LOSX_INT R R R Reset value = 0000 0110 Bit Name 7:3 Reserved 2 LOS2_INT Function LOS2_INT. Indicates the LOS status on CKIN2. 0: Normal operation. 1: Internal loss-of-signal alarm on CKIN2 input. 1 LOS1_INT LOS1_INT. Indicates the LOS status on CKIN1. 0: Normal operation. 1: Internal loss-of-signal alarm on CKIN1 input. 0 LOSX_INT LOSX_INT. Indicates the LOS status of the external reference on the XA/XB pins. 0: Normal operation. 1: Internal loss-of-signal alarm on XA/XB reference clock input. 42 Rev. 1.0 Si5327 Register 130. Bit D7 D6 D5 D4 D3 D2 D1 Name Type D0 LOL_INT R R R R R R R R Reset value = 0000 0001 Bit Name 7:1 Reserved 0 LOL_INT Function PLL Loss of Lock Status. 0: PLL locked. 1: PLL unlocked. Rev. 1.0 43 Si5327 Register 131. Bit D7 D6 D5 D4 D3 Name Type D2 D1 D0 LOS2_FLG LOS1_FLG LOSX_FLG R R R R R R/W R/W R/W Reset value = 0001 1111 Bit Name 7:3 Reserved 2 LOS2_FLG Function CKIN2 Loss-of-Signal Flag. 0: Normal operation. 1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to this bit. 1 LOS1_FLG CKIN1 Loss-of-Signal Flag. 0: Normal operation 1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOS1_MSK bit. Flag cleared by writing 0 to this bit. 0 LOSX_FLG External Reference (signal on pins XA/XB) Loss-of-Signal Flag. 0: Normal operation 1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to this bit. 44 Rev. 1.0 Si5327 Register 132. Bit D7 D6 D5 D4 D3 D2 Name Type D1 D0 LOL_FLG R R R R R R R/W R Reset value = 0000 0010 Bit Name 7:2 Reserved 1 LOL_FLG Function PLL Loss of Lock Flag. 0: PLL locked 1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to this bit. 0 Reserved Register 134. Bit D7 D6 D5 D4 D3 Name PARTNUM_RO [11:4] Type R D2 D1 D0 Reset value = 0000 0001 Bit Name 7:0 PARTNUM_ RO [11:0] Function Device ID (1 of 2). 0000 0001 1011: Si5327 Rev. 1.0 45 Si5327 Register 135. Bit D7 D6 D5 D4 D3 D2 D1 Name PARTNUM_RO [3:0] REVID_RO [3:0] Type R R D0 Reset value = 1011 0010 Bit 7:4 Name Function PARTNUM_RO [11:0] Device ID (2 of 2). 0000 0001 1011: Si5327 3:0 REVID_RO [3:0] Device Revision. 0000: Revision A 0001: Revision B 0010: Revision C Others: Reserved Register 136. Bit D7 D6 Name RST_REG ICAL Type R/W R/W D5 D4 D3 D2 D1 D0 R R R R R R Reset value = 0000 0000 Bit Name 7 RST_REG Function Internal Reset (Same as Pin Reset). Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted. 0: Normal operation. 1: Reset of all internal logic. Outputs disabled or tristated during reset. 6 ICAL Start an Internal Calibration Sequence. For proper operation, the device must go through an internal calibration sequence. ICAL is a self-clearing bit. Writing a “1” to this location initiates an ICAL. The calibration is complete once the LOL alarm goes low. 0: Normal operation. 1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibration, LOL will go low. Notes: 1. A valid stable clock (within 100 ppm) must be present to begin ICAL. 2. If the input changes by more than 500 ppm, the part may do an autonomous ICAL. 3. See Table 9, “Register Locations Requiring ICAL,” on page 53 for register changes that require an ICAL. 5:0 46 Reserved Rev. 1.0 Si5327 Register 137. Bit D7 D6 D5 D4 D3 D2 D1 FASTLOCK Name Type D0 R R R R R R R R/W Reset value = 0000 0000 Bit Name 7:1 Reserved 0 FASTLOCK Function Do not modify. This bit must be set to 1 to enable FASTLOCK. This improves initial lock time by dynamically changing the loop bandwidth. Register 138. Bit D7 D6 D5 D4 D3 D2 Name Type R R R R R D1 D0 LOS2_EN LOS1_EN R/W R/W R Reset value = 0000 1111 Bit Name 7:2 Reserved 1 LOS2_EN Function Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split between two registers. 00: Disable LOS monitoring 01: Reserved 10: Enable LOSA monitoring 11: Enable LOS monitoring LOSA is a slower and less sensitive version of LOS. SEe the Si53xx Family Reference Manual for details. 0 LOS1_EN Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2). Note: LOS1_EN is split between two registers. 00: Disable LOS monitoring 01: Reserved 10: Enable LOSA monitoring 11: Enable LOS monitoring LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Reference Manual for details. Rev. 1.0 47 Si5327 Register 139. Bit D7 D6 Name Type R R D5 D4 LOS2_EN LOS1_EN R/W R/W D3 D2 D1 D0 R R R R Reset value = 1111 1111 Bit Name 7:6 Reserved 5 LOS2_EN Function Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split between two registers. 00: Disable LOS monitoring 01: Reserved 10: Enable LOSA monitoring 11: Enable LOS monitoring LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Reference Manual for details 4 LOS1_EN Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2). Note: LOS1_EN is split between two registers. 00: Disable LOS monitoring 01: Reserved 10: Enable LOSA monitoring 11: Enable LOS monitoring LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Reference Manual for details. 3:0 48 Reserved Rev. 1.0 Si5327 CKOUT1+ CKOUT1– NC GND NC VDD CKOUT2– CKOUT2+ CMODE 7. Pin Descriptions: Si5327 36 35 34 33 32 31 30 29 28 RST 1 27 SDI NC 2 26 A2_SS INT_LOS1 3 25 A1 LOS2 4 VDD 5 XA 6 XB 7 24 A0 GND Pad 23 SDA_SDO 22 SCL 21 CKSEL GND 8 20 NC NC 9 19 NC LOL CKIN1– GND CKIN1+ NC CKIN2– CKIN2+ VDD RATE 10 11 12 13 14 15 16 17 18 Pin # Pin Name I/O Signal Level Description 1 RST I LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are tristated during reset. The part must be programmed after a reset or power on to get a clock output. See the Si53xx Family Reference Manual for details. This pin has a weak pull-up. 2, 9, 14, 19, 20, 30, 33 NC 3 INT_LOS1 No Connection. Leave floating. Make no external connections to this pin for normal operation. O LVCMOS Interrupt/CKIN1 LOS Indicator. This pin functions as a device interrupt output or an alarm output for CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit. If used as an alarm output, the pin functions as a LOS alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and INT_PIN = 0. 0 = CKIN1 present 1 = LOS on CKIN1 The active polarity is controlled by CK_BAD_POL. If no function is selected, the pin tristates. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”. Rev. 1.0 49 Si5327 Pin # Pin Name I/O Signal Level Description 4 LOS2 O LVCMOS 5, 10, 32 VDD VDD Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should also be placed as close to the device as is practical. 7 6 XB XA I Analog External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. Refer to the Si53xx Family Reference Manual for interfacing to an external reference. External reference must be from a high-quality clock source (TCXO, OCXO). Accepts 37–41 MHz crystal or reference clock, as determine by the RATE pin setting. 8, 15, 31 GND GND Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. Grounding these pins does not eliminate the requirement to ground the GND PAD on the bottom of the package. 11 RATE I 3-Level External Crystal or Reference Clock Rate. Three level input that selects an external crystal or reference clock to be applied to the XA/XB interface. L setting (GND) = crystal on XA/XB M setting (VDD/2) = clock or XO on XA/XB H setting (VDD) = reserved Some designs may require an external resistor voltage divider when driven by an active device that will tristate. 16 17 CKIN1+ CKIN1– I Multi Clock Input 1. Differential input clock. This input can also be driven with a singleended signal. Input frequency range is 2 kHz to 710 MHz. 12 13 CKIN2+ CKIN2– I Multi Clock Input 2. Differential input clock. This input can also be driven with a singleended signal. Input frequency range is 2 kHz to 710 MHz. CKIN2 Invalid Indicator. This pin functions as a LOS alarm indicator for CKIN2 if CK2_BAD_PIN = 1. 0 = CKIN2 present 1 = LOS on CKIN2 The active polarity can be changed by CK_BAD_POL. If CK2_BAD_PIN = 0, the pin tristates. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”. 50 Rev. 1.0 Si5327 Pin # Pin Name I/O Signal Level Description 18 LOL O LVCMOS PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator if the LOL_PIN register bit is set to 1. 0 = PLL locked 1 = PLL unlocked If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the LOL_POL bit. The PLL lock status will always be reflected in the LOL_INT read only register bit. 21 CKSEL I LVCMOS Input Clock Select. This pin functions as the manual input clock selector. 0 = Select CKIN1 1 = Select CKIN2 CKSEL should not be left open and should be driven to either logic high or logic low. 22 SCL I LVCMOS Serial Clock. This pin functions as the serial clock input for both SPI and I2C modes. This pin has a weak pull-down. 23 SDA_SDO I/O LVCMOS Serial Data. In I2C control mode (CMODE = 0), this pin functions as the bidirectional serial data port. In SPI control mode (CMODE = 1), this pin functions as the serial data output. 25 24 A1 A0 I LVCMOS Serial Port Address. In I2C control mode (CMODE = 0), these pins function as hardware controlled address bits. The I2C address is 1101 [A2] [A1] [A0]. In SPI control mode (CMODE = 1), these pins are ignored. These pins have a weak pull-down. 26 A2_SS I LVCMOS Serial Port Address/Slave Select. In I2C control mode (CMODE = 0), this pin functions as a hardware controlled address bit [A2]. In SPI control mode (CMODE = 1), this pin functions as the slave select input. This pin has a weak pull-down. 27 SDI I LVCMOS Serial Data In. In I2C control mode (CMODE = 0), this pin is ignored. In SPI control mode (CMODE = 1), this pin functions as the serial data input. This pin has a weak pull-down. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”. Rev. 1.0 51 Si5327 Pin # Pin Name I/O Signal Level Description 29 28 CKOUT1– CKOUT1+ O Multi Output Clock 1. Differential output clock with a frequency range of 2 kHz to 808 MHz. Output signal format is selected by SFOUT1_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 34 35 CKOUT2– CKOUT2+ O Multi Output Clock 2. Differential output clock with a frequency range of 2 kHz to 808 MHz. Output signal format is selected by SFOUT2_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 36 CMODE I LVCMOS Control Mode. Selects I2C or SPI control mode for the Si5327. 0 = I2C Control Mode 1 = SPI Control Mode This pin must not be NC. Tie either high or low. See the Si53xx Family Reference Manual for details on I2C or SPI operation. GND PAD GND GND Supply Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”. 52 Rev. 1.0 Si5327 Table 9 lists all of the register locations that should be followed by an ICAL after their contents are changed. Table 9. Register Locations Requiring ICAL Addr Register 0 BYPASS_REG 0 CKOUT_ALWAYS_ON 2 BWSEL_REG 4 HIST_DEL 5 ICMOS 9 HIST_AVG 10 DSBL2_REG 10 DSBL1_REG 11 PD_CK2 11 PD_CK1 19 VALTIME 19 LOCKT 25 N1_HS 31 NC1_LS 34 NC2_LS 40 N2_HS 40 N2_LS 43 N31 46 N32 Table 10. Si5327 Internal Pull up/Pull down Pin # Si5327 Pull up/ Pull down 1 RST U 11 RATE U, D 21 CKSEL U, D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U, D Rev. 1.0 53 Si5327 8. Ordering Guide Ordering Part Number Output Clock Frequency Range Package ROHS6, Pb-Free Temperature Si5327B-C-GM 2 kHz–808 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C Si5327C-C-GM 2 kHz–346 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C Si5327D-C-GM 2 kHz–243 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C Si5327-EVB Evaluation Board Note: Add an R at the end of the device to denote tape and reel options. 54 Rev. 1.0 Si5327 9. Package Outline: 36-Pin QFN Figure 8 illustrates the package details for the Si5327. Table 11 lists the values for the dimensions shown in the illustration. Figure 8. 36-Pin Quad Flat No-lead (QFN) Table 11. Package Dimensions Symbol Millimeters Symbol Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 b 0.18 0.25 D D2 Min Nom Max L 0.50 0.60 0.70 0.05 — — 12º 0.30 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 6.00 BSC 3.95 4.10 Millimeters 4.25 e 0.50 BSC ddd — — 0.10 E 6.00 BSC eee — — 0.05 E2 3.95 4.10 4.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 55 Si5327 10. Recommended PCB Layout Figure 9. PCB Land Pattern Diagram Figure 10. Ground Pad Recommended Layout 56 Rev. 1.0 Si5327 Table 12. PCB Land Pattern Dimensions Dimension MIN MAX e 0.50 BSC. E 5.42 REF. D 5.42 REF. E2 4.00 4.20 D2 4.00 4.20 GE 4.53 — GD 4.53 — X — 0.28 Y 0.89 REF. ZE — 6.31 ZD — 6.31 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Card Assembly 10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 57 Si5327 11. Si5327 Device Top Mark Mark Method: Laser Font Size: 0.80 mm Right-Justified Line 1 Marking: Si5327Q Customer Part Number Q = Speed Code: B, C, D See Ordering Guide for options Line 2 Marking: C-GM C = Product Revision G = Temperature Range –40 to 85 °C (RoHS6) M = QFN Package Line 3 Marking: YYWWRF YY = Year WW = Work Week R = Die Revision F = Internal code Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Line 4 Marking: Pin 1 Identifier Circle = 0.75 mm Diameter Lower-Left Justified XXXX Internal Code 58 Rev. 1.0 Si5327 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.4 Updated Table 3, “AC Specifications,” on page 9. Added table note. Updated Table 5, “Jitter Generation,” on page 14. Updated maximum jitter generation specifications. Revision 0.4 to Revision 1.0 Minor changes to Table 2 on page 5 Minor changes to Table 4 on page 12 Added maximum lock and settle time specs to Table 3. Fixed typos in description of Register 10 on page 28. Fixed typos in description of Register 48 on page 41. Added warning about MEMS oscillators to "4.1." on page 20. Rev. 1.0 59 Si5327 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 60 Rev. 1.0