Si5316 P RECISION C L O C K J I T T E R A TTENUATOR Features The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC-192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitterattenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 15% higher than nominal SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range. The Si5316 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5316 is ideal for providing jitter attenuation in high performance timing applications. Rev. 1.0 7/12 Copyright © 2012 by Silicon Laboratories NC NC 1 27 CK2DIV NC 2 26 CK1DIV C1B 3 25 FRQSEL C2B 4 VDD 5 XA 6 XB 7 GND 8 20 GND NC 9 19 GND 24 FRQSEL0 GND Pad 23 BWSEL1 22 BWSEL0 21 CS 10 11 12 13 14 15 16 17 18 LOL Description 36 35 34 33 32 31 30 29 28 RST CKIN1– ITU G.709 line cards Wireless basestations Test and measurement Synchronous Ethernet CKIN1+ Optical modules SONET/SDH OC-48/OC-192/ STM-16/STM-64 line cards 10GbE, 10GFC line cards VDD SFOUT1 NC Applications VDD Si5316 GND Pin Assignments RATE1 Ordering Information: See page 20. SFOUT0 DBL_BY CKOUT– Integrated loop filter with selectable loop bandwidth (100 Hz–7.9 kHz) Meets OC-192 GR-253-CORE jitter specifications CKIN2– Dual clock inputs with integrated clock select mux One clock input can be 1x, 4x, or 32x the frequency of the second clock input Single clock output with selectable signal format: LVPECL, LVDS, CML, CMOS LOL, LOS alarm outputs Pin programmable settings On-chip voltage regulator for 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10% operation Small size (6 x 6 mm 36-lead QFN) Pb-free, RoHS compliant CKOUT+ CKIN2+ Fixed frequency jitter attenuator with selectable clock ranges at 19, 38, 77, 155, 311, and 622 MHz (710 MHz max) Support for SONET, 10GbE, 10GFC, and corresponding FEC rates Ultra-low jitter clock output with jitter generation as low as 0.3 psRMS (50 kHz–80 MHz) RATE0 Patents pending Si5316 Si5316 Functional Block Diagram Xtal or Refclock CK1DIV Signal Format CKIN1 DSPLL ® CK2DIV CKIN2 Loss of Signal Disable VDD (1.8, 2.5, or 3.3 V) Signal Detect GND Clock Select 2 CKOUT Frequency Bandwidth Select Select Rev. 1.0 Loss of Lock PLL Bypass Si5316 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Phase Noise Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. Typical Applications Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. Pin Descriptions: Si5316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. Package Outline: 36-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1. Si5316 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Rev. 1.0 3 Si5316 1. Electrical Specifications Table 1. Recommended Operating Conditions (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Symbol Test Condition Min Typ Max Unit –40 25 85 ºC 3.3 V nominal 2.97 3.3 3.63 V 2.5 V nominal 2.25 2.5 2.75 V 1.8 V nominal 1.71 1.8 1.89 V TA VDD Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. Table 2. DC Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units Supply Current (Supply current is independent of VDD) IDD LVPECL Format 622.08 MHz Out — 217 243 mA CMOS Format 19.44 MHz Out — 194 220 mA 1.8 V ±5% 0.9 — 1.4 V 2.5 V ±10% 1.0 — 1.7 V 3.3 V ±10% 1.1 — 1.95 V Single-ended 20 40 60 k 0 — VDD V fCKIN < 212.5 MHz See Figure 6. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 6. 0.25 — — VPP fCKIN < 212.5 MHz See Figure 6. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 6. 0.25 — — VPP CKIN Input Pins Input Common Mode Voltage (Input Threshold Voltage) Input Resistance Input Voltage Level Limits Single-ended Input Voltage Swing Differential Input Voltage Swing VICM CKNRIN CKNVIN VISE VID See note 2 Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 10. In most designs, an external resistor voltage divider is recommended. 4 Rev. 1.0 Si5316 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units CKOVCM LVPECL 100 load line-to-line VDD – 1.42 — VDD – 1.25 V Differential Output Swing CKOVD LVPECL 100 load line-to-line 1.1 — 1.9 VPP Single-ended Output Swing CKOVSE LVPECL 100 load line-to-line 0.5 — 0.93 VPP Differential Output Voltage CKOVD CML 100 load line-to-line 350 425 500 mVPP Common Mode Output Voltage CKOVCM CML 100 load line-to-line — VDD – 0.36 — V Differential Output Voltage CKOVD LVDS 100 load line-to-line 500 700 900 mVPP Low swing LVDS 100 load line-to-line 350 425 500 mVPP CKOVCM LVDS 100 load line-to-line 1.125 1.2 1.275 V CKORD CML, LVDS, LVPECL — 200 — Output Voltage Low CKOVOLLH CMOS — — 0.4 V Output Voltage High CKOVOHLH VDD = 1.71 V CMOS 0.8 x VDD — — V Output Drive Current CKOIO CMOS Driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally. VDD = 1.8 V — 7.5 — mA VDD = 3.3 V — 32 — mA Output Clock (CKOUT)1 Common Mode Common Mode Output Voltage Differential Output Resistance Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 10. In most designs, an external resistor voltage divider is recommended. Rev. 1.0 5 Si5316 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units VIL VDD = 1.71 V — — 0.5 V VDD = 2.25 V — — 0.7 V VDD = 2.97 V — — 0.8 V VDD = 1.89 V 1.4 — — V VDD = 2.25 V 1.8 — — V VDD = 3.63 V 2.5 — — V 2-Level LVCMOS Input Pins Input Voltage Low Input Voltage High VIH Input Low Current IIL — — 50 µA Input High Current IIH — — 50 µA Weak Internal Input Pull-up Resistor RPUP — 75 — k Weak Internal Input Pull-down Resistor RPDN — 75 — k Input Voltage Low VILL — — 0.15 x VDD V Input Voltage Mid VIMM 0.45 x VDD — 0.55 x VDD V Input Voltage High VIHH 0.85 x VDD — — V Input Low Current IILL3 –20 — — µA Input Mid Current 3 –2 — 2 µA 3 — — 20 µA 3-Level Input Pins Input High Current IIMM IIHH Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 10. In most designs, an external resistor voltage divider is recommended. 6 Rev. 1.0 Si5316 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units VOL IO = 2 mA VDD = 1.71 V — — 0.4 V IO = 2 mA VDD = 2.97 V — — 0.4 V IO = –2 mA VDD = 1.71 V VDD – 0.4 — — V IO = –2 mA VDD = 2.97 V VDD – 0.4 — — V RST = 0 –100 — 100 µA — 12 — k 0 — 1.2 V 0.5 — 1.2 VPP — 12 — k 0 — 1.2 V 0.5 — 2.4 VPP LVCMOS Output Pins Output Voltage Low Output Voltage High VOH Disabled Leakage Current IOZ Single-Ended Reference Clock Input Pin XA (XB with cap to gnd) Input Resistance XARIN Input Voltage Level Limits XAVIN Input Voltage Swing XAVPP XTAL/RefCLK RATE[1:0] = LM, ML, MH, or HM Differential Reference Clock Input Pins (XA/XB) Input Resistance XA/XBRIN Differential Input Voltage Level Limits XA/XBVIN Input Voltage Swing XTAL/RefCLK RATE[1:0] = LM, ML, MH, or HM XAVPP/XBVPP Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 10. In most designs, an external resistor voltage divider is recommended. V SIGNAL + Differential I/Os VICM , VOCM SIGNAL – VISE , VOSE Single-Ended Peak-to-Peak Voltage (SIGNAL +) – (SIGNAL –) Differential Peak-to-Peak Voltage VID,VOD VICM, VOCM t SIGNAL + VID = (SIGNAL+) – (SIGNAL–) SIGNAL – Figure 1. Voltage Characteristics Rev. 1.0 7 Si5316 Table 3. AC Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units CKF FRQSEL[1:0] = LL FRQSEL[1:0] = LM FRQSEL[1:0] = LH FRQSEL[1:0] = ML FRQSEL[1:0] = MM FRQSEL[1:0] = MH 19.38 38.75 77.5 155.0 310.0 620.0 — — — — — — 22.28 44.56 89.13 178.25 356.5 710.0 MHz Whichever is smaller (i.e., the 40%/60% limitation applies only to high clock frequencies) 40 — 60 % 2 — — ns — — 3 pF — — 11 ns — — 212.5 MHz CMOS Output VDD = 1.71 Cload = 5 pF — — 8 ns CMOS Output VDD = 2.97 Cload = 5 pF — — 2 ns CKIN Input Pins Input/Output Clock Frequency (CKIN1, CKIN2, CKOUT) Input Duty Cycle (Minimum Pulse Width) CKNDC Input Capacitance CKNCIN Input Rise/Fall Time CKNTRF 20–80% See Figure 6 CKOUT Output Pins Maximum Output Frequency in CMOS Format CKOFMC Single-ended Output Rise/Fall (20–80%) CKOTRF Differential Output Rise/Fall Time CKOTRF 20 to 80 %, fOUT = 622.08 — 230 350 ps Output Duty Cycle Differential Uncertainty CKODC 100 Load Line to Line Measured at 50% Point (not for CMOS) — — ±40 ps tRSTMIN 1 — — µs CIN — — 3 pF — 25 — ns — 750 µs LVCMOS Input Pins Minimum Reset Pulse Width Input Capacitance LVCMOS Output Pins Rise/Fall Times LOSn Trigger Window tRF CLOAD = 20 pf See Figure 6 LOSTRIG From last CKIN to LOS *Note: Input to output skew is not controlled and can assume any value. 8 Rev. 1.0 Si5316 Table 3. AC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Time to Clear LOL after LOS Cleared tCLRLOL Test Condition Min Typ Max Units fin unchanged and XA/XB stable. LOS to LOL — 10 — ms PLL Performance Lock Time tLOCKHW Whenever RST, FRQTBL, RATE, BWSEL, or FRQSEL are changed, with valid CKIN to LOL; BW = 100 Hz — 0.035 1.2 sec Output Clock Phase Change tP_STEP After clock switch f3 128 kHz — 200 — ps — 0.05 0.1 dB Closed Loop Jitter Peaking JPK Jitter Tolerance Spurious Noise Phase Change due to Temperature Variation* JTOL BW determined by BWSEL[1:0] 5000/ BW — — ns pkpk SPSPUR Max spur @ n x f3 (n > 1, n x f3 < 100 MHz) — –93 –70 dBc tTEMP Max phase changes from – 40 to +85 ºC — 300 500 ps *Note: Input to output skew is not controlled and can assume any value. 80% CKIN, CKOUT 20% tF tR Figure 2. Rise/Fall Time Characteristics Rev. 1.0 9 Si5316 Table 4. Three-Level Input Pins1,2,3,4 Parameter Min Max Input Low Current –30 µA — Input Mid Current –11 µA –11 µA Input High Current — –30 µA Notes: 1. The current parameters are the amount of leakage that the 3L inputs can tolerate from an external driver using the external resistor values indicated in this example. In most designs, an external resistor voltage divider is recommended. 2. Resistor packs are only needed if the leakage current of the external driver exceeds the current specified in Table 2. Any resistor pack may be used (e.g., Panasonic EXB-D10C183J). PCB layout is not critical. 3. If a pin is tied to ground or VDD, no resistors are needed. 4. If a pin is left open (no connect), no resistors are needed. Si5316 VDD 75 k Iimm 75 k External Driver Figure 3. Three-Level (3L) Input Pins (No External Resistors) V DD 18 k 75 k 18 k 75 k 3L input current External Driver V DD Si5316 One of eight resistors from a Panasonic EXB-D10C183J (or similar) resistor pack Figure 4. Three-Level Input Pins (Example with External Resistors) 10 Rev. 1.0 Si5316 Table 5. Performance Specifications1, 2, 3, 4, 5 (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit Jitter Generation fIN = fOUT = 622.08 MHz, LVPECL Output Format BW = 120 Hz JGEN 50 kHz–80 MHz — 0.27 0.42 ps rms 12 kHz–20 MHz — 0.25 0.41 ps rms 800 Hz–80 MHz — 0.28 0.45 ps rms Phase Noise fIN = fOUT = 622.08 MHz LVPECL Output Format CKOPN 1 kHz offset — –106 — dBc/Hz 10 kHz offset — –121 — dBc/Hz 100 kHz offset — –122 — dBc/Hz 1 MHz offset — –132 — dBc/Hz Notes: 1. BWSEL [1:0] loop bandwidth settings provided in “Si53xx-RM: Any-Frequency Precision Clocks Si53xx Family Reference Manual.” 2. 114.285 MHz 3rd OT crystal used as XA/XB input. 3. VDD = 2.5 V 4. TA = 85 °C 5. Test condition: fIN = 622.08 MHz, fOUT = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20-80%), LVPECL clock output. Table 6. Thermal Conditions (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit Thermal Resistance Junction to Ambient JA Still Air — 32 — ºC/W Thermal Resistance Junction to Case JC Still Air — 14 — ºC/W Rev. 1.0 11 Si5316 Table 7. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 3.8 V LVCMOS Input Voltage VDIG –0.3 to (VDD + 0.3) V CKINn Voltage Level Limits CKNVIN 0 to VDD V XA/XB Voltage Level Limits XAVIN 0 to 1.2 V Operating Junction Temperature TJCT –55 to 150 C Storage Temperature Range TSTG –55 to 150 C 2 kV ESD MM Tolerance; All pins except CKIN+/CKIN– 150 V ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN– 750 V ESD MM Tolerance; CKIN+/CKIN– 100 V ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– Latch-Up Tolerance JESD78 Compliant Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 12 Rev. 1.0 Si5316 2. Typical Phase Noise Plot The following is the typical phase noise performance of the Si5316. The clock input source was a Rohde and Schwarz model SML03 RF Generator. The phase noise analyzer was an Agilent model E5052B. The Si5316 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by the jitter at the input clock. The loop BW was 120 Hz. 2.1. Example: SONET OC-192 Figure 5. Typical Phase Noise Plot Jitter Band Jitter, RMS SONET_OC48, 12 kHz to 20 MHz 250 fs SONET_OC192_A, 20 kHz to 80 MHz 274 fs SONET_OC192_B, 4 to 80 MHz 166 fs SONET_OC192_C, 50 kHz to 80 MHz 267 fs Brick Wall, 800 Hz to 80 MHz 274 fs Note: SONET jitter bands include the SONET skirts. The phase noise plot is brick wall integration. Rev. 1.0 13 Si5316 3. Typical Applications Schematic C4 1 µF System Power Supply C3 0.1 µF Ferrite Bead C2 0.1 µF VDD = 3.3 V C1 0.1 µF 130 CKIN1– 82 GND PAD GND CKIN1+ VDD 130 0.1 µF CKOUT+ + CKOUT– 82 Clock Output 100 – 0.1 µF Input Clock Sources1 VDD = 3.3 V 130 130 CKIN2+ CKIN2– 82 82 Option 1: C1B CKIN_1 Loss of Signal C2B CKIN_2 Loss of Signal LOL PLL Loss of Lock Indicator XA Crystal (114.285 MHz) XB Si5316 0.1 µF Option 2: Refclk+ XA 0.1 µF XB Refclk– VDD 15 k RATE[1:0]2 Crystal/Ref Clk Rate 15 k Input Clock Select CS VDD 15 k Input Clock 1 Pre-Divider Select Input Clock 2 Pre-Divider Select 15 k VDD 15 k Frequency Select 15 k Signal Format Select 15 k Clock Output Disable/ Bypass Mode Control Reset CK2DIV2 15 k FRQSEL[1:0]2 VDD 15 k Bandwidth Select CK1DIV2 VDD 15 k 15 k VDD BWSEL[1:0]2 15 k SFOUT[1:0]2 VDD 15 k DBL_BY2 15 k RST Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes 3-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). Figure 6. Si5316 Typical Application Circuit 14 Rev. 1.0 Si5316 4. Functional Description 4.1. External Reference The Si5316 is a precision jitter attenuator for high-speed communication systems, including OC-48/STM-16, OC192/STM-64, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 15% higher than nominal SONET/ SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range. The Si5316 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. For applications which require input clocks at different frequencies, the frequency of CKIN1 can be 1x, 4x, or 32x the frequency of CKIN2 as specified by the CK1DIV and CK2DIV inputs. The Si5316 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 100 Hz to 7.9 kHz. To calculate potential loop bandwidth values for a given input/output clock frequency, Silicon Laboratories offers a PC-based software utility, DSPLLsim, that calculates valid loop bandwidth settings automatically. This utility can be downloaded from http:// www.silabs.com/timing. An external, 38.88 MHz clock or a low-cost 114.285 MHz 3rd overtone crystal is used as part of a fixed-frequency oscillator within the DSPLL. This external reference is required for the device to operate. Silicon Laboratories recommends using a high quality crystal. Specific recommendations may be found in the Family Reference Manual. An external 38.88 MHz clock from a high quality OCXO or TCXO can also be used as a reference for the device. In digital hold, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference when the DSPLL is in digital hold will be tracked by the output of the device. Note that crystals can have temperature sensitivities. 4.2. Further Documentation Consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailed information about the Si5316. Additional design support is available from Silicon Laboratories through your distributor. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from http://www.silabs.com/timing. The Si5316 supports manual active input clock selection. The Si5316 monitors both input clocks for loss-of-signal and provides a LOS alarm when it detects missing pulses on either input clock. Hitless switching is not supported by the Si5316. During a clock transition, the phase of the output clock will slew at a rate defined by the PLL loop bandwidth until the original input clock phase to output clock phase is restored. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The Si5316 has one differential clock output. The electrical format of the clock output is programmable to support LVPECL, LVDS, CML, or CMOS loads. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply. Rev. 1.0 15 Si5316 NC NC SFOUT1 VDD GND SFOUT0 CKOUT– CKOUT+ NC 5. Pin Descriptions: Si5316 36 35 34 33 32 31 30 29 28 RST 1 27 CK2DIV NC 2 26 CK1DIV C1B 3 25 FRQSEL1 C2B 4 VDD 5 XA 6 XB 7 GND 8 20 GND NC 9 19 GND 24 FRQSEL0 GND Pad 23 BWSEL1 22 BWSEL0 21 CS LOL CKIN1– CKIN1+ RATE1 DBL_BY CKIN2– CKIN2+ VDD RATE0 10 11 12 13 14 15 16 17 18 Table 8. Si5316 Pin Descriptions Pin # 1 Pin Name 2, 9, 28, 29, 36 NC 3 C1B O 4 C2B O 5, 10, 32 VDD VDD RST I/O I Signal Level Description LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5316 will perform an internal self-calibration when a valid signal is present. This pin has a weak pull-up. No Connection. Leave floating. Make no external connection to this pin for normal operation. LVCMOS CKIN1 Loss of Signal. Active high Loss-of-signal indicator for CKIN1. Once triggered, the alarm will remain active until CKIN1 is validated. 0 = CKIN1 present 1 = LOS on CKIN1 LVCMOS CKIN2 Loss of Signal. Active high Loss-of-signal indicator for CKIN2. Once triggered, the alarm will remain active until CKIN2 is validated. 0 = CKIN2 present 1 = LOS on CKIN2 Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should also be placed as close to device as is practical. *Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD). 16 Rev. 1.0 Si5316 Table 8. Si5316 Pin Descriptions (Continued) Pin # 7 6 Pin Name XB XA 8, 19, 20, 31 GND 11 15 RATE0 RATE1 12 13 CKIN2+ CKIN2– 14 DBL_BY 16 17 CKIN1+ CKIN1– 18 LOL I/O I Signal Level Description Analog External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. Refer to Family Reference Manual for interfacing to an external reference. External reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pins. GND Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. Grounding these pins does not eliminate the requirement to ground the GND PAD on the bottom of the package. Pins 19 and 20 may be left NC. I 3-Level* External Crystal or Reference Clock Rate. Three level inputs that select the type and rate of external crystal or reference clock to be applied to the XA/XB port. Refer to the Family Reference Manual for settings. These pins have both a weak pull-up and a weak pull-down; they default to M. The "HH" setting is not supported. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. I Multi Clock Input 2. Differential input clock. This input can also be driven with a singleended signal. I 3-Level* Output Disable/Bypass Mode Control. Controls enable of CKOUT divider/output buffer path and PLL bypass mode. L = CKOUT enabled M = CKOUT disabled H = Bypass mode with CKOUT enabled This pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Bypass mode is not supported for CMOS clock outputs. I Multi Clock Input 1. Differential input clock. This input can also be driven with a singleended signal. O LVCMOS PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator. 0 = PLL locked 1 = PLL unlocked *Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD). Rev. 1.0 17 Si5316 Table 8. Si5316 Pin Descriptions (Continued) Pin # 21 Pin Name CS I/O I 23 22 BWSEL1 BWSEL0 I 25 24 FRQSEL 1 FRQSEL 0 I 26 CK1DIV I 27 CK2DIV I Signal Level Description LVCMOS Input Clock Select. This pin functions as the input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CKSEL input state. 0 = Select CKIN1 1 = Select CKIN2 Must be driven high or low. 3-Level* Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. Detailed operations and timing characteristics for these pins may be found in the Any-Frequency Precision Clock Family Reference Manual. These pins are both pull-ups and pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 3-Level* Frequency Select. Sets the output frequency of the device. When the frequency of CKIN1 is not equal to CKIN2, the lower frequency input clock must be equal to the output clock frequency. These pins have both weak pull-ups and weak pull-downs and default to M. For the pin settings, see Table 3 on page 8. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 3-Level* Input Clock 1 Pre-Divider Select. Pre-divider on CKIN1. Used with CK2DIV to divide input clock frequencies to a common value. L = CKIN1 input divider set to 1. M = CKIN1 input divider set to 4. H = CKIN1 input divider set to 32. This pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 3-Level* Input Clock 2 Pre-Divider Select. Pre-divider on CKIN2. Used with CK1DIV to divide input clock frequencies to a common value. L = CKIN2 input divider set to 1. M = CKIN2 input divider set to 4. H = CKIN2 input divider set to 32. This pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. *Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD). 18 Rev. 1.0 Si5316 Table 8. Si5316 Pin Descriptions (Continued) Pin # 33 30 Pin Name SFOUT0 SFOUT1 I/O I Signal Level Description 3-Level* Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for CKOUT. Valid settings include LVPECL, LVDS, and CML. Also includes selections for CMOS mode, tristate mode, and tristate/sleep mode. SFOUT[1:0] 34 35 CKOUT– CKOUT+ O Multi GND PAD GND GND Supply Signal Format HH Reserved HM LVDS HL CML MH LVPECL MM Reserved ML LVDS—low swing LH CMOS LM Disabled LL Reserved These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Clock Output. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. *Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD). Rev. 1.0 19 Si5316 6. Ordering Guide Ordering Part Number Package ROHS6, Pb-Free Temperature Range Si5316-C-GM 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C Note: Add an R at the end of the device to denote tape and reel options. 20 Rev. 1.0 Si5316 7. Package Outline: 36-Lead QFN Figure 7 illustrates the package details for the Si5316. Table 9 lists the values for the dimensions shown in the illustration. Figure 7. 36-Pin Quad Flat No-lead (QFN) Table 9. Package Dimensions Symbol A Millimeters Symbol Min Nom Max 0.80 0.85 0.90 L Millimeters Min Nom Max 0.50 0.60 0.70 A1 0.00 0.02 0.05 — — 12º b 0.18 0.25 0.30 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 D D2 6.00 BSC 3.95 4.10 4.25 e 0.50 BSC ddd — — 0.10 E 6.00 BSC eee — — 0.05 E2 3.95 4.10 4.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 21 Si5316 8. Recommended PCB Layout Figure 8. PCB Land Pattern Diagram Figure 9. Ground Pad Recommended Layout 22 Rev. 1.0 Si5316 Table 10. PCB Land Pattern Dimensions Dimension MIN MAX e 0.50 BSC. E 5.42 REF. D 5.42 REF. E2 4.00 4.20 D2 4.00 4.20 GE 4.53 — GD 4.53 — X — 0.28 Y 0.89 REF. ZE — 6.31 ZD — 6.31 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Card Assembly 10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 23 Si5316 9. Top Marking 9.1. Si5316 Top Marking Figure 10. Si5316 Top Marking 9.2. Top Marking Explanation Mark Method: Laser Line 1 Marking: Si5316 Customer Part Number Line 2 Marking: C-GM C = Product Revision G = Temperature Range –40 to 85 °C (RoHS6) M = QFN Package Line 3 Marking: YYWWRF YY = Year WW = Work Week R = Die Revision F = Internal code Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Line 4 Marking: Pin 1 Identifier Circle = 0.75 mm Diameter Lower-Left Justified XXXX Internal Code 24 Rev. 1.0 Si5316 DOCUMENT CHANGE LIST Revision 0.23 to 0.24 Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 5. Added Figure 5, “Typical Phase Noise Plot,” on page 13. Showed preferred interface for an external reference clock in Figure 6, “Si5316 Typical Application Circuit,” on page 14. Updated "3. Ordering Guide" on page 11. Added “5. Recommended PCB Layout” . Revision 0.24 to Revision 0.3 Changed 1.8 V operating range ±5%. Updated Table 1 on page 4. Updated Table 2 on page 5. Updated Table 8 on page 16. Added table under Figure 5 on page 13. Updated "1. Functional Description" on page 6. Clarified "2. Pin Descriptions: Si5316" on page 7 including pull-up/pull-down. Revision 0.3 to Revision 0.4 Updated Table 1, “Performance Specifications1,” on page 4. Updated Table 8, “Si5316 Pin Descriptions,” on page 16. Updated Figure 6, “Si5316 Typical Application Circuit,” on page 14. Updated "4.1. External Reference" on page 15. Updated "2. Pin Descriptions: Si5316" on page 7. Revision 0.4 to Revision 1.0 Expanded and rearranged specification tables in section “1. Electrical Specifications” . Updated "2. Typical Phase Noise Plot" on page 13. Changed “any-rate” to “any-frequency” throughout. Added "9. Top Marking" on page 24. Added recommended ground pad drawing in "8. Recommended PCB Layout" on page 22. Rev. 1.0 25 Si5316 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 26 Rev. 1.0