Si4313 REGISTER DESCRIPTIONS

AN589
Si4313 R EGISTER D ESCRIPTIONS
1. Complete Register Summary
Function/Description
Data
D7
D6
D5
D4
D3
D2
D1
D0
POR
Defaul
R/W
Addr
Table 1. Register Descriptions
00
R
Device Type
0
0
0
dt[4]
dt[3]
dt[2]
dt[1]
dt[0]
08h
01
R
Device Version
0
0
0
vc[4]
vc[3]
vc[2]
vc[1]
vc[0]
06h
02
R
Device Status
ffovfl
ffunfl
rxffem
Reserved
Reserved
Reserved
cps[1]
cps[0]
03
R
Interrupt Status 1
ifferr
Reserved
Reserved
irxffafull
iext
Reserved
Reserved
Reserved
04
R
Interrupt Status 2
iswdet
ipreaval
ipreainval
irssi
iwut
ilbd
ichiprdy
ipor
05
R/W
Interrupt Enable 1
enfferr
Reserved
Reserved
enrxffafull
enext
Reserved
Reserved
Reserved
00h
06
R/W
Interrupt Enable 2
enswdet
enpreaval
enpreainval
enrssi
enwut
enlbd
enchiprdy
enpor
03h
07
R/W
Operating & Function Control 1
swres
enlbd
enwt
x32ksel
Reserved
rxon
pllon
xton
01h
08
R/W
Operating & Function Control 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ffclrrx
Reserved
00h
09
R/W
Crystal Oscillator Load Capacitance
xtalshft
xlc[6]
xlc[5]
xlc[4]
xlc[3]
xlc[2]
xlc[1]
xlc[0]
7Fh
0A
R/W
Microcontroller Output Clock
Reserved
Reserved
clkt[1]
clkt[0]
enlfc
mclk[2]
mclk[1]
mclk[0]
06h
0B
R/W
GPIO0 Configuration
gpio0drv[1]
gpio0drv[0]
pup0
gpio0[4]
gpio0[3]
gpio0[2]
gpio0[1]
gpio0[0]
00h
0C
R/W
GPIO1 Configuration
gpio1drv[1]
gpio1drv[0]
pup1
gpio1[4]
gpio1[3]
gpio1[2]
gpio1[1]
gpio1[0]
00h
0D
R/W
GPIO2 Configuration
gpio2drv[1]
gpio2drv[0]
pup2
gpio2[4]
gpio2[3]
gpio2[2]
gpio2[1]
gpio2[0]
00h
0E
R/W
I/O Port Configuration
Reserved
extitst[2]
extitst[1]
extitst[0]
itsdo
dio2
dio1
dio0
00h
0F
R/W
ADC Configuration
adcstart /
adcdone
adcsel[2]
adcsel[1]
adcsel[0]
adcref[1]
adcref[0]
adcgain[1]
adcgain[0]
00h
10
R/W
ADC Sensor Amplifier Offset
Reserved
Reserved
Reserved
Reserved
adcoffs[3]
adcoffs[2]
adcoffs[1]
adcoffs[0]
00h
11
R
ADC Value
adc[7]
adc[6]
adc[5]
adc[4]
adc[3]
adc[2]
adc[1]
adc[0]
12
R/W
Temperature Sensor Control
tsrange[1]
tsrange[0]
entsoffs
entstrim
tstrim[3]
tstrim[2]
tstrim[1]
tstrim[0]
20h
13
R/W
Temperature Value Offset
tvoffs[7]
tvoffs[6]
tvoffs[5]
tvoffs[4]
tvoffs[3]
tvoffs[2]
tvoffs[1]
tvoffs[0]
00h
14
R/W
Wake-Up Timer Period 1
Reserved
Reserved
Reserved
wtr[4]
wtr[3]
wtr[2]
wtr[1]
wtr[0]
03h
15
R/W
Wake-Up Timer Period 2
wtm[15]
wtm[14]
wtm[13]
wtm[12]
wtm[11]
wtm[10]
wtm[9]
wtm[8]
00h
16
R/W
Wake-Up Timer Period 3
wtm[7]
wtm[6]
wtm[5]
wtm[4]
wtm[3]
wtm[2]
wtm[1]
wtm[0]
01h
17
R
Wake-Up Timer Value 1
wtv[15]
wtv[14]
wtv[13]
wtv[12]
wtv[11]
wtv[10]
wtv[9]
wtv[8]
18
R
Wake-Up Timer Value 2
wtv[7]
wtv[6]
wtv[5]
wtv[4]
wtv[3]
wtv[2]
wtv[1]
wtv[0]
1A
R/W
Low Battery Detector Threshold
Reserved
Reserved
Reserved
lbdt[4]
lbdt[3]
lbdt[2]
lbdt[1]
lbdt[0]
1B
R
Battery Voltage Level
0
0
0
vbat[4]
vbat[3]
vbat[2]
vbat[1]
vbat[0]
1C
R/W
IF Filter Bandwidth
dwn3_
bypass
ndec[2]
ndec[1]
ndec[0]
filset[3]
filset[2]
filset[1]
filset[0]
01h
1D
R/W
AFC Loop Gearshift Override
afcbd
enafc
afcgearh[2]
afcgearh[1]
afcgearh[0]
1p5
bypass
matap
ph0size
44h
1E
R/W
AFC/ AntDiv Timing Control
swant_timer[
1]
swant_timer[0]
shwait[2]
shwait[1]
shwait[0]
anwait[2]
anwait[1]
anwait[0]
0Ah
1F
R/W
Clock Recovery Gearshift Override
Reserved
Reserved
crfast[2]
crfast[1]
crfast[0]
crslow[2]
crslow[1]
crslow[0]
03h
Rev 0.1 2/11
Copyright © 2011 by Silicon Laboratories
AN589
14h
AN589
Table 1. Register Descriptions
20
R/W
Clock Recovery Oversampling Ratio
rxosr[7]
rxosr[6]
rxosr[5]
rxosr[4]
rxosr[3]
rxosr[2]
rxosr[1]
rxosr[0]
64h
21
R/W
Clock Recovery Offset 2
rxosr[10]
rxosr[9]
rxosr[8]
skip2phth
ncoff[19]
ncoff[18]
ncoff[17]
ncoff[16]
01h
22
R/W
Clock Recovery Offset 1
ncoff[15]
ncoff[14]
ncoff[13]
ncoff[12]
ncoff[11]
ncoff[10]
ncoff[9]
ncoff[8]
47h
23
R/W
Clock Recovery Offset 0
ncoff[7]
ncoff[6]
ncoff[5]
ncoff[4]
ncoff[3]
ncoff[2]
ncoff[1]
ncoff[0]
AEh
24
R/W
Clock Recovery Timing Loop Gain 1
Reserved
Reserved
Reserved
rxncocomp
cgainx2
crgain[10]
crgain[9]
crgain[8]
02h
25
R/W
Clock Recovery Timing Loop Gain 0
crgain[7]
crgain[6]
crgain[5]
crgain[4]
crgain[3]
crgain[2]
crgain[1]
crgain[0]
8Fh
26
R
Received Signal Strength Indicator
rssi[7]
rssi[6]
rssi[5]
rssi[4]
rssi[3]
rssi[2]
rssi[1]
rssi[0]
27
R/W
RSSI Threshold for Clear Channel
Indicator
rssith[7]
rssith[6]
rssith[5]
rssith[4]
rssith[3]
rssith[2]
rssith[1]
rssith[0]
1Eh
2A
R/W
AFC Limiter
afclim[7]
afclim[6]
aAfclim[5]
afclim[4]
afclim[3]
afclim[2]
afclim[1]
afclim[0]
00h
2B
R
AFC Correction Read
afc_corr[9]
afc_corr[8]
afc_corr[7]
afc_corr[6]
afc_corr[3]
afc_corr[2]
00h
2C
R/W
OOK Counter Value 1
afc_corr[1]
afc_corr[0]
ookfrzen
peakdeten
madeten
ookcnt[10]
ookcnt[9]
ookcnt[8]
18h
2D
R/W
OOK Counter Value 2
ookcnt[7]
ookcnt[6]
ookcnt[5]
ookcnt[4]
ookcnt[3]
ookcnt[2]
ookcnt[1]
ookcnt[0]
BCh
2E
R/W
Slicer Peak Hold
reserv.
attack[2]
attack[1]
attack[0]
decay[3]
decay[2]
decay[1]
decay[0]
26h
30
R/W
FIFO config
fiforx
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8Dh
35
R/W
Preamble Detection Control
preath[4]
preath[3]
preath[2]
preath[1]
preath[0]
rssi_off[2]
rssi_off[1]
rssi_off[0]
2Ah
36
R/W
Sync Word 3
sync[31]
sync[30]
sync[29]
sync[28]
sync[27]
sync[26]
sync[25]
sync[24]
2Dh
37
R/W
Sync Word 2
sync[23]
sync[22]
sync[21]
sync[20]
sync[19]
sync[18]
sync[17]
sync[16]
D4h
38
R/W
Sync Word 1
sync[15]
sync[14]
sync[13]
sync[12]
sync[11]
sync[10]
sync[9]
sync[8]
00h
39
R/W
Sync Word 0
sync[7]
sync[6]
sync[5]
sync[4]
sync[3]
sync[2]
sync[1]
sync[0]
00h
60
R/W
Channel Filter Coefficient Address
Inv_pre_th[3]
Inv_pre_t[2]
Inv_pre_th[1]
Inv_pre_th[0]
chfiladd[3]
chfiladd[2]
chfiladd[1]
chfiladd[0]
A0h
62
R/W
Crystal Oscillator / Control Test
pwst[2]
pwst[1]
pwst[0]
clkhyst
enbias2x
enamp2x
bufovr
enbuf
04h
69
R/W
AGC Override 1
Reserved
sgin
agcen
lnagain
pga3
pga2
pga1
pga0
20h
70
R/W
Modulation Mode Control 1
Reserved
Reserved
Reserved
Reserved
manppol
enmaninv
enmanch
Reserved
0Ch
71
R/W
Modulation Mode Control 2
rxrclk[1]
rxclk[0]
dtmod[1]
dtmod[0]
eninv
fd[8]
modtyp[1]
modtyp[0]
00h
73
R/W
Frequency Offset 1
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1]
fo[0]
00h
74
R/W
Frequency Offset 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
fo[9]
fo[8]
00h
75
R/W
Frequency Band Select
Reserved
sbsel
hbsel
fb[4]
fb[3]
fb[2]
fb[1]
fb[0]
75h
76
R/W
Nominal Carrier Frequency 1
fc[15]
fc[14]
fc[13]
fc[12]
fc[11]
fc[10]
fc[9]
fc[8]
BBh
77
R/W
Nominal Carrier Frequency 0
fc[7]
fc[6]
fc[5]
fc[4]
fc[3]
fc[2]
fc[1]
fc[0]
80h
79
R/W
Frequency Hopping Channel Select
fhch[7]
fhch[6]
fhch[5]
fhch[4]
fhch[3]
fhch[2]
fhch[1]
fhch[0]
00h
7A
R/W
Frequency Hopping Step Size
fhs[7]
fhs[6]
fhs[5]
fhs[4]
fhs[3]
fhs[2]
fhs[1]
fhs[0]
00h
7E
R/W
RX FIFO Control
Reserved
Reserved
rxafthr[5]
rxafthr[4]
rxafthr[3]
rxafthr[2]
rxafthr[1]
rxafthr[0]
37h
7F
R/W
FIFO Access
fifod[7]
fifod[6]
fifod[5]
fifod[4]
fifod[3]
fifod[2]
fifod[1]
fifod[0]
2
Rev 0.1
afc_corr[5] afc_corr[4]
AN589
2. Detailed Register Descriptions
Register 00h. Device Type Code (DT)
Bit
D7
D6
D5
D4
D3
D2
Name
Reserved
dt[4:0]
Type
R
R
D1
D0
D1
D0
Reset value = 00001000
Bit
Name
7:5
Reserved
4:0
dt[4:0]
Function
Reserved.
Device Type Code.
This internally hardwired code identifies the type or family of chip.
EZRadioPRO devices = 01000 = 08h.
Register 01h. Version Code (VC)
Bit
D7
D6
D5
D4
D3
D2
Name
Reserved
vc[4:0]
Type
R
R
Reset value = xxxxxxxx
Bit
Name
7:5
Reserved
4:0
vc[4:0]
Function
Reserved.
Version Code.
This internally hardwired code identifies the chip revision. For EZRadioPRO devices, V2
revision = 00010 = 02h, A0 revision = 00100 = 04h, B1 revision = 00110 = 06h.
Rev 0.1
3
AN589
Register 02h. Device Status
Bit
D7
D6
D5
D4
D3
Name
ffovfl
ffunfl
rxffem
Reserved
cps[1:0]
Type
R
R
R
R
R
Reset value = xxxxxxxx
4
Bit
Name
Function
7
ffovfl
RX FIFO Overflow Status.
6
ffunfl
RX FIFO Underflow Status.
5
rxffem
4:2
Reserved
1:0
cps[1:0]
RX FIFO Empty Status.
Reserved.
Chip Power State.
00:
Idle State
01:
RX State
Rev 0.1
D2
D1
D0
AN589
Register 03h. Interrupt/Status 1
Bit
D7
Name
ifferr
Type
R
D6
D5
D4
D3
D2
D1
Reserved
irxffafull
iext
Reserved
R
R
R
R
D0
Reset value = xxxxxxxx
Bit
Name
Function
7
ifferr
6:5
Reserved
4
irxffafull
RX FIFO Almost Full.
When set to 1 the RX FIFO has met its almost full threshold and needs to be read by the
microcontroller.
3
iext
External Interrupt.
When set to 1 an interrupt occurred on one of the GPIO’s if it is programmed so. The status can be checked in register 0Eh. See GPIOx Configuration section for the details.
2:0
Reserved
FIFO Underflow/Overflow Error.
When set to 1 the RX FIFO has overflowed or underflowed.
Reserved.
Reserved.
When any of the Interrupt/Status 1 bits change state from 0 to 1 the device will notify the microcontroller by setting
the nIRQ pin LOW if it is enabled in the Interrupt Enable 1 register. The nIRQ pin will go to HIGH and all the
enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled
in the Interrupt Enable 1 register then it becomes a status signal that can be read anytime in the same location and
will not be cleared by reading the register.
Table 2. When Individual Status Bits are Set/Cleared if not Enabled as Interrupts
Bit
Status
Name
7
ifferr
6:5
Reserved
4
irxffafull
3
iext
2:0
Reserved
Set/Clear Conditions
Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO reset to
the specific FIFO that caused the condition.
Reserved.
Will be set when the number of bytes received (and not yet read-out) in RX FIFO is greater
than the Almost Full threshold set by SPI. It is automatically cleared when we read enough
data from RX FIFO so that the number of data bytes not yet read is below the Almost Full
threshold.
External interrupt source.
Reserved.
Rev 0.1
5
AN589
Register 04h. Interrupt/Status 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
iswdet
ipreaval
ipreainval
irssi
iwut
ilbd
ichiprdy
ipor
Type
R
R
R
R
R
R
R
R
Reset value = xxxxxxxx
Bit
Name
Function
7
iswdet
Sync Word Detected.
When a sync word is detected this bit will be set to 1.
6
ipreaval
Valid Preamble Detected.
When a preamble is detected this bit will be set to 1.
5
ipreainval
4
irssi
RSSI.
When RSSI level exceeds the programmed threshold this bit will be set to 1.
3
iwut
Wake-Up-Timer.
On the expiration of programmed wake-up timer this bit will be set to 1.
2
ilbd
Low Battery Detect.
When a low battery event has been detected this bit will be set to 1. This interrupt event
is saved even if it is not enabled by the mask register bit and causes an interrupt after it is
enabled.
1
ichiprdy
0
ipor
Invalid Preamble Detected.
When the preamble is not found within a period of time set by the invalid preamble detection threshold in Register 60h, this bit will be set to 1.
Chip Ready (XTAL).
When a chip ready event has been detected this bit will be set to 1.
Power-on-Reset (POR).
When the chip detects a Power on Reset above the desired setting this bit will be set to 1.
When any of the Interrupt/Status Register 2 bits change state from 0 to 1 the control block will notify the
microcontroller by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 2 register. The nIRQ pin will go
to HIGH and all the enabled interrupt bits will be cleared when the microcontroller reads this address. If any of
these bits is not enabled in the Interrupt Enable 2 register then it becomes a status signal that can be read anytime
in the same location and will not be cleared by reading the register.
Table 3. Detailed Description of Status Registers when not Enabled as Interrupts
6
Bit
Status
Name
Set/Clear Conditions
7
iswdet
Goes high once the Sync Word is detected. Goes low once we are done receiving the current packet.
6
ipreaval
5
ipreainval
Goes high once the preamble is detected. Goes low once the sync is detected or the RX
wait for the sync times-out.
Self clearing, user should use this as an interrupt source rather than a status.
Rev 0.1
AN589
Table 3. Detailed Description of Status Registers when not Enabled as Interrupts (Continued)
4
irssi
Should remain high as long as the RSSI value is above programmed threshold level
3
iwut
Wake time timer interrupt. Use as an interrupt, not as a status.
2
ilbd
Low Battery Detect. When a low battery event has been detected this bit will be set to 1. It
will remain set as long as the battery voltage is below the threshold but will reset if the voltage returns to a level higher than the threshold.
1
ichiprdy
0
ipor
Chip ready goes high once we enable the xtal, RX, and a settling time for the Xtal clock
elapses. The status stay high unless we go back to Idle mode.
Power on status.
Register 05h. Interrupt Enable 1
Bit
D7
Name
enfferr
Type
R/W
D6
D5
D4
D3
D2
D1
Reserved
enrxffafull
enext
Reserved
R/W
R/W
R/W
R/W
D0
Reset value = 00000000
Bit
Name
Function
7
enfferr
6:5
Reserved
Reserved.
4
enrxffafull
Enable RX FIFO Almost Full.
When set to 1 the RX FIFO Almost Full interrupt will be enabled.
3
enext
2
Reserved
Enable FIFO Underflow/Overflow.
When set to 1 the FIFO Underflow/Overflow interrupt will be enabled.
Enable External Interrupt.
When set to 1 the External Interrupt will be enabled.
Reserved.
Rev 0.1
7
AN589
Register 06h. Interrupt Enable 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
enswdet
enpreaval
enpreainval
enrssi
enwut
enlbd
enchiprdy
enpor
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 00000011
8
Bit
Name
Function
7
enswdet
6
enpreaval
5
enpreainval
4
enrssi
Enable RSSI.
When set to 1 the RSSI Interrupt will be enabled.
3
enwut
Enable Wake-Up Timer.
When set to 1 the Wake-Up Timer interrupt will be enabled.
2
enlbd
Enable Low Battery Detect.
When set to 1 the Low Battery Detect interrupt will be enabled.
1
enchiprdy
0
enpor
Enable Sync Word Detected.
When set to 1 the Syn Word Detected Interrupt will be enabled.
Enable Valid Preamble Detected.
When set to 1 the Valid Preamble Detected Interrupt will be enabled.
Enable Invalid Preamble Detected.
When set to 1 the Invalid Preamble Detected Interrupt will be enabled.
Enable Chip Ready (XTAL).
When set to 1 the Chip Ready interrupt will be enabled.
Enable POR.
When set to 1 the POR interrupt will be enabled.
Rev 0.1
AN589
Register 07h. Operating Mode and Function Control 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
swres
enlbd
enwt
x32ksel
Reserved
rxon
pllon
xton
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 00000001
Bit
Name
Function
7
swres
Software Register Reset Bit.
This bit may be used to reset all registers simultaneously to a DEFAULT state, without the
need for sequentially writing to each individual register. The RESET is accomplished by
setting swres = 1. This bit will be automatically cleared.
6
enlbd
Enable Low Battery Detect.
When this bit is set to 1 the Low Battery Detector circuit and threshold comparison will be
enabled.
5
enwt
Enable Wake-Up-Timer.
Enabled when enwt = 1. If the Wake-up-Timer function is enabled it will operate in any
mode and notify the microcontroller through the GPIO interrupt when the timer expires.
4
x32ksel
3
Reserved
2
rxon
RX on in Manual Receiver Mode.
Automatically cleared if Multiple Packets config. is disabled and a valid packet received.
1
pllon
TUNE Mode (PLL is ON).
When pllon = 1 the PLL will remain enabled in Idle State. This allows for faster turnaround time at the cost of increased current consumption in Idle State.
0
xton
READY Mode (Xtal is ON).
32,768 kHz Crystal Oscillator Select.
0: RC oscillator
1: 32 kHz crystal
Reserved.
Rev 0.1
9
AN589
Register 08h. Operating Mode and Function Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved
ffclrrx
Reserved
Type
R/W
R/W
R/W
Reset value = 00000000
10
Bit
Name
7:2
Reserved
1
ffclrrx
0
Reserved
Function
Reserved.
RX FIFO Reset/Clear.
This has to be a two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0 will clear the
contents of the RX FIFO.
Reserved.
Rev 0.1
AN589
Register 09h. 30 MHz Crystal Oscillator Load Capacitance
Bit
D7
D6
D5
D4
D3
Name
xtalshft
xlc[6:0]
Type
R/W
R/W
D2
D1
D0
Reset value = 01111111
Bit
Name
Function
7
xtalshft
Additional capacitance to coarse shift the frequency if xlc[6:0] is not sufficient. Not binary
with xlc[6:0].
6:0
xlc[6:0]
Tuning Capacitance for the 30 MHz XTAL.
Rev 0.1
11
AN589
Register 0Ah. Microcontroller Output Clock
Bit
D7
D6
D5
D4
D3
D2
D1
Name
Reserved
clkt[1:0]
enlfc
mclk[2:0]
Type
R
R/W
R/W
R/W
D0
Reset value = xx000110
12
Bit
Name
Function
7:6
Reserved
5:4
clkt[1:0]
Clock Tail.
If enlfc = 0 then it can be useful to provide a few extra cycles for the microcontroller to
complete its operation. Setting the clkt[1:0] register will provide the addition cycles of the
clock before it shuts off.
00:
0 cycle
01:
128 cycles
10:
256 cycles
11:
512 cycles
3
enlfc
Enable Low Frequency Clock.
When enlfc = 1 and the chip is in Sleep mode then the 32.768 kHz clock will be provided
to the microcontroller no matter what the selection of mclk[2:0] is. For example if
mclk[2:0] = 000, 30 MHz will be available through the GPIO to output to the microcontroller in all Idle or RX states. When the chip is commanded to Sleep mode the 30 MHz
clock will become 32.768 kHz.
2:0
mclk[2:0]
Microcontroller Clock.
Different clock frequencies may be selected for configurable GPIO clock output. All clock
frequencies are created by dividing the XTAL except for the 32 kHz clock which comes
directly from the 32 kHz RC Oscillator. The mclk[2:0] setting is only valid when xton = 1
except the 111.
000:
30 MHz
001:
15 MHz
010:
10 MHz
011:
4 MHz
100:
3 MHz
101:
2 MHz
110:
1 MHz
111:
32.768 kHz
Reserved.
Rev 0.1
AN589
Register 0Bh. GPIO Configuration 0
Bit
D7
D6
D5
D4
D3
D2
Name
gpiodrv0[1:0]
pup0
gpio0[4:0]
Type
R/W
R/W
R/W
D1
D0
Reset value = 00000000
Bit
7:6
Name
Function
gpiodrv0[1:0] GPIO Driving Capability Setting.
5
pup0
4:0
gpio0[4:0]
Pullup Resistor Enable on GPIO0.
When set to 1 a 200 kresistor is connected internally between VDD and the pin if the
GPIO is configured as a digital input.
GPIO0 Pin Function Select.
00000:
Power-On-Reset (output)
00001:
Wake-Up Timer: 1 when WUT has expired (output)
00010:
Low Battery Detect: 1 when battery is below threshold setting (output)
00011:
Direct Digital Input
00100:
External Interrupt, falling edge (input)
00101:
External Interrupt, rising edge (input)
00110:
External Interrupt, state change (input)
00111:
Reserved
01000:
Reserved
01001:
Reserved
01010:
Direct Digital Output
01011:
Reserved
01100:
Reserved
01101:
Reserved
01110:
Reference Voltage (output)
01111:
RX Data CLK output to be used in conjunction with RX Data pin (output)
10000:
Reserved
10001:
Reserved
10010:
Reserved
10011:
Reserved
10100:
RX Data (output)
10101:
RX State (output)
10110:
RX FIFO Almost Full (output)
10111:
Reserved
11000:
Reserved
11001:
Valid Preamble Detected (output)
11010:
Invalid Preamble Detected (output)
11011:
Sync Word Detected (output)
11100:
Clear Channel Assessment (output)
11101:
VDD
else :
GND
Rev 0.1
13
AN589
Register 0Ch. GPIO Configuration 1
Bit
D7
D6
D5
D4
D3
D2
Name
gpiodrv1[1:0]
pup1
gpio1[4:0]
Type
R/W
R/W
R/W
D1
D0
Reset value = 00000000
Bit
7:6
Name
gpiodrv1[1:0] GPIO Driving Capability Setting.
5
pup1
4:0
gpio1[4:0]
14
Function
Pullup Resistor Enable on GPIO1.
When set to 1 a 200 kresistor is connected internally between VDD and the pin if the
GPIO is configured as a digital input.
GPIO1 Pin Function Select.
00000:
Inverted Power-On-Reset (output)
00001:
Wake-Up Timer: 1 when WUT has expired (output)
00010:
Low Battery Detect: 1 when battery is below threshold setting (output)
00011:
Direct Digital Input
00100:
External Interrupt, falling edge (input)
00101:
External Interrupt, rising edge (input)
00110:
External Interrupt, state change (input)
00111:
Reserved
01000:
Reserved
01001:
Reserved
01010:
Direct Digital Output
01011:
Reserved
01100:
Reserved
01101:
Reserved
01110:
Reference Voltage (output)
01111:
RX Data CLK output to be used in conjunction with RX Data pin (output)
10000:
Reserved
10001:
Reserved
10010:
Reserved
10011:
Reserved
10100:
RX Data (output)
10101:
RX State (output)
10110:
RX FIFO Almost Full (output)
10111:
Reserved
11000:
Reserved
11001:
Valid Preamble Detected (output)
11010:
Invalid Preamble Detected (output)
11011:
Sync Word Detected (output)
11100:
Clear Channel Assessment (output)
11101:
VDD
else :
GND
Rev 0.1
AN589
Register 0Dh. GPIO Configuration 2
Bit
D7
D6
D5
D4
D3
D2
Name
gpiodrv2[1:0]
pup2
gpio2[4:0]
Type
R/W
R/W
R/W
D1
D0
Reset value = 00000000
Bit
7:6
Name
Function
gpiodrv2[1:0] GPIO Driving Capability Setting.
5
pup2
4:0
gpio2[4:0]
Pullup Resistor Enable on GPIO2.
When set to 1 a 200 kresistor is connected internally between VDD and the pin if the
GPIO is configured as a digital input.
GPIO2 Pin Function Select.
00000:
Microcontroller Clock
00001:
Wake-Up Timer: 1 when WUT has expired (output)
00010:
Low Battery Detect: 1 when battery is below threshold setting (output)
00011:
Direct Digital Input
00100:
External Interrupt, falling edge (input)
00101:
External Interrupt, rising edge (input)
00110:
External Interrupt, state change (input)
00111:
Reserved
01000:
Reserved
01001:
Reserved
01010:
Direct Digital Output
01011:
Reserved
01100:
Reserved
01101:
Reserved
01110:
Reference Voltage (output)
01111:
RX Data CLK output to be used in conjunction with RX Data pin (output)
10000:
Reserved
10001:
Reserved
10010:
Reserved
10011:
Reserved
10100:
RX Data (output)
10101:
RX State (output)
10110:
RX FIFO Almost Full (output)
10111:
Reserved
11000:
Reserved
11001:
Valid Preamble Detected (output)
11010:
Invalid Preamble Detected (output)
11011:
Sync Word Detected (output)
11100:
Clear Channel Assessment (output)
11101:
VDD
else :
GND
Rev 0.1
15
AN589
Register 0Eh. I/O Port Configuration
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved
extitst[2]
extitst[1]
extitst[0]
itsdo
dio2
dio1
dio0
Type
R
R
R
R
R/W
R/W
R/W
R/W
Reset value = 00000000
Bit
Name
7
Reserved
Reserved.
6
extitst[2]
External Interrupt Status.
If the GPIO2 is programmed to be an external interrupt source then the status can be read
here.
5
extitst[1]
External Interrupt Status.
If the GPIO1 is programmed to be an external interrupt source then the status can be read
here.
4
extitst[0]
External Interrupt Status.
If the GPIO0 is programmed to be an external interrupt source then the status can be read
here.
3
itsdo
Interrupt Request Output on the SDO Pin.
nIRQ output is present on the SDO pin if this bit is set and the nSEL input is inactive (high).
2
dio2
Direct I/O for GPIO2.
If the GPIO2 is configured to be a direct output then the value on the GPIO pin can be set
here. If the GPIO2 is configured to be a direct input then the value of the pin can be read
here.
1
dio1
Direct I/O for GPIO1.
If the GPIO1 is configured to be a direct output then the value on the GPIO pin can be set
here. If the GPIO1 is configured to be a direct input then the value of the pin can be read
here.
0
dio0
Direct I/O for GPIO0.
If the GPIO0 is configured to be a direct output then the value on the GPIO pin can be set
here. If the GPIO0 is configured to be a direct input then the value of the pin can be read
here.
16
Function
Rev 0.1
AN589
Register 0Fh. ADC Configuration
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
adcstart/
adcdone
adcsel[2:0]
adcref[1:0]
adcgain[1:0]
Type
R/W
R/W
R/W
R/W
Reset value = 00000000
Bit
Name
Function
7
adcstart/
adcdone
ADC Measurement Start Bit.
Set this bit=1 starts the ADC measurement process. This bit self-clears during the measurement cycle and returns high when the measurement is complete. The conversion
process is fast; reading this bit may always appear to return a 1.
6:4
adcsel[2:0]
ADC Input Source Selection.
The internal 8-bit ADC input source can be selected as follows:
000:
Internal Temperature Sensor
001:
GPIO0, single-ended
010:
GPIO1, single-ended
011:
GPIO2, single-ended
100:
GPIO0(+) – GPIO1(–), differential
101:
GPIO1(+) – GPIO2(–), differential
110:
GPIO0(+) – GPIO2(–), differential
111:
GND
3:2
adcref[1:0]
ADC Reference Voltage Selection.
The reference voltage of the internal 8-bit ADC can be selected as follows:
0X:
bandgap voltage (1.2 V)
10:
VDD/3
11:
VDD/2
1:0
adcgain[1:0]
ADC Sensor Amplifier Gain Selection.
The full scale range of the internal 8-bit ADC in differential mode (see adcsel) can be set
as follows:
adcref[0]=0
FS=0.014 x (adcgain[1:0] + 1) x VDD
adcref[0]=1
FS=0.021 x (adcgain[1:0] + 1) x VDD
Rev 0.1
17
AN589
Register 10h. ADC Sensor Amplifier Offset
Bit
D7
D6
D5
D4
D3
D2
D1
Name
Reserved
adcoffs[3:0]
Type
R
R/W
D0
Reset value = xxxx0000
Bit
Name
7:4
Reserved
3:0
adcoffs[3:0]
Function
Reserved.
ADC Sensor Amplifier Offset*.
*Note: The offset can be calculated as Offset = adcoffs[2:0] x VDD/1000; MSB = adcoffs[3] = Sign bit.
Register 11h. ADC Value
Bit
D7
D6
D5
D4
D3
Name
adc[7:0]
Type
R
Reset value = xxxxxxxx
18
Bit
Name
7:0
adc[7:0]
Function
Internal 8 bit ADC Output Value.
Rev 0.1
D2
D1
D0
AN589
Register 12h. Temperature Sensor Calibration
Bit
D7
D6
D5
D4
D3
D2
D1
Name
tsrange[1:0]
entsoffs
entstrim
tstrim[3:0]
Type
R/W
R/W
R/W
R/W
D0
Reset value = 00100000
Bit
Name
Function
7:6
tsrange[1:0]
Temperature Sensor Range Selection.
(FS range is 0..1024 mV)
00: –64 C .. 64 C (full operating range), with 0.5 C resolution (1 LSB in the 8-bit ADC)
01: –64 C .. 192 C, with 1 C resolution (1 LSB in the 8-bit ADC)
11: 0 C .. 128 C, with 0.5 C resolution (1 LSB in the 8-bit ADC)
10: –40 F .. 216 F, with 1 F resolution (1 LSB in the 8-bit ADC)
5
entsoffs
Temperature Sensor Offset to Convert from K to ºC. Default is 1. Test mode only, to
use set tsrange and entsoffs to 0.
4
entstrim
Temperature Sensor Trim Enable.
3:0
tstrim[3:0]
Temperature Sensor Trim Value.
Register 13h. Temperature Value Offset
Bit
D7
D6
D5
D4
D3
Name
tvoffs[7:0]
Type
R/W
D2
D1
D0
Reset value = 00000000
Bit
Name
7:0
tvoffs[7:0]
Function
Temperature Value Offset.
This value is added to the measured temperature value. (MSB, tvoffs[8]: sign bit).
Rev 0.1
19
AN589
Note: If a new configuration is needed (e.g., for the WUT or the LDC), proper functionality is required. The
function must first be disabled, then the settings changed, then enabled back on.
Register 14h. Wake-Up Timer Period 1
Bit
D7
D6
D5
D4
D3
D2
Name
Reserved
wtr[4:0]
Type
R/W
R/W
D1
D0
Reset value = xxx00011
Bit
Name
7:5
Reserved
4:0
wtr[4:0]
Function
Reserved.
Wake Up Timer Exponent (R) Value*.
Maximum value for R is decimal 20. A value greater than 20 will yield a result as if 20
were written. R Value = 0 can be written here.
*Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R)/32.768 ms. R = 0 is allowed, and the
maximum value for R is decimal 20. A value greater than 20 will result in the same as if 20 was written.
Register 15h. Wake-Up Timer Period 2
Bit
D7
D6
D5
D4
D3
Name
wtm[15:8]
Type
R/W
D2
D1
D0
D1
D0
Reset value = 00000000
Bit
7:0
Name
wtm[15:8]
Function
Wake Up Timer Mantissa (M) Value*.
*Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R)/32.768 ms.
Register 16h. Wake-Up Timer Period 3
Bit
D7
D6
D5
D4
D3
Name
wtm[7:0]
Type
R/W
D2
Reset value = 00000001
Bit
Name
7:0
wtm[7:0]
Function
Wake Up Timer Mantissa (M) Value*.
M[7:0] = 0 is not valid here. Write at least decimal 1.
*Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R)/32.768 ms.
20
Rev 0.1
AN589
Register 17h. Wake-Up Timer Value 1
Bit
D7
D6
D5
D4
D3
Name
wtv[15:8]
Type
R
D2
D1
D0
Reset value = xxxxxxxx
Bit
7:0
Name
Function
wtv[15:8]
Wake Up Timer Current Mantissa (M) Value. The value in wtv[15:0] reflects the current
count value of the timer.
Register 18h. Wake-Up Timer Value 2
Bit
D7
D6
D5
D4
D3
Name
wtv[7:0]
Type
R
D2
D1
D0
Reset value = xxxxxxxx
Bit
Name
Function
7:0
wtv[7:0]
Wake Up Timer Current Mantissa (M) Value. The value in wtv[15:0] reflects the current
value of the timer.
Register 1Ah. Low Battery Detector Threshold
Bit
D7
D6
D5
D4
D3
D2
Name
Reserved
lbdt[4:0]
Type
R
R/W
D1
D0
Reset value = xxx10100
Bit
Name
7:5
Reserved
4:0
lbdt[4:0]
Function
Reserved.
Low Battery Detector Threshold.
This threshold is compared to Battery Voltage Level. If the Battery Voltage is less than the
threshold the Low Battery Interrupt is set. Default = 2 V.*
*Note: The threshold can be calculated as Vthreshold = (1.675 + lbdt x 50 mV) ±25 mV.
Rev 0.1
21
AN589
Register 1Bh. Battery Voltage Level
Bit
D7
D6
D5
D4
D3
D2
Name
Reserved
vbat[4:0]
Type
R
R
D1
D0
Reset value = xxxxxxxx
22
Bit
Name
Function
7:5
Reserved
Reserved.
4:0
vbat[4:0]
Battery Voltage Level.
The battery voltage is converted by a 5 bit ADC if the LBD bit D6 of Reg 07h is also set.
In Sleep Mode the register is updated in every 1 s. In other states it measures continuously. The measured voltage is calculated by the following formula:
Vbat_meas=1.7 V + vbat[4:0] x 50 mV
Rev 0.1
AN589
Register 1Ch. IF Filter Bandwidth
Bit
D7
Name dwn3_bypass
Type
R/W
D6
D5
D4
D3
D2
D1
ndec_exp[2:0]
filset[3:0]
R/W
R/W
D0
Reset value = 00000001
Bit
7
6:4
3:0
Name
Function
dwn3_bypass Bypass Decimator by 3 (if set).
ndec_exp[2:0] IF Filter Decimation Rates.
filset[3:0]
IF Filter Coefficient Sets.
IF Filter coefficient sets; Defaults are for Rb = 40 kbps and Fd = 20 kHz so Bw = 80 kHz.
The required bandwidth can be approximated from the following equation:
BW mod =  Rb   1 + enmanch  + 2  Fd   k
Where BWmod is the bandwidth of the modulation bandwidth in kHz, Rb is the payload bit rate in kbps, Fd is the
frequency deviation of the received GFSK/FSK signal in kHz, enmanch is Manchester Coding parameter (see
Register 70h, enmach is 1 when Manchester coding is enabled, enmanch is 0 when disabled) and k is a correction
factor depending if GFSK or FSK is received.

k = 1 for FSK
 k = 0.9 for GFSK with default Gaussian filter settings (BT = 0.5)
The bandwidth of the channel select filter in the receiver might need some extra bandwidth to cope with tolerances
in transmit and receive frequencies which depends on the tolerances of the applied crystals. When the relative
frequency error (Ferror) between transmitter and receiver is less than half the modulation bandwidth (BWmod) then
the AFC will correct the frequency error without needing extra bandwidth. When the frequency error exceeds
BWmod/2 then some extra bandwidth will be needed to assure proper AFC operation under worst case conditions.
As a guide line the bandwidth in the channel select filter should be set to the following:
BW mod
F error  --------------------  BW ch – sel = BW mod
2
BW mod
F error  --------------------  BW ch – sel = 2  F error
2
Rev 0.1
23
AN589
For a required IF filter bandwidth, the three filter parameters (ndec_exp, dwn3_bypass, and filset) may be found
from the table below. If the desired filter bandwidth is not exactly available, the next higher available bandwidth
should be selected.
BW [kHz] ndec_exp dwn3_bypass
2.6
5
0
2.8
5
0
3.1
5
0
3.2
5
0
3.7
5
0
4.2
5
0
4.5
5
0
4.9
4
0
5.4
4
0
5.9
4
0
6.1
4
0
7.2
4
0
8.2
4
0
8.8
4
0
9.5
3
0
10.6
3
0
11.5
3
0
12.1
3
0
14.2
3
0
16.2
3
0
17.5
3
0
18.9
2
0
21.0
2
0
22.7
2
0
24.0
2
0
28.2
2
0
32.2
2
0
34.7
2
0
37.7
1
0
24
filset
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1
BW [kHz] ndec_exp dwn3_bypass
41.7
1
0
45.2
1
0
47.9
1
0
56.2
1
0
64.1
1
0
69.2
1
0
75.2
0
0
83.2
0
0
90.0
0
0
95.3
0
0
112.1
0
0
127.9
0
0
137.9
0
0
142.8
1
1
167.8
1
1
181.1
1
1
191.5
0
1
225.1
0
1
248.8
0
1
269.3
0
1
284.9
0
1
335.5
0
1
361.8
0
1
420.2
0
1
468.4
0
1
518.8
0
1
577.0
0
1
620.7
0
1
Rev 0.1
filset
2
3
4
5
6
7
1
2
3
4
5
6
7
4
5
9
15
1
2
3
4
8
9
10
11
12
13
14
AN589
Register 1Dh. AFC Loop Gearshift Override
Bit
D7
D6
D5
D4
D3
Name
afcbd
enafc
afcgearh[2:0]
Type
R/W
R/W
R/W
D2
D1
D0
1p5bypass
matap
ph0size
R/W
R/W
Reset value = 01000100
Bit
Name
Function
7
afcbd
AFC wideband enable (active high). If set, the IF filter bandwidth is reduced after preamble detection, in order to optimize RX sensitivity. The alternate IF filter coefficients
must be specified in SPI Reg 60h and 61h; contact Silicon Labs Application Support for
details.
6
enafc
AFC Enable.
5:3
afcgearh[2:0] AFC High Gear Setting. Feedback loop gain during AFC setting process is proportional
to 2^(–afcgearh[2:0]).
2
1p5bypass
If high (1), select 0dB bias for the second phase antenna selection, if low (0), select
1.5 dB. The default is (1), selecting 0 dB.
1
matap
Number of taps for moving average filter during Antenna Diversity RSSI evaluation. Allows for reduced noise variation on measured RSSI value but with slower update
rate. If high (1), filter tap length = 8*Tb. If low (0=default), filter tap length = 8*Tb prior to
first PREAMBLE_VALID, and 4*Tb thereafter.
0
ph0size
If low, we will reset the Preamble detector if there are 5 consecutive zero phases. If
high, the reset will happen after 3 consecutive zero phases.
Register 1Eh. AFC Timing Control
Bit
D7
D6
D5
D4
D3
D2
D1
Name
swant_timer[1:0]
shwait[2:0]
anwait[2:0]
Type
R/W
R/W
R/W
D0
Reset value = xx001010
Bit
7:6
Name
Function
swant_timer[1:0 swant_timer=additional number of bit periods to wait for RSSI value to stabilize during
]
Antenna Diversity 2nd phase antenna evaluation. If matap=0, total wait
time=8 x Tb+swant_timer[1:0]. If matap=1, total wait time=12 x Tb+swant_timer{1:0].
Effective only during Antenna Diversity.
5:3
shwait[2:0]
shwait[2:0]=short wait periods after AFC correction used before preamble is detected.
Short wait=(RegValue+1) x 2Tb. If set to ‘0’ then no AFC correction will occur before
preamble detect, i.e., AFC will be disabled.
2:0
anwait[2:0]
anwait[2:0]=antenna switching wait time. Number of bit periods between toggling
selection of antennas=(anwait[2:0] + 2) x 4. Default value = 3’b010=16 bit periods.
Rev 0.1
25
AN589
Register 1Fh. Clock Recovery Gearshift Override
Bit
D7
D6
D5
D4
D3
D2
D1
Name
Reserved
crfast[2:0]
crslow[2:0]
Type
R/W
R/W
R/W
D0
Reset value = 00000011
Bit
Name
Function
7:6
Reserved
Reserved.
5:3
crfast[2:0]
Clock Recovery Fast Gearshift Value.
2:0
crslow[2:0]
Clock Recovery Slow Gearshift Value.
The gear-shift register controls BCR loop gain. Before the preamble is detected, BCR loop gain is as follows:
BCRLoopGain 
crgain
2 crfast
Once the preamble is detected, internal state machine automatically shift BCR loop gain to the following:
BCRLoopGain 
crgain
2 crslow
crfast = 3’b000 and crslow = 3’b101 are recommended for most applications. The value of “crslow” should be
greater than “crfast”.
26
Rev 0.1
AN589
Register 20h. Clock Recovery Oversampling Rate
Bit
D7
D6
D5
D4
D3
Name
rxosr[7:0]
Type
R/W
D2
D1
D0
Reset value = 01100100
Bit
Name
7:0
rxosr[7:0]
Function
Oversampling Rate.
3 LSBs are the fraction, default = 0110 0100 = 12.5 clock cycles per data bit
The oversampling rate can be calculated as rxosr = 500 kHz/(2ndec_exp x RX_DR). The ndec_exp and the
dwn3_bypass values found at Address: 1Ch–IF Filter Bandwidth register together with the receive data rate (Rb)
are the parameters needed to calculate rxosr:
rxosr 
500  1  2  dwn3 _ bypass 
2 ndec _ exp 3  Rb  (1  enmanch)
The Rb unit used in this equation is in kbps. The enmanch is the Manchester Coding parameter (see Reg. 70h,
enmach is 1 when Manchester coding is enabled, enmanch is 0 when disabled). The number found in the equation
should be rounded to an integer. The integer can be translated to a hexadecimal.
For optimal modem performance it is recommended to set the rxosr to at least 8. A higher rxosr can be obtained by
choosing a lower value for ndec_exp or enable dwn3_bypass. A correction in filset might be needed to correct the
channel select bandwidth to the desired value. Note that when ndec_exp or dwn3_bypass are changed the related
parameters (rxosr, ncoff and crgain) need to be updated.
Rev 0.1
27
AN589
Register 21h. Clock Recovery Offset 2
Bit
D7
D6
D5
D4
D3
D2
D1
Name
rxosr[10:8]
skip2phth
ncoff[19:16]
Type
R/W
R/W
R/W
D0
Reset value = 00000001
Bit
Name
7:5
rxosr[10:8]
Oversampling Rate.
Upper bits.
Function
4
skip2phth
Skip 2nd Phase Ant Div Threshold. Threshold for skipping the 2nd phase of RSSI
detection during antenna diversity algorithm. 0=16 dB (default), 1=11 dB.
NOT RECOMMENDED FOR USER CONFIGURATION.
3:0
ncoff[19:16]
NCO Offset.
See formula above.
The offset can be calculated as follows:
ncoff 
Rb  (1  enmanch)  2 20 ndec _ exp
500  1  2  dwn3 _ bypass 
The default values for register 20h to 23h gives 40 kbps RX_DR with Manchester coding is disabled.
Register 22h. Clock Recovery Offset 1
Bit
D7
D6
D5
D4
D3
Name
ncoff[15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
Reset value = 01000111
Bit
Name
7:0
ncoff[15:8]
Function
NCO Offset.
See formula above.
Register 23h. Clock Recovery Offset 0
Bit
D7
D6
D5
D4
D3
Name
ncoff[7:0]
Type
R/W
Reset value = 10101110
28
Bit
Name
7:0
ncoff[7:0]
Function
NCO Offset.
See formula above
Rev 0.1
AN589
Register 24h. Clock Recovery Timing Loop Gain 1
Bit
D7
D6
D5
D4
D3
D2
D1
Name
Reserved
rxncocomp
cgainx2
crgain[10:8]
Type
R/W
R/W
R/W
R/W
D0
Reset value = 00000010
Bit
Name
7:5
Reserved
4
rxncocomp
3
cgainx2
2:0
crgain[10:8]
Function
Reserved.
Receive Compensation Enable for High Data Rate Offset.
Multiplying the CR Gain by 2.
Clock Recovery Timing Loop Gain.
The loop gain can be calculated as follows:
15
2   1 + enmanch   Rb
crgain = 2 + ----------------------------------------------------------------------rxosr  Fd
Register 25h. Clock Recovery Timing Loop Gain 0
Bit
D7
D6
D5
D4
D3
Name
crgain[7:0]
Type
R/W
D2
D1
D0
Reset value = 10001111
Bit
Name
7:0
crgain[7:0]
Function
Clock Recovery Timing Loop Gain.
Rev 0.1
29
AN589
Register 26h. Received Signal Strength Indicator
Bit
D7
D6
D5
D4
D3
Name
rssi[7:0]
Type
R
D2
D1
D0
D2
D1
D0
D1
D0
Reset value = xxxxxxxx
Bit
Name
7:0
rssi[7:0]
Function
Received Signal Strength Indicator Value.
Register 27h. RSSI Threshold for Clear Channel Indicator
Bit
D7
D6
D5
D4
D3
Name
rssith[7:0]
Type
R/W
Reset value = 00011110
Bit
Name
7:0
rssith[7:0]
Function
RSSI Threshold.
Interrupt is set if the RSSI value is above this threshold.
Register 28h. Antenna Diversity 1
Bit
D7
D6
D5
D4
D3
Name
adrssi[7:0]
Type
R
Reset value = xxxxxxxx
30
Bit
Name
7:0
adrssi[7:0]
Function
Measured RSSI Value on Antenna 1.
Rev 0.1
D2
AN589
Register 29h. Antenna Diversity 2
Bit
D7
D6
D5
D4
D3
Name
adrssi2[7:0]
Type
R
D2
D1
D0
D2
D1
D0
Reset value = xxxxxxxx
Bit
Name
7:0
adrssi2[7:0]
Function
Measured RSSI Value on Antenna 2.
Register 2Ah. AFC Limiter
Bit
D7
D6
D5
D4
D3
Name
Afclim[7:0]
Type
R/W
Reset value = 00000000
Bit
Name
7:0
Afclim[7:0]
Function
AFC Limiter.
AFC limiter value.
For the following registers (addresses 2Bh and 2Ch), use the following equation:
3  500 kHz
ook_cnt_val = -----------------------------------------------------R b   enmanch + 1 
where Rb's unit is in kHz and "enmanch" is the Manchester Enable bit (found at address 71h bit [1]).
Therefore, the minimal data rate that this register can support without Manchester is 0.366 kbps.
Register 2Bh. AFC Correction (MSBs)
Bit
D7
D6
D5
D4
D3
Name
afc_corr[9:2]
Type
R
D2
D1
D0
Reset value = xxxxxxxx
Bit
Name
Function
7:0
afc_corr[9:2]
AFC Correction Values.
AFC loop correction values [9:2] (MSBs only). Values are updated once, after sync word
is found during receiving. See also address 2Ch.
Rev 0.1
31
AN589
Register 2Ch. OOK Counter Value 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
afc_corr[1:0]
ookfrzen
peakdeten
madeten
ookcnt[10]
ookcnt[9]
ookcnt[8]
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 00011000
Bit
Name
Function
7:6
afc_corr[1:0]
5
ookfrzen
OOK Freeze.
ookfrzen= when 0 (default), AGC and OOK Moving Average Detector threshold operate
continuously. When 1, AGC and OOK MA Detector threshold operate until
PREAMBLE_VALID signal is detected; values are frozen thereafter. Recommended for
use with non-Manchestered payload data.
4
peakdeten
Peak Detector Enable.
peakdeten= when 1 (default), Peak Detector for OOK Modem is enabled. Provides
improved performance in presence of co-channel interferers, at slight reduction of sensitivity. Peak Detector output is logically AND’ed with Moving Average Detector output.
3
madeten
MA_Enable.
madeten= when 1 (default), Moving Average Detector for OOK Modem is enabled. Provides best sensitivity, but requires DC-balanced data (e.g., Manchester data) and is more
sensitive to co-channel interference. Peak Detector output is logically AND’ed with Moving Average Detector output.
2:0
ookcnt[10:8]
AFC Correction Values.
AFC loop correction values [1:0] (LSBs). Values are updated once, after sync word is
found during receiving. See also address 2Bh.
OOK Counter [10:8].
OOK counter [10:8] =OOK counter Value MSBs. This counter value will affect the OOK
AGC’s decay time.
Register 2Dh. OOK Counter Value 2
Bit
D7
D6
D5
D4
D3
Name
ookcnt[7:0]
Type
R/W
D2
D1
D0
Reset value = 10111100
32
Bit
Name
7:0
ookcnt[7:0]
Function
OOK Counter [7:0].
OOK counter value LSBs. This counter value will affect the OOK AGC’s decay time.
Rev 0.1
AN589
Register 2Eh. Slicer Peak Holder
Bit
D7
D6
D5
D4
D3
D2
D1
Name
Reserved
attack[2:0]
decay[3:0]
Type
R/W
R/W
R/W
D0
Reset value = 00101100
Bit
Name
Function
7
Reserved
Reserved.
6:4
attack[2:0]
Attack. attack [2:0}=OOK Peak Detector attack time. Peak detector value charges up at
rate proportional to 2^(-attack[2:0]). OOK slicing threshold is set 6 dB below peak detector value. Effective only when OOK Peak Detector is enabled.
3:0
decay[3:0]
Decay. decay[3:0]=OOK Peak Detector decay time. Peak detector value discharges at
rate proportional to 2^(-decay[3:0]). OOK slicing threshold is set 6 dB below peak detector value. Effective only when OOK Peak Detector is enabled.
Rev 0.1
33
AN589
Register 30h. FIFO Configuration
Bit
D7
D6
D5
D4
D3
Name
FIFO_RX
Reserved
Type
R/W
R/W
D2
D1
D0
D1
D0
Reset value = 10000010
Bit
Name
Function
7
FIFO_RX
FIFO Receive.
Must set to 0 to allow correct operation of the FIFO. Default is 1.
6:0
Reserved
Reserved.
Register 35h. Preamble Detection Control 1
Bit
D7
D6
D5
D4
D3
D2
Name
preath[4:0]
rssi_offset[2:0]
Type
R/W
R/W
Reset value = 00101010
Bit
Name
Function
7:3
preath[4:0]
Preamble Detection Threshold. The value in the preath[4:0] register corresponds to the
number of nibbles (4 bits) of preamble pattern (i.e., 01010...) that must be received correctly, before a PREAMBLE_VALID signal is issued. This threshold helps guard against
false preamble detection upon noise.
2:0
34
rssi_offset[2:0] rssi_offset[2:0]
Value added as offset to RSSI calculation. Every increment in this register results in an
increment of +4 dB in the RSSI.
Rev 0.1
AN589
Register 36h. Synchronization Word 3
Bit
D7
D6
D5
D4
D3
Name
sync[31:24]
Type
R/W
D2
D1
D0
D2
D1
D0
D2
D1
D0
Reset value = 00101101
Bit
Name
7:0
sync[31:24]
Function
Synchronization Word 3.
4th byte of the synchronization word.
Register 37h. Synchronization Word 2
Bit
D7
D6
D5
D4
D3
Name
sync[23:16]
Type
R/W
Reset value = 11010100
Bit
Name
7:0
sync[23:16]
Function
Synchronization Word 2.
3rd byte of the synchronization word.
Register 38h. Synchronization Word 1
Bit
D7
D6
D5
D4
D3
Name
sync[15:8]
Type
R/W
Reset value = 00000000
Bit
Name
7:0
sync[15:8]
Function
Synchronization Word 1.
2nd byte of the synchronization word.
Rev 0.1
35
AN589
Register 39h. Synchronization Word 0
Bit
D7
D6
D5
D4
D3
Name
sync[7:0]
Type
R/W
D2
D1
D0
D2
D1
D0
D2
D1
D0
Reset value = 00000000
Bit
Name
Function
7:0
sync[7:0]
Synchronization Word 0.
1st byte of the synchronization word.
Register 4Fh. ADC8 Control
Bit
D7
D6
D5
D4
D3
Name
Reserved
adc8[5:0]
Type
R/W
R/W
Reset value = 00010000
Bit
Name
Function
7:6
Reserved
Reserved.
5:0
adc8[5:0]
ADC8 Control Bits.
Register 60h. Channel Filter Coefficient Address
Bit
D7
D6
D5
D4
D3
Name
invalid_preamble_threshold[3:0]
Reserved
Type
R/W
R/W
Reset value = 00000000
Bit
7:4
3:0
36
Name
Function
invalid_preamble_ Invalid Preamble Threshold.
threshold[3:0]
invalid_preamble_threshold[3:0}=This configures (in nibbles) for how long we will
search for preamble. If during this time the preamble is not detected, we will send a
signal (which can be configured as interrupt) and restart looking for the preamble
again. The interval between each interrupt is given by the formula below.
Reserved
Reserved.
Rev 0.1
AN589
Register 62h. Crystal Oscillator/Power-on-Reset Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
pwst[2:0]
clkhyst
enbias2x
enamp2x
bufovr
enbuf
Type
R
R/W
R/W
R/W
R/W
R/W
Reset value = xxx00100
Bit
Name
Function
7:5
pwst[2:0]
4
clkhyst
3
enbias2x
2 Times Higher Bias Current Enable.
2
enamp2x
2 Times Higher Amplification Enable.
1
bufovr
Output Buffer Enable Override.
If set to 1 then the enbuf bit controls the output buffer.
0: output buffer is controlled by the state machine.
1: output buffer is controlled by the enbuf bit.
0
enbuf
Output Buffer Enable.
This bit is active only if the bufovr bit is set to 1.
Internal Power States of the Chip.
LP:
000
RDY: 001
Tune: 011
RX:
111
Clock Hysteresis Setting.
Rev 0.1
37
AN589
Register 69h. AGC Override 1
Bit
D7
D6
D5
D4
D3
D2
D1
Name
Reserved
sgin
agcen
lnagain
pga[3:0]
Type
R
R/W
R/W
R/W
R/W
D0
Reset value = 00100000
38
Bit
Name
Function
7
Reserved
6
sgin
sgin=AGC stop increasing gain override bit (active low). When ‘0’ (default), AGC gain
increases during signal reductions are prevented. When ‘1’, AGC gain increases during
signal reductions are allowed. Only effective during Preamble, prior to detection of
PREAMBLE_VALID signal.
5
agcen
Automatic Gain Control Enable.
agcen=Automatic Gain Control enable. When this bit is set then the result of the control
can be read out from bits [4:0], otherwise the gain can be controlled manually by writing
into bits [4:0].
4
lnagain
LNA Gain Select.
Inagain=LNA Gain select.
0 – min. gain = 5 dB
1 – max. gain = 25 dB
3:0
pga[3:0]
PGA Gain Override Value.
0000: 0 dB
0001: 3 dB
0010: 6 dB
...
1000: 24 dB max.
Reserved.
Rev 0.1
AN589
Register 70h. Modulation Mode Control 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved
Reserved
manppol
enmaninv
enmanch
enwhite
Type
R
R/W
R/W
R/W
R/W
R/W
Reset value = 00001100
Bit
Name
Function
7:4
Reserved
Reserved.
3
manppol
Manchester Preamble Polarity (will transmit a series of 1 if set, or series of 0 if
reset).
This bit affects only the transmitter side, not the receiver. This is valid only if Manchester
Mode is enabled.
2
enmaninv
Manchester Data Inversion is Enabled if this bit is set.
When this bit is low, a 10 pair is considered a Manchester 0, and a 01 pair as a Manchester 1. By setting this bit, do the opposite: every 10 will be considered as a 1, and every 01
will be considered as a 0. This function is relevant only if the Manchester mode is
enabled.
1
enmanch
Manchester Coding is Enabled if this bit is set.
What Manchester coding does is to replace a single high bit (1) with two bits starting with
low followed by high (01) and a low bit (0) with a high bit followed by a low bit (10). When
Manchester is enabled, please configure as well the enmaninv at 70h bit [2] since it influences the Manchester encoding/decoding process.
0
enwhite
Data Whitening is Enabled if this bit is set.
Rev 0.1
39
AN589
Register 71h. Modulation Mode Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
rxclk[1:0]
dtmod[1:0]
eninv
fd[8]
modtyp[1:0]
Type
R/W
R/W
R/W
R/W
R/W
Reset value = 00000000
Bit
Name
Function
7:6
trclk[1:0]
5:4
dtmod[1:0]
3
eninv
Invert RX Data.
2
fd[8]
MSB of Frequency Deviation Setting.
1:0
modtyp[1:0]
RX Data Clock Configuration.
00: NA
01: NA
10: RX Data CLK is available via the SDO pin.
11: RX Data CLK is available via the nIRQ pin.
Modulation Source.
00: Direct Mode using Data function via the GPIO pin (one of the GPIO’s should be programmed accordingly as well)
01: Direct Mode using Data function via the SDI pin (only when nSEL is high)
10: FIFO Mode
11: PN9 (internally generated)
Modulation Type.
00: Unmodulated carrier
01: OOK
10: FSK
11: GFSK
The frequency offset can be calculated: Offset = 156.25 Hz x (hbsel + 1) x fo[7:0] . fo[9:0] is a 2s complement
value. In EZRadioPRO, reading from this register will give the AFC correction last results, not this register value.
Register 73h. Frequency Offset 1
Bit
D7
D6
D5
D4
D3
Name
fo[7:0]
Type
R/W
D2
D1
D0
Reset value = 00000000
40
Bit
Name
7:0
fo[7:0]
Function
Frequency Offset Setting.
The frequency offset can be calculated as Offset = 156.25 Hz x (hbsel + 1) x fo[7:0].
fo[9:0] is a twos complement value.
Rev 0.1
AN589
In EZRadioPRO, reading from this register will give the AFC correction last results, not this register value.
Register 74h. Frequency Offset 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved
fo[9:8]
Type
R
R/W
Reset value = 00000000
Bit
Name
7:2
Reserved
1:0
fo[9:8]
Function
Reserved.
Upper Bits of the Frequency Offset Setting.
fo[9] is the sign bit. The frequency offset can be calculated as Offset = 156.25 Hz x (hbsel
+ 1) x fo[7:0]. fo[9:0] is a twos complement value.
Register 75h. Frequency Band Select
Bit
D7
D6
D5
D4
D3
D2
Name
Reserved
sbsel
hbsel
fb[4:0]
Type
R
R/W
R/W
R/W
D1
D0
Reset value = 01110101
Bit
Name
Function
7
Reserved
6
sbsel
Side Band Select.
5
hbsel
High Band Select.
Setting hbsel = 1 will choose the frequency range from 480–960 MHz (high bands). Setting hbsel = 0 will choose the frequency range from 240–479.9 MHz (low bands).
4:0
fb[4:0]
Frequency Band Select.
Every increment corresponds to a 10 MHz Band for the Low Bands and a 20 MHz Band
for the High Bands. Setting fb[4:0] = 00000 corresponds to the 240–250 MHz Band for
hbsel = 0 and the 480–500 MHz Band for hbsel = 1. Setting fb[4:0] = 00001 corresponds
to the 250–260 MHz Band for hbsel = 0 and the 500–520 MHz Band for hbsel = 1.
Reserved.
Rev 0.1
41
AN589
The RF carrier frequency can be calculated as follows:
fcarrier = (fb+24+(fc+fo)/64000) x 10000 x (hbsel+1) + (fhch x fhs x 10) [kHz],
where parameters fc, fo, fb and hb_sel come from registers 73h–77h. Parameters fhch and fhs come from register
79h and 7Ah.
Register 76h. Nominal Carrier Frequency
Bit
D7
D6
D5
D4
D3
Name
fc[15:8]
Type
R/W
D2
D1
D0
D2
D1
D0
D2
D1
D0
Reset value = 10111011
Bit
Name
7:0
fc[15:8]
Function
Nominal Carrier Frequency Setting.
See formula above.
Register 77h. Nominal Carrier Frequency
Bit
D7
D6
D5
D4
D3
Name
fc[7:0]
Type
R/W
Reset value = 10000000
Bit
Name
7:0
fc[7:0]
Function
Nominal Carrier Frequency Setting.
See formula above.
Register 79h. Frequency Hopping Channel Select
Bit
D7
D6
D5
D4
D3
Name
fhch[7:0]
Type
R/W
Reset value = 00000000
42
Bit
Name
7:0
fhch[7:0]
Function
Frequency Hopping Channel Number.
Rev 0.1
AN589
Register 7Ah. Frequency Hopping Step Size
Bit
D7
D6
D5
D4
D3
Name
fhs[7:0]
Type
R/W
D2
D1
D0
Reset value = 00000000
Bit
Name
7:0
fhs[7:0]
Function
Frequency Hopping Step Size in 10 kHz Increments.
See formula for the nominal carrier frequency at "Register 76h. Nominal Carrier Frequency".
Register 7Eh. RX FIFO Control
Bit
D7
D6
D5
D4
D3
D2
Name
Reserved
rxafthr[5:0]
Type
R/W
R/W
D1
D0
D1
D0
Reset value = 00110111
Bit
Name
Function
7:6
Reserved
Reserved.
5:0
rxafthr[5:0]
RX FIFO Almost Full Threshold.
Register 7Fh. FIFO Access
Bit
D7
D6
D5
D4
D3
Name
fifod[7:0]
Type
R/W
D2
Reset value = NA
Bit
Name
7:0
fifod[7:0]
Function
FIFO Data.
A Read (R/W=0) to this address will begin a burst read of the RX FIFO.
Rev 0.1
43
AN589
CONTACT INFORMATION
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Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
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and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
44
Rev 0.1