RFM31 RFM31 ISM Receiver Module V 1.1 Features Frequency Range = 240–960 MHz Configurable packet structure Sensitivity = –118 dBm Preamble detector RX 64 byte FIFO Low battery detector Temperature sensor and 8-bit ADC –40 to +85 °C temperature range Integrated voltage regulators Frequency hopping capability Low Power Consumption ● 18.5 mA receive Data Rate = 1 to 128 kbps Power Supply = 1.8 to 3.6 V Ultra low power shutdown mode Digital RSSI Wake-up timer FSK, GFSK, and OOK modulation Auto-frequency calibration (AFC) Power-on-reset (POR) Clear channel assessment RFM31 Programmable RX BW 2.6–620 kHz Programmable packet handler Programmable GPIOs Applications Remote control Home security & alarm Remote meter reading Remote keyless entry Telemetry Home automation Personal data logging Industrial control Toy control Sensor networks Tire pressure monitoring Health monitors Wireless PC peripherals Tag readers The RFM31 is low cost ISM receiver module and offers advanced radio features including continuous frequency coverage from 240–960 MHz , The extremely low receive sensitivity (–118 dBm) ensures extended range and improved link performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte RX FIFO, automatic packet handling, and preamble detection reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The RFM31‘s digital receive architecture features a high-performance ADC and DSP based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. This digital architecture simplifies system design while allowing for the use of lower-end MCUs. 1 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 TABLE OF CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ……... . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ……... . . . . . . . . . .10 2.1. Operating Modes . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ……. . . . . . . . . . . .11 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …… . . . . . . . . .12 3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . .12 3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . .14 3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . ….. . . . . . . . . . . . . . . . . .17 3.4. Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ….. . . . . . . . . . . . . . . . . . . .17 3.5. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . ….. . . . . . . . . . . . . . . . . . . . .18 3.6. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . . . . . .19 4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . .25 4.1. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . … . . . . . .. . . .25 5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . .. . . . . . . . .26 5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . . .26 5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . . .26 5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . .26 5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . .26 5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . . .26 5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . . . . .27 5.7. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . .28 5.8. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . . . . . .28 6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . ……. . . . . .. . . . . . . . . . . . . . .29 6.1. RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . . . . ... . . .29 6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . .30 6.3. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . …….. . . . . . . . . . . . . . .. . .30 6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . …. . … . . . . . . . . ... . .33 6.5. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . . . . . .33 6.6. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ……. . .. . . . . . ……... . .33 6.7. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . . . . . .34 7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . .. . . .35 7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . …… . . . . . . . . . . . .. . . . .35 7.2. Modem Settings for OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …… . . . . . . . . . . . . . . .38 8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . . . . . .41 8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …… . . . . . . . . . . . . . . . . .41 8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …… . . . . . . . . . . . . . . . . .42 8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . .. . . . .. . . .43 8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ……. . . . . . . . . . . . . . . . . . .47 8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . . . . . . . . .48 2 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . .. . . . . . . . . .49 8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . …... . . . . . . . . . . . . . .. . . . . . . . .51 8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . .. . . . . . . .52 8.9. Antenna-Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . .. . .. . . . .53 8.10. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . …... . . . . . . . . . . . . … . . . . .54 9. Reference Design . . . . . . . . . . . … . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . . . . . . . . . . . .55 10. Measurement Results . . . . . . . . . . . . . … . . . . . . . . . . . . . . . ….. . . . . . . . . . . . . . . . .. . . . . .58 11. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . . . .. . . . . . . . . . . . .59 10.1. Complete Register Table and Descriptions . . . . . . . . . . …. . . . . . . . . . . . . . …. . . . . . .59 12. Pin Descriptions: RFM31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . . . . . ... . … . . . . . . . .129 13. MechanicalDimension:RFM31. . . . . . . . . .. . . . . . . . . . . . . . … . . . . . . . . . . …. . . . . . . . . .131 14.Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . .. . . . . . . . . . . . . . 133 15. Errata Status Summary......................................................................................................134 16.Errata Details.......................................................................................................................135 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . … . . . . . . . . . . . .. . . . . . . . .136 3 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 1. Electrical Specifications Table 1. DC Characteristics Parameter Supply Voltage Range Power Saving Modes Symbol Conditions Vdd IShutdown RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF2 Min Typ Max Units 1.8 3.0 3.6 V 10 TBD nA — Low Power Digital Regulator ON (Register values IStandby retained) and Main Digital Regulator, and RC Oscillator 400 — — OFF1 RC Oscillator and Low Power Digital Regulator ON ISleep nA (Register values retained) and Main Digital Regulator 800 — nA — OFF1 ISensorLBD ISensorTS IReady TUNE Mode Current ITune RX Mode Current IRX Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF2 Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF2 Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled1 Synthesizer and regulators enabled — — — — — 1 1 600 9.5 18.5 — — — — — μA μA μA mA mA Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 4 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 1 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency Range Synthesizer Frequency Resolution2 Reference Frequency Reference Frequency Input Level2 Synthesizer FSYNTH-LB FSYNTH-HB FRES-LB FRES-HB fREF Min Typ Max Units Low Band 240 — 480 MHz High Band 480 — 960 MHz Low Band — 156.25 — Hz High Band — 312.5 — Hz fcrystal /3 — 10 — MHz 0.7 — 1.6 V — 200 — μs — 2 4 kHzRMS △F = 10 kHz — –80 — dBc/Hz △F = 100 kHz — –90 — dBc/Hz △F = 1 MHz — –115 — dBc/Hz △F = 10 MHz — –130 — dBc/Hz When fREF_LV instead using of reference frequency crystal. Measured peak-to-peak (VPP) Settling Measured from leaving Ready mode tLOCK Time2 Conditions with XOSC running to any frequency includ-ing VCO Calibration Residual FM2 Phase Noise2 △FRMS Lφ (fM) Integrated over ±250 kHz bandwidth (500 Hz lower bound of integration) Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 5 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 3. Transmitter AC Electrical Characteristics1 Parameter Symbol Conditions Min Typ Max Units RX Frequency Range FSYNTH-LB FSYNTH-HB Low Band 240 — 480 MHz High Band 480 — 960 MHz RX Sensitivity PRX_2 (BER < 0.1%) — –118 -115 dBm — –107 -104 dBm — –103 -100 dBm — –101 -98 dBm –110 -107 dBm — –102 -99 dBm 2.6 — 620 kHz — 0 0.1 ppm — –20 — dBm — ±0.5 — dB — –31 — dB — –35 — dB 0.5, channel spacing = 150 kHz — –40 — dB Desired Ref Signal 3 dB above sensitivity. — –52 — dB Interferer and desired modulated with — –56 — dB 40 kbps△F = 20 kHz GFSK with BT = 0.5 — –63 — dB IF=937 kHz — –30 — dB Measured at RX pins — — –54 (2 kbps, GFSK, BT = 0.5, △f =±5 kHz) 2 PRX_40 (BER < 0.1%) (40 kbps, GFSK, BT = 0.5, △f =±20 kHz) 2 PRX_100 (BER < 0.1%) (100 kbps, GFSK, BT = 0.5, △f =±50 kHz) 2 PRX_125 (BER < 0.1%) (125 kbps, GFSK, BT = 0.5, △f =±62.5 kHz) 1 PRX_OOK (BER < 0.1%) (4.8 kbps, 350 kHz BW, OOK) 2 (BER < 0.1%) (40 kbps, 400 kHz BW, OOK) RX Bandwidth2 Residual BER BW PRX_RES Performance2 Input Intercept Point, 3rd IIP3RX Order2 RSSI Resolution ±1-Ch Offset C/I1-CH Selectivity2 C/I2-CH (BER < 0.1%) ≥±3-Ch Offset Selectivity2 Blocking at 4 MHz2 Blocking at 8 MHz2 Image Rejection2 Spurious C/I3-CH (BER <0.1%) Blocking at 1 MHz2 Emissions2 Up to +5 dBm Input Level f1 = 915 MHz, f2 = 915 MHz, P1 = P2 = –40 dBm RESRSSI Selectivity2 (BER < 0.1%) ±2-Ch Offset 1 1MBLOCK 4MBLOCK 8MBLOCK ImREJ POB_RX1 Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps△F = 20 kHz GFSK with BT = dBm (LO feed through) Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 6 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 4. Auxiliary Block Specifications1 Parameter Symbol Min Typ Max Units — 0.5 — °C TSS — 5 — mV/°C LBDRES — 50 — mV LBDCT — 250 — μs 32.768K — 30M Hz ADCENB — 8 — bit ADCRES — 4 — mV ADCCT — 305 — μsec t30M — 1 — ms 30MRES — 97 — fF — 6 — sec — 100 — ppm — 2500 — ppm — 16 — ms — 100 — μs Temperature Sensor TSA Accuracy2 Temperature Sensor Sensitivity2 Low Battery Detector Resolution2 Low Battery Detector Conversion Time2 Microcontroller Clock Conditions When calibrated using temp sensor offset register Configurable to 30 MHz, Output Frequency MC 15 MHz, 10 MHz, 4 MHz, 3 MHz, 2 MHz, 1 MHz, or 32.768 kHz General Purpose ADC Accuracy2 General Purpose ADC Resolution2 Temp Sensor & General Purpose ADC Conversion Time2 30 MHz XTAL Start-Up time 30 MHz XTAL Cap Resolution2 32 kHz XTAL t32K Start-Up Time2 32 kHz XTAL Accuracy2 32 kHz RC OSC Accuracy2 POR Reset Time Software Reset Time2 32KRES 32KRCRES tPOR tsoft Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 7 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Parameter Symb Conditions Min Typ Max Units ol Rise Time TRISE 0.1 x VDD to 0.9 x VDD, CL= 5 pF — — 8 ns Fall Time TFALL 0.9 x VDD to 0.1 x VDD, CL= 5 pF — — 8 ns Input Capacitance CIN — — 1 pF VDD – 0.6 — — V — 0.6 V –100 VDD – 0.6 — — 100 — nA V — — 0.6 V Min Typ Max Units — — 8 ns — — 8 ns 1 pF Logic High Level Input Voltage VIH Logic Low Level Input Voltage VIL Input Current Logic High Level Output Voltage IIN VOH 0<VIN< VDD IOH<1 mA source, VDD=1.8 V Logic Low Level Output Voltage VOL IOL<1 mA sink, VDD=1.8 V Note: All specification guaranteed by production test unless otherwise noted. Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) Parameter Rise Time Symbol TRISE Fall Time TFALL Conditions 0.1 x VDD to 0.9 x VDD, CL= 10 pF, DRV<1:0>=HH 0.9 x VDD to 0.1 x VDD, CL= 10 pF, DRV<1:0>=HH Input Capacitance CIN — — Logic High Level Input Voltage VIH VDD – 0.6 — Logic Low Level Input Voltage VIL — — 0.6 V Input Current IIN 0<VIN< VDD –100 — 100 nA Input Current If Pullup is Activated IINP VIL=0 V 5 — 25 μA IOmaxLL DRV<1:0>=LL 0.1 0.5 0.8 mA IOmaxLH DRV<1:0>=LH 0.9 2.3 3.5 mA IOmaxHL DRV<1:0>=HL 1.5 3.1 4.8 mA IOmaxHH DRV<1:0>=HH IOH< IOmax source, VDD=1.8 V IOL< IOmax sink, VDD=1.8 V 1.8 3.6 5.4 mA VDD – 0.6 — — V — — 0.6 V Maximum Output Current Logic High Level Output Voltage VOH Logic Low Level Output Voltage VOL V Note: All specification guaranteed by production test unless otherwise noted. 8 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 7. Absolute Maximum Ratings Parameter Value Unit –0.3, +3.6 V Voltage on Digital Control Inputs –0.3, VDD + 0.3 V Voltage on Analog Inputs –0.3, VDD + 0.3 V +10 dBm –40 to +85 ℃ Thermal Impedance θ JA 30 ℃/W Junction Temperature TJ +125 ℃ –55 to +125 ℃ VDD to GND RX Input Power Operating Ambient Temperature Range T A Storage Temperature Range TSTG Note: Stresses beyond those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Caution: ESD sensitive device. 9 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 2. Functional Description The RFM31 is ISM wireless receiver module with continuous frequency tuning over the complete 240–960 MHz band. The wide operating voltage range of 1.8–3.6 V and low current consumption makes the RFM31 and ideal solution for battery powered applications. The RFM31 uses a single-conversion, image-reject mixer to downconvert the 2-level FSK/GFSK/OOK modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a high performance △∑ ADC allowing filtering, demodulation, slicing, error correction, and packet handling to be performed in the built-in DSP increasing the receiver‘s performance and flexibility versus analog based architectures. The demodulated signal is then output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO. A high precision local oscillator (LO) is generated by an integrated VCO and △∑ Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates, output frequency, frequency deviation, and Gaussian filtering at any frequency between 240–960 MHz. The RFM31 is designed to work with a microcontroller to create a very low cost system. Voltage regulators are integrated on-chip which allow for a wide range of operating supply voltage conditions from +1.8 to +3.6 V. A standard 4-pin SPI bus is used to communicate with the microcontroller. Three configurable general purpose I/Os are available for use to tailor towards the needs of the system. A more complete list of the available GPIO functions is shown in "8. Auxiliary Functions" but just to name a few, microcontroller clock output, Antenna Diversity, Antenna SwitchPOR, and specifc interrupts. The RFM31application shown in Figure 1. Figure 1. RFM31 Application Example 10 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 2.1. Operating Modes The RFM31 provides several modes of operation which can be used to optimize the power consumption of the device application. Depending upon the system communication protocol, the optimal trade-off between the radio wake time and power consumption can be achieved. Table 8 summarizes the modes of operation of the RFM31. In general, any given mode of operation may be classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception the Shutdown mode, all can be dynamically selected by sending the appropriate commands over the SPI in order to optimize the average current consumption. An ―X‖ in any cell means that, in the given mode of operation, that block can be independently programmed to be either ON or OFF, without noticeably affecting the current consumption. The SPI circuit block includes the SPI interface and the register space. The 32 kHz OSC circuit block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal oscillator, and wake-up timer. AUX (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector. Table 8. Operating Modes Mode Name Shutdown Circuit Blocks Digital LDO OFF SPI SPI 32 kHz 30 MHz OSC AUX XTAL PLL RX IVDD OFF OFF OFF OFF OFF OFF 10 nA ON ON OFF OFF OFF OFF OFF 400 nA (Register contents retained) ON ON X OFF OFF OFF 800 nA Sensor ON X ON OFF OFF OFF 1 μA Ready ON X X ON OFF OFF 600 μA Tuning ON X X ON ON OFF 9.5 mA Receive ON X X ON ON ON 18.5 mA (Register contents lost) Standby Sleep 11 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 3. Controller Interface 3.1. Serial Peripheral Interface (SPI) The RFM31 communicates with the host MCU over a 3 wire SPI interface: SCLK, SDI, and nSEL. The host MCU can also read data from internal registers on the SDO output pin. A SPI transaction is a 16-bit sequence which consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA), as demonstrated in Figure 1. The 7-bit address field supports reading from or writing to one of the 128, 8-bit control registers. The R/W select bit determines whether the SPI transaction is a write or read transaction. If R/W = 1, it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the RFM31 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9. The SCLK rate is flexible with a maximum rate of 10 MHz. Figure 2. SPI Timing Table 9. Serial Interface Timing Parameters Symbol Parameter Min tCH Clock high time 40 tCL Clock low time 40 tDS Data setup time 20 tDH Data hold time 20 tDD Output data delay time 20 tEN Output enable time 20 tDE Output disable time 50 tSS Select setup time 20 tSH Select hold time 50 tSW Select high period 80 Diagram To read back data from the RFM31, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin. The READ function is shown in Figure 3. After the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup. 12 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Figure 3. SPI Timing—READ Mode The SPI interface contains a burst read/write mode which will allows for reading/writing sequential registers without having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address. An SPI burst write transaction is demonstrated in Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be latched into the RFM31 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5. Figure 4. SPI Timing—Burst Write Mode Figure 5. SPI Timing—Burst Read Mode 13 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 3.2. Operating Mode Control There are three primary states in the RMF31 radio state machine: SHUTDOWN, IDLE, and RX (see Figure 6). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the module to the applications needs. "Register 07h. Operating Mode and Function Control 1" controls which operating mode/state is selected. The RX state may be reached automatically from any of the IDLE states by setting the rxon bit in "Register 07h. Operating Mode and Function Control 1". Table 10 shows each of the operating modes with the time required to reach RX mode as well as the current consumption of each mode. The output of the LPLDO is internally connected in parallel to the output of the main digital regulator (and is available externally at the VR_DIG pin); this common digital supply voltage is connected to all digital circuit blocks, including the digital modem, crystal oscillator, and SPI and register space. The LPLDO has extremely low quiescent current consumption but limited current supply capability; it is used only in the IDLE-STANDBY and IDLE-SLEEP modes. Figure 6. State Machine Diagram Table 10. Operating Modes State/Mode xtal pll wt LBD or TS Response Time to RX Current in State /Mode [μA] Shut Down State X X X X 16.21 ms 10 nA Standby Mode 0 0 0 0 1.21 ms 400 nA Sleep Mode 0 0 1 0 800 nA Sensor Mode 0 0 X 1 1 μA Ready Mode 1 0 X X 210 μs 600 μA Tune Mode 1 1 X X 200 μs 9.5 mA RX State 1 1 X X NA 18.5 mA Idle States: 14 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 3.2.1. Shutdown State The shutdown state is the lowest current consumption state of the device with nominally less than 10 nA of current consumption. The shutdown state may be entered by driving the SDN pin high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access. When the module is connected to the power supply, a POR will be initiated after the falling edge of SDN. 3.2.2. Idle State There are four different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and Function Control 1". All modes have a tradeoff between current consumption and response time to RX mode. This tradeoff is shown in Table 10. After the POR event, SWRESET, or exiting from the SHUTDOWN state the module will default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock correctly. 3.2.2.1. STANDBY Mode STANDBY mode has the lowest current consumption possible with only the LPLDO enabled to maintain the register values. In this mode the registers can be accessed in both read and write mode. The standby mode can be entered by writing 0h to Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.2. SLEEP Mode In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up the radio at specified intervals. See "8.6. Wake-Up Timer" for more information on the Wake-Up-Timer. Sleep mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.3. SENSOR Mode In SENSOR Mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 and the temperature sensor can be enabled by setting ents = 1 in "Register 07h. Operating Mode and Function Control 1". See "8.4.Temperature Sensor" and "8.5. Low Battery Detector" for more information on these features. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 3.2.2.4. READY Mode READY Mode is designed to give a fast transition time to RX mode with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing the time required to switch to the RX mode by eliminating the crystal start-up time. Ready mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control 1". To achieve the lowest current consumption state the crystal oscillator buffer should be disabled. This is done by setting "Register 62h. Crystal Oscillator/Power-on-Reset Control" to a value of 02h. To exit ready mode, bufovr (bit 1) of this register must be set back to 0. 3.2.2.5. TUNE Mode In TUNE Mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the fastest response to RX mode as the PLL will remain locked but it results in the highest current consumption. This mode of operation is designed for Frequency Hopping Systems (FHS). Tune mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode, theinternal state machine automatically enables the crystal oscillator. 3.2.3. RX State The RX state may be entered from any of the Idle modes when the rxon bit is set to 1 in "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occur automatically to get the module into RX mode when going from STANDBY mode to RX mode by setting the rxon bit: 15 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 1. Enable the Main Digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is ―0‖, default value is ―1‖). 5. Wait until PLL settles to required transmit frequency (controlled by timer). 6. Enable receive circuits: LNA, mixers, and ADC. 7. Calibrate ADC (RC calibration). 8. Enable receive mode in the digital modem. Depending on the configuration of the radio all or some of the following functions will be performed automatically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional) including sync word, header check, and CRC. 3.2.4. Device Status Add R/W Function/Description 02 R Device Status D7 D6 ffovfl ffunfl D5 D4 rxffem D3 D2 headerr D1 D0 cps[1] cps[0] POR Def. — The operational status of the module can be read from "Register 02h. Device Status". 16 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 3.3. Interrupts The RFM31 is capable of generating an interrupt signal when certain events occur. The module notifies the microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit; the nIRQ output signal will then be reset until the next change in status is detected. All of the interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt status register. If the interrupt is not enabled when the event occurs inside of the module it will not trigger the nIRQ pin, but the status may still be read correctly at anytime in the Interrupt Status registers. Add R/W 03 R 04 Function/De POR D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Status 1 ifferr Reserved Reserved irxffafull iext Reserved ipkvalid icrcerror — R Interrupt Status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor — 05 R/W Interrupt Enable1 enfferr Reserved Reserved enrxffafull enext Reserved enpkvalid 06 R/W scription Def. encrcerr 00h or Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor 01h See ―Register 03h. Interrupt/Status 1,‖ and ―Register 04h. Interrupt/Status 2,‖ for a complete list of interrupts. 3.4. Device Code The device version code is readable from "Register 01h. Version Code (VC)". This is a read only register. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. Notes 01 R Device Version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 00h DV 17 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 3.5. System Timing The system timing for RX mode is shown in Figure 7. If a small range of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at the initial power up of the device. The relevant system timing registers are shown below. Function/De Add R/W 53 R/W PLL Tune Time 54 R/W Reserved 1 55 R/W scription D7 D6 D5 D4 D3 D2 D1 pllts[4:0] X X X Calibration xtalstart adccaldo Control half ne D0 POR Def. pllt0[2:0] X X enrcfcal rccal X Vcoca ldp 45h X X 00h vcocal skipvco 04h The VCO will automatically calibrate at every frequency change or power up. The VCO CAL may also be forced by setting the vcocal bit. The 32.768 kHz RC oscillator is also automatically calibrated but the calibration may also be forced. The enrcfcal will enable the RC Fine Calibration which will occur every 30 seconds. The rccal bit will force a complete calibration of the RC oscillator which will take approximately 2 ms. The PLL T0 time is to allow for bias settling of the VCO, the default for this should be adequate. The PLL TS time is for the settling time of the PLL, which has a default setting of 200 μs. This setting should be adequate for most applications but may be reduced if small frequency jumps are used. For more information on the PLL register configuration options, see ―Register 53h. PLL Tune Time,‖ and ―Register 55h. Calibration Control,‖. Figure 7. RX Timing 18 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 3.6. Frequency Control 3.6.1. Frequency Programming In order to transmit an RF signal, the desired channel frequency, fcarrier, must be programmed into the RFM31.Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier frequency is generated rd by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3 order) ΔΣ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer part (N) and a fractional part (F).In a generic sense, the output frequency of the synthesizer is: fout = 10MHz x (N + F) The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]), and Frequency Modulation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is discussed further in "3.6.4. Frequency Deviation". Also, a fixed offset can be added to fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency is shown below: f carrier = 10MHz x (hbsel + 1) x (N + F) fc[15: 0] fTX =10MHz *(hbsel+ 1)*( fb[4 : 0] +24+ 64000 ) Add R/W 73 R/W 74 R/W 75 R/W 76 R/W 77 R/W Function/Descr POR D7 D6 D5 D4 D3 D2 D1 D0 Frequency Offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h Frequency Offset2 Reserved Reserved Reserved Reserved fo[9] fo[8] 00h Reserved sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 35h fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h iption Frequency Band Select Nominal Carrier Frequency 1 Nominal Carrier Frequency 0 Reserved Reserved Def. The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connecting a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h.Frequency Band Select". This effectively partitions the entire 240–930 MHz frequency range into two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer part has a fixed offset of 24 added to it as shown in the formula above. Table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band. After selection of the fb (N) the fractional component may be solved with the following equation: ( 10MHz *f(hbsel + 1) fc[15:0]= TX - fb[4:0]-24) * 64000 fb and fc are the actual numbers stored in the corresponding registers. 19 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 11. Frequency Band Selection fb[4:0] Value N 0 Frequency Band hbsel=0 hbsel=1 24 240–249.9 MHz 480–499.9 MHz 1 25 250–259.9 MHz 500–519.9 MHz 2 26 260–269.9 MHz 520–539.9 MHz 3 27 270–279.9 MHz 540–559.9 MHz 4 28 280–289.9 MHz 560–579.9 MHz 5 29 290–299.9 MHz 580–599.9 MHz 6 30 300–309.9 MHz 600–619.9 MHz 7 31 310–319.9 MHz 620–639.9 MHz 8 32 320–329.9 MHz 640–659.9 MHz 9 33 330–339.9 MHz 660–679.9 MHz 10 34 340–349.9 MHz 680–699.9 MHz 11 35 350–359.9 MHz 700–719.9 MHz 12 36 360–369.9 MHz 720–739.9 MHz 13 37 370–379.9 MHz 740–759.9 MHz 14 38 380–389.9 MHz 760–779.9 MHz 15 39 390–399.9 MHz 780–799.9 MHz 16 40 400–409.9 MHz 800–819.9 MHz 17 41 410–419.9 MHz 820–839.9 MHz 18 42 420–429.9 MHz 840–859.9 MHz 19 43 430–439.9 MHz 860–879.9 MHz 20 44 440–449.9 MHz 880–899.9 MHz 21 45 450–459.9 MHz 900–919.9 MHz 22 46 460–469.9 MHz 920–930.0 MHz 23 47 470–479.9 MHz — The module will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in the RX Mixing architecture. 20 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 3.6.2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the RFM31, it is often easier to think in terms of ―channels‖ or ―channel numbers‖ rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size (fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency Hopping Channel Select Register then selects channels based on multiples of the step size. Fcarrier= Fnom + fhs[7 : 0] X ( fhch[7 : 0] X 10kHz) For example: if the nominal frequency is set to 900 MHz using Registers 73h–77h and the channel step size is set to 1 MHz using "Register 7Ah. Frequency Hopping Step Size". For example, if the "Register 79h. Frequency Hopping Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. Add R/W 79 R/W 7A R/W Function/Descript ion Frequency Hopping Channel Select Frequency Hopping Step Size POR D7 D6 D5 D4 D3 D2 D1 D0 fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch [2] fhch [1] fhch [0] 00h fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h Def. 3.6.3. Automatic Frequency Change If registers 79h or 7Ah are changed in TX mode, the state machine will automatically transition the module back to tune and change the frequency. This feature is useful to reduce the number of SPI commands required in a Frequency Hopping System. This in turn reduces microcontroller activity, reducing current consumption. 3.6.4. Frequency Deviation The peak frequency deviation is configurable from ±1 to ±320 kHz. The Frequency Deviation (Δf) is controlled by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier frequency setting. When enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviation will remain in increments of 625 Hz. When using frequency modulation the carrier frequency will deviatefrom the nominal center channel carrier frequency by ±Δf: △ f = fd [8: 0] X 625Hz △f fd [8: 0] = 625Hz △f = peak deviation 21 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Figure 8. Frequency Deviation The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see "4.1. Modulation Type" for further details. Add R/W 71 R/W 72 R/W Function/Des cription Modulation Mode Control 2 Frequency Deviation POR D7 D6 D5 D4 D3 D2 D1 D0 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h fd [7] fd [6] fd [5] fd [4] fd [3] fd [2] fd [1] fd [0] 43h Def. 22 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 3.6.5. Frequency Offset Adjustment When the AFC is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to get a negative offset you will need to take the twos complement of the positive offset number. The offset can be calculated by the following: DesiredOffset = 156.25Hz x (hbsel + 1) x fo[9 : 0] DesiredOffset fo[9 : 0] = 156.25Hz x (hbsel + 1) The adjustment range in high band is: ±160 kHz, and adjustment range in low band is: ±80 kHz. For example to compute an offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band mode the fo[9:0] register should be set to 360h. When AFC is enabled the same registers can be used to read the offset value as automatically obtained by the AFC. A stable offset value can read after preamble detection using the preamble detection or sync word detection interrupt. Function/Descri Add R/W 73 R/W Frequency Offset 74 R/W Frequency Offset ption POR Not Def. es fo[1] 00h 73 fo[8] 00h D7 D6 D5 D4 D3 D2 D1 D0 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] Reserved Reserv Reserv Reserv Reserv Reserv ed ed ed ed ed fo[9] 3.6.6. Auto Frequency Control (AFC) The receiver supports automatic frequency control (AFC) to compensate for frequency differences between the transmitter and receiver reference frequencies. These differences can be caused by the absolute accuracy and temperature dependencies of the reference crystals. Due to frequency offset compensation in the modem, the receiver is tolerant to frequency offsets up to 0.25 times the IF bandwidth when the AFC is disabled. When the AFC is enabled, the received signal will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range of frequency offsets up to 0.35 times the IF bandwidth. The trade-off of receiver sensitivity (at 1% PER) versus carrier offset and the impact of AFC are illustrated in Figure 9. Figure 9. Sensitivity at 1% PER vs. Carrier Frequency Offset 23 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 The AFC function shares registers 73h and 74h with the Frequency Offset setting. If AFC is enabled (D6 in ―Register 1Dh. AFC Loop Gearshift Override,‖), the Frequency Offset shows the results of the AFC algorithm for the current receive slot. When selecting the preamble length, the length needs to be long enough to settle the AFC. In general two bytes of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened by about 8 bits. Note that with the AFC disabled, the preamble length must still be long enough to settle the receiver and to detect the preamble (see "6.6. Preamble Length"). The AFC corrects the detected frequency offset by changing the frequency of the Fractional-N PLL. When the preamble is detected, the AFC will freeze. In multi-packet mode the AFC is reset at the end of every packet and will re-acquire the frequency offset for the next packet. An automatic reset circuit prevents excessive drift by resetting the AFC loop when the tuning exceeds 2 times the frequency deviation (as set by fd[8:0] in register 71h and 72h) in high band or 1 times the frequency deviation in low band. This range can be halved by the ―afcbd‖ bit in register 1Dh. Frequency Correction Add R/W 1D R/W AFC disabled Freq Offset Register AFC enabled AFC Function/Descrip tion AFC Loop Gearshift Override D7 D6 D5 D4 D3 afcbd enafc afcgearh afcgear afcgear [2] h[1] h[0] D2 D1 D0 afcgearl[2] afcgearl[1] afcgearl[0] POR Def. 40h 24 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 4. Modulation Options 4.1. FIFO Mode In FIFO mode, the integrated FIFO is used to receive the data. The FIFO is accessed via "Register 7Fh. FIFO Access" with burst read capability. The FIFO may be configured specific to the application packet size, etc. (see "6. Data Handling and Packet Handler" for further information). When in FIFO mode the module will automatically exit the RX State when the ipkvalid interrupt occurs. The module will return to any of the other states based on the settings in "Register 07h. Operating Mode and Function Control 1". In RX mode the rxon bit will only be cleared if ipkvalid occurs. A CRC, Header, or Sync error will generate an interrupt and the microcontroller will need to decide on the next action. 25 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 5. Internal Functional Blocks This section provides an overview some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 240–960 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of gain control which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal performance. 5.2. RX I-Q Mixer The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs are driven in quadrature, and separate I and Q Intermediate Frequency (IF) outputs drive the programmable gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO output. 5.3. Programmable Gain Amplifier The Programmable Gain Amplifier (PGA) provides the necessary gain to boost the signal level into the Dynamic Range of the ADC. The PGA must also have enough gain switching to allow for large input signals to ensure a linear RSSI range up to –20 dBm. The PGA is designed to have steps of 3 dB which are controlled by the AGC algorithm in the digital modem. 5.4. ADC The amplified I&Q IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low current consumption and high dynamic range. The bandpass response of the ADC provides exceptional rejection of out of band blockers. 5.5. Digital Modem Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the following functions: Channel RX Selection Filter Demodulation AGC Preamble Invalid Radio Preamble Detector Signal Strength Indicator (RSSI) Automatic Packet Cyclic Detector Frequency Compensation (AFC) Handling including EZMac™ features Redundancy Check (CRC) The digital Channel Filter and Demodulator are optimized for ultra low power consumption and are highly configurable. Supported modulation types are GFSK, FSK, and OOK. The Channel Filter can be configured to support a large choice of bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported ranging from 1 up to 128 kbps. The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The configurable Preamble Detector is used to improve the reliability of the Sync-word detection. The Sync-word detector is only enabled when a valid preamble is detected, significantly reducing the probability of false Sync-word detection. 26 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 The Invalid Preamble Detector issues an interrupt when no valid preamble signal is found. After the receiver is enabled, the Invalid Preamble Detector output is ignored for 16 Tb (Where Tb is the time of a bit duration) to allow the receiver to settle. The Invalid Preamble Detect interrupt can be used to save power and speed-up search in receive mode. It is advised to mask the invalid preamble interrupt when Antenna Diversity is enabled. The Received Signal Strength Indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), and carrier sense (CS) functionality. Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital Automatic Frequency Control (AFC) in receive mode. A comprehensive programmable Packet Handler including key features of EZMacTM is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast, group, and point-to-point communication. A wireless communication channel can be corrupted by noise and interference, and it is therefore important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the tail of each transmitted packet and verified by the receiver to confirm that no errors have occurred. The Packet Handler and CRC are extremely valuable features which can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. 5.6. Synthesizer An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided on-chip. Using a ΣΔ synthesizer has many advantages; it provides large amounts of flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The PLL and Δ-Σ modulator scheme is designed to support any desired frequency and channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). Figure 10. PLL Synthesizer Block Diagram The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip spiral inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the desired output frequency band. The modulus of this divider stage is controlled dynamically by the output from the Δ-Σ modulator. The tuning resolution of the Δ-Σ modulator is determined largely by the over-sampling rate and the number of bits carried internally. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–960 MHz. 5.6.1. VCO The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select". A 2X VCO is utilized to help avoid problems due to frequency pulling, especially when turning on the integrated Power Amplifier. In receive mode, the LO frequency is automatically shifted downwards (without reprogramming) by the IF frequency of 937.5 kHz, allowing receive 27 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 operation on the same frequency. The VCO integrates the resonator inductor, tuning varactor, so no external VCO components are required. The VCO uses capacitance bank to cover the wide frequency range specified. The capacitance bank will automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not be desirable so the VCO calibration may be skipped by setting the appropriate register. 5.7. Crystal Oscillator For RF31 IC The RFM31 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 μs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the 30 MHz crystal blank. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to slightly adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load Capacitance". The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit is a course shift in frequency but is not binary with xlc[6:0]. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to slightly adjust the frequency of the crystal oscillator. This latter function can be used to compensate for crystal production tolerances. Utilizing the on-chip temperature sensor and suitable control software even the temperature dependency of the crystal can be canceled. The crystal load capacitance is programmed using register 09h. The typical value of the total on-chip (internal) capacitance Cint can be calculated as follows: Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift Note that the course shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning. See more on this, calculating Cext and crystal selection guidelines in "11. Application Notes". If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency Offset field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as discussed in "3.6.Frequency Control". The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for the entire system and the BOM cost is reduced. The available clock frequencies (i.e., internal division ratios) and the GPIO configuration are discussed further in "8.2. Microcontroller Clock". The RF31 may also be driven with an external 30 MHz clock signal through the XIN pin. Add R/W 09 R/W Function/Descripti on Crystal Oscillator Load Capacitance D7 D6 D5 D4 D3 D2 D1 D0 xtalshift xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] POR Def. 40h 5.8. Regulators There are a total of six regulators integrated onto the RFM31. With the exception of the IF and Digital all regulators are designed to operate with only internal decoupling. The IF and Digital regulators both require an external 1μ f decoupling capacitor. All of the regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V, and produce a nominal regulated output voltage of +1.7 V ±5%. The internal circuitry nominally operates from this regulated +1.7 V supply. A supply voltage should only be connected to the VDD pins. No voltage should be forced on the IF or DIG regulator outputs. 28 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 6. Data Handling and Packet Handler 6.1. RX FIFO A 64 byte FIFO is integrated into the module for RX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to access the FIFO. A burst read, as described in "3.1. Serial Peripheral Interface (SPI)", from address 7Fh will read data from the RX FIFO. Figure 11. FIFO Threshold Add R/W 08 R/W Function/Descri ption Operating &Function D7 D6 D5 D4 D3 D2 D1 D0 antdi antdiv[1] antdiv[0] rxmpk Reserve enldm ffclrrx Reserved v[2] Control 2 POR Def. 00h d The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the incoming RX data reaches the Almost Full Threshold an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. Add R/W 7E R/W Function/D D7 D6 D5 D4 Reserved Reserved rxafthr[5] rxafthr[4] escription RX FIFO Control D3 D2 D1 D0 rxafthr rxafthr rxafthr rxafthr [3] [2] [1] [0] POR Def. 37h The RX FIFO may be cleared or reset with the ffclrrx bit in ―Register 08h. Operating Mode and Function Control 2,‖. All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and ―Register 06h. Interrupt Enable 2,‖. If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers. 29 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 6.2. Packet Configuration When using the FIFO, automatic packet handling may be enabled for the RX mode. "Register 30h. Data Access Control" through ―Register 39h. Synchronization Word 0,‖ and ―Register 3Fh. Check Header 3,‖ through ―Register 4Bh. Received Packet Length,‖ control the configuration, status, and decoded RX packet data for Packet Handling. The general packet structure is shown in Figure 12. The length of each field is shown below the field. The preamble pattern is always a series of alternating ones and zeroes, starting with a one. All the fields have programmable lengths to accommodate different applications. The most common CRC polynominals are available for selection. Figure 12. Packet Structure An overview of the packet handler configuration registers is shown in Table 13. A complete register description can be found in ―12.1. Complete Register Table and Descriptions‖. 6.3. Packet Handler RX Mode 6.3.1. Packet Handler Disabled When the packet handler is disabled certain portions of the packet handler are still required. Proper modem operation requires preamble and sync, as shown in Figure 13. Bits after sync will be treated as raw data with no qualification. This mode allows for the creation of a custom packet handler when the automatic qualification parameters are not sufficient. Manchester encoding is supported but the use of data whitening, CRC, or header checks is not. Figure 13. Required RX Packet Structure with Packet Handler Disabled 6.3.2. Packet Handler Enabled When the packet handler is enabled, all the fields of the packet structure need to be configured. If multiple packets are desired to be stored in the FIFO, then there are options available for the different fields that will be stored into the FIFO. Figure 14 demonstrates the options and settings available when multiple packets are enabled. Figure 15 demonstrates the operation of fixed packet length and correct/incorrect packets. 30 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Figure 14. Multiple Packets in RX Packet Handler Figure 15. Multiple Packets in RX with CRC or Header Error CRC Handling Manchester Whitening Option FIFO 10 0 option set — set — option — Direct 0X X set set — — — FIFO option in option Data Storage set Handling option Header set Sync option Preamble & 1 CLK IO enpacrx 10 and dtmod[1:0] FIFO_PH Direct Data Data modes word detection Table 12. RX Packet Handler Configuration Optional for sync-detection — 31 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 13. Packet Handler Registers 32 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 6.4. Data Whitening, Manchester Encoding, and CRC Data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to achieve a more uniform spectrum. When enabled, the payload data bits are XORed with a pseudorandom sequence output from the built-in PN9 generator. The generator is initialized at the beginning of the payload. The receiver recovers the original data by repeating this operation. Manchester encoding can be used to ensure a dc-free transmission and good synchronization properties. When Manchester encoding is used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled due to the nature of the encoding. The effective datarate when using Manchester encoding is limited to 64 kbps. Data Whitening and Manchester encoding can be selected with "Register 70h. Modulation Mode Control 1". The CRC is configured via "Register 30h. Data Access Control". Figure 16. Operation of Data Whitening, Manchester Encoding, and CRC 6.5. Preamble Detector The RFM31 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length", as described in ―6.2. Packet Configuration‖. The preamble detection threshold, preath[4:0] as set in "Register 35h. Preamble Detection Control 1", is in units of 4 bits. The preamble detector searches for a preamble pattern with a length of preath[4:0]. When a false preamble detect occurs, the receiver will continuing searching for the preamble when no sync word is detected. The Preamble Detector output may be programmed onto one of the GPIOs or read in the Interrupt Status registers. 6.6. Preamble Length The required preamble length threshold will depend on when the receive mode is entered in relation to the transmitted packet. When the receiver is enabled long before the arrival of the packet, then a short preamble detection threshold might result in false detects on the received noise before the actual preamble arrives. In this case, it is recommended to program a 20 bit preamble detection threshold. A shorter Preamble Detection Threshold might be chosen when occasional false detects are tolerable. When antenna diversity is enabled, it is advised to use a 20 bit preamble detection threshold. When the receiver is synchronously enabled just before the start of the packet, then a shorter preamble detection threshold might be chosen (e.g., 8 bit). The required preamble length is determined from the sum of the receiver settling time and the preamble detection threshold. The receiver settling time is listed in Table 14. 33 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 14. Minimum Receiver Settling Time Mode Approximate Recommended preamble Recommended preamble receiver settling time length with 8-bit length with 20-bit detection threshold detection threshold (G)FSK AFC Disabled 1 byte 20 bits 32 bits (G)FSK AFC Enabled 2 byte 28bits 40 bits 1 byte — 64 bits 2 byte — 8 byte 2 byte 3 byte 4 byte 8 byte — 8 byte (G)FSK AFC Disabled +Antenna Diversity Enabled (G)FSK AFC Enabled +Antenna Diversity Enabled OOK OOK + Antenna Diversity Enabled Note: The recommended preamble length and the preamble detection threshold may be shortened when occasional packet errors are tolerable. 6.7. Invalid Preamble Detector When scanning channels in a Frequency Hopping System, it is desirable to determine if a channel is valid in the minimum amount of time. The preamble detector can output an invalid preamble detect signal. When an error is detected in the preamble, the Invalid Preamble Detect signal (nPQD) is asserted, indicating an invalid channel. The signal can be used to qualify the channel without requiring the full preamble to be received. The Preamble Detect and Invalid Preamble Detect signals are available in "Register 03h. Interrupt/Status 1" and ―Register 04h. Interrupt/Status 2,‖. The Invalid Preamble Detector issues an interrupt when no valid preamble signal is found. After the receiver is enabled, the Invalid Preamble Detector will be held low for 16 Tb (Tb is the time of the bit duration) to allow the receiver to settle. The 16 Tb is a fixed time which will work with a 4-byte Preamble (or longer) when AFC is enabled, or a 3-byte preamble (or longer) when AFC is disabled. The invalid preamble detect interrupt can be useful to save power and speed-up search in receive mode. It is advised to disable the invalid preamble interrupt when Antenna Diversity is enabled. The Invalid Preamble Detect interrupt may be triggered during the Antenna Diversity algorithm if one of the antennas is weak but the other is capable of still receiving the signal if the Antenna Diversity algorithm is allowed to complete. 34 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 7. RX Modem Configuration 7.1. Modem Settings for FSK and GFSK The modem performs channel selection and demodulation in the digital domain. The channel filter bandwidth is configurable from 620 to 2.6 kHz. The data-rate, modulation index, and bandwidth are set via registers 1C–25. The modulation index is equal to 2 times the peak deviation divided by the data rate (Rb). Table 15 gives the modem register settings for various common data-rates. Select the desired data-rate (Rb), and Deviation (Fd) to determine the proper register settings. For data-rates and modulation types not listed in the table a calculator tool within EXCEL can be used. When Manchester coding is disabled, the required channel filter bandwidth is calculated as BW = 2 x (Fd + 0.25Rb) where Fd is the frequency deviation and Rb is the data rate. For modulation indices below 1 the required channel filter bandwidth is calculated as BW = Fd + Rb. The channel filter needs to be increased when the frequency offset between transmitter and receiver is more than half the channel filter bandwidth. In this case it is recommended to enable the AFC and choose the IF bandwidth equal to 2 x frequency offset. Table 15. RX Modem Configurations for FSK and GFSK RX Modem setting examples for GFSK and FSK Application parameters Rb Fd kbps kHz 2 5 2.4 mod index Register values (hex) BW -3dB dwn3_bypass ndec_exp[2:0] filset[3:0] rxosr[10:0] ncoff[19:0] crgain[10:0] kHz 1Ch 1Ch 1Ch 20,21h 21,22,23h 24,25h 5.00 11.5 0 3 3 0FA 08312 06B 4.8 4.00 11.5 0 3 3 0D0 09D49 0A0 2.4 36 30.00 75.2 0 0 1 683 013A9 005 4.8 4.8 2.00 12.1 0 3 4 068 13A93 278 4.8 45 18.75 95.3 0 0 4 341 02752 00A 9.6 4.8 1.00 18.9 0 2 1 068 13A93 4EE 9.6 45 9.38 95.3 0 0 4 1A1 04EA5 024 10 5 1.00 18.9 0 2 1 064 147AE 521 10 40 8.00 90 0 0 3 190 051EC 02B 19.2 9.6 1.00 37.7 0 1 1 068 13A93 4EE 20 10 1.00 37.7 0 1 1 064 147AE 521 20 40 4.00 95.3 0 0 4 0C8 0A3D7 0A6 38.4 19.6 1.02 75.2 0 0 1 068 13A93 4D5 40 20 1.00 75.2 0 0 1 064 147AE 521 40 40 2.00 112.1 0 0 5 064 147AE 291 50 25 1.00 75.2 0 0 1 050 1999A 668 57.6 28.8 1.00 90 0 0 3 045 1D7DC 76E 100 50 1.00 191.5 1 0 F 078 11111 446 100 300 6.00 620.7 1 0 E 078 11111 0B8 125 125 2.00 335.5 1 0 8 060 15555 2AD 35 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 7.1.1. Advanced FSK and GFSK Settings In nearly all cases, the information in Table 15, ―RX Modem Configurations for FSK and GFSK,‖ can be used to determine the required FSK and GFSK modem parameters. The section includes a more detailed discussion of the various modem parameters to allow for experienced designers to further configure the modem performance. In FSK or GFSK mode the receiver can handle a wide range of modulation indices ranging from 0.5 up to 32. The modulation index (h) is defined by the following: 2×Fd h = Rb×(1+enmanch) When the modulation index is 1 or higher the modulation bandwidth can be approximated by the following equation: (Rb2 ×(1+enmanch)+2×Fd) BWmod = When the modulation index is lower than 1 the modulation bandwidth can be approximated by the following: ) ( BWmod = Rb×(1+enmanch)+ Fd Where BWmod is an approximation of the modulation bandwidth in kHz, Rb is the payload bit rate in kbps, Fd is the frequency deviation of the received GFSK/FSK signal in kHz and enmanch is the Manchester Coding parameter (see Reg. 70h, enmach is 1 when Manchester coding is enabled, enmanch is 0 when disabled). The bandwidth of the channel select filter in the receiver might need some extra bandwidth to cope with tolerances in transmit and receive frequencies which depends on the tolerances of the applied crystals. When the relative frequency error (Ferror) between transmitter and receiver is less than half the modulation bandwidth (BWmod) then the AFC will correct the frequency error without needing extra bandwidth. When the frequency error exceeds BWmod/2 then some extra bandwidth will be needed to assure proper AFC operation under worst case conditions. When the AFC is enabled it is recommended to set the bandwidth of the channel select filter (BWch-sel) according to the formulas below: F error ≤ F error > BWmod 2 BWmod 2 => BW ch-sel = BWmod => BW ch-sel = 2×F error When the AFC is disabled it is recommended to set the bandwidth of the channel select filter (BWch-sel) according to the following: BW ch-sel = BWmod+2×F error When the required bandwidth (BW) is calculated then the three filter parameters, ndec_exp, dwn3_bypass and filset, can be found from the table below. When the calculated bandwidth value is not exactly available then select the higher available bandwidth closest to the calculated bandwidth. 36 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 16. Filter Bandwidth Parameters BW ndec_exp dwn3_bypass filset BW ndec_exp dwn3_bypass filset [kHz] 1C-[6:4] 1C-[7] 1C-[3:0] [kHz] 1C-[6:4] 1C-[7] 1C-[3:0] 2.6 5 0 1 41.7 1 0 2 2.8 5 0 2 45.2 1 0 3 3.1 5 0 3 47.9 1 0 4 3.2 5 0 4 56.2 1 0 5 3.7 5 0 5 64.1 1 0 6 4.2 5 0 6 69.2 1 0 7 4.5 5 0 7 75.2 0 0 1 4.9 4 0 1 83.2 0 0 2 5.4 4 0 2 90.0 0 0 3 5.9 4 0 3 95.3 0 0 4 6.1 4 0 4 112.1 0 0 5 7.2 4 0 5 127.9 0 0 6 8.2 4 0 6 137.9 0 0 7 8.8 4 0 7 142.8 1 1 4 9.5 3 0 1 167.8 1 1 5 10.6 3 0 2 181.1 1 1 9 11.5 3 0 3 191.5 0 1 15 12.1 3 0 4 225.1 0 1 1 14.2 3 0 5 248.8 0 1 2 16.2 3 0 6 269.3 0 1 3 17.5 3 0 7 284.9 0 1 4 18.9 2 0 1 335.5 0 1 8 21.0 2 0 2 361.8 0 1 9 22.7 2 0 3 420.2 0 1 10 24.0 2 0 4 468.4 0 1 11 28.2 2 0 5 518.8 0 1 12 32.2 2 0 6 577.0 0 1 13 34.7 2 0 7 620.7 0 1 14 37.7 1 0 1 37 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 7.2. Modem Settings for OOK The RFM31 is configured for OOK mode by setting the modtyp[1:0] field to OOK in "Register 71h. Modulation Mode Control 2". In OOK mode, the following parameters can be configured: data rate, manchester coding, channel filter bandwidth, and the clock recovery oversampling rate. Manchester coding is enabled by setting enmanch in Register 70h. The receive channel select filter bandwidth is configured via "Register 1Ch. IF Filter Bandwidth". The register settings for the available channel bandwidth bandwidths are shown in Table 17. Table 17. Channel Filter Bandwidth Settings BW[kHz] dwn3_bypass filset[3:0] 75.2 0 1 83.2 0 2 90 0 3 95.3 0 4 112.1 0 5 127.9 0 6 137.9 0 7 191.5 1 F 225.1 1 1 248.8 1 2 269.3 1 3 284.9 1 4 335.5 1 8 361.8 1 9 420.2 1 10 468.4 1 11 518.8 1 12 577 1 13 620.7 1 14 The proper settings for ndec[2:0] are listed in Table 18 where Rb is the data rate (Rb) which is doubled when Manchester coding is enabled. 38 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 18. ndec[2:0] Settings Rb(1+ enmanch) [kbps] ndec[2:0] Min Max 0 1 5 1 2 4 2 3 3 3 8 2 8 40 1 40 65 0 The clock recovery oversampling rate is set via rxosr[10:0] in "Register 20h. Clock Recovery Oversampling Rate" and "Register 21h. Clock Recovery Offset 2". ndec_exp and dwn3_bypass together with the receive data rate (Rb) are used to calculate rxosr: 500×(1+2×dwn3_bypass) 2ndec_exp-3 ×Rb×（1+enmanch） rxosr = Where: Rb is in kbps and enmanch is the Manchester Coding parameter. The resulting rxdr[10:0] value should be rounded to an integer hexadecimal number. The clock recovery offset ncoff[19:0] in "Register 21h. Clock Recovery Offset 2", "Register 22h. Clock Recovery Offset 1", and "Register 23h. Clock Recovery Offset 0" is calculated as follows: ncoff = Rb×（1+enmanch）×220+ndec_exp 500×(1+2×dwn3_bypass) Where: Rb is in kbps. The clock recovery gain crgain[10:0] in "Register 24h. Clock Recovery Timing Loop Gain 1" and "Register 25h. Clock Recovery Timing Loop Gain 0" is calculated as follows: 216 crgain = 2+ rxosr 39 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 19. RX Modem Configuration for OOK with Manchester Disabled RX Modem Setting Examples for OOK (Manchester Disabled) Appl Parameters Register Values Rb Fd dwn3_bypass ndec_exp[2:0] filset[3:0] rxosr[10:0] ncoff[19:0] crgain[10:0] [kbps] [kHz] 1Ch 1Ch 1Ch 20,21h 21,22,23h 24,25h 1.2 75 0 4 1 0D0 09D49 13D 1.2 110 0 4 5 0D0 09D49 13D 1.2 335 1 4 8 271 0346E 06B 1.2 420 1 4 A 271 0346E 06B 1.2 620 1 4 E 271 0346E 06B 2.4 335 1 3 8 271 0346E 06B 4.8 335 1 2 8 271 0346E 06B 9.6 335 1 1 8 271 0346E 06B 10 335 1 1 8 258 0369D 06F 15 335 1 1 8 190 051EC 0A6 19.2 335 1 1 8 139 068DC 0D3 20 335 1 1 8 12C 06D3A 0DC 30 335 1 1 8 0C8 0A3D7 14A 38.4 335 1 1 8 09C 0D1B7 1A6 40 335 1 1 8 096 0DA74 1B7 Table 20. RX Modem Configuration for OOK with Manchester Enabled RX Modem Setting Examples for OOK (Manchester Disabled) Appl Parameters Register Values Rb Fd dwn3_bypass ndec_exp[2:0] filset[3:0] rxosr[10:0] ncoff[19:0] crgain[10:0] [kbps] [kHz] 1Ch 1Ch 1Ch 20,21h 21,22,23h 24,25h 1.2 75 0 3 1 0D0 04EA5 13D 1.2 110 0 3 5 0D0 04EA5 13D 1.2 335 1 3 8 271 01A37 06B 1.2 420 1 3 A 271 01A37 06B 1.2 620 1 3 E 271 01A37 06B 2.4 335 1 2 8 271 01A37 06B 4.8 335 1 1 8 271 01A37 06B 9.6 335 1 1 8 139 0346E 0D3 10 335 1 1 8 12C 0369D 0DC 15 335 1 1 8 0C8 051EC 14A 19.2 335 1 1 8 09C 068DC 1A6 20 335 1 1 8 096 06D3A 1B7 30 335 1 0 8 0C8 051EC 14A 38.4 335 1 0 8 09C 068DC 1A6 40 335 1 0 8 096 06D3A 1B7 40 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8. Auxiliary Functions 8.1. Smart Reset The RFM31 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable reset signal in any circumstances. Reset will be initiated if any of the following conditions occur: Initial power on, when VDD starts from 0V: reset is active till VDD reaches VRR (see table); When A VDD decreases below VLD for any reason: reset is active till VDD reaches VRR again; software reset via ―Register 08h. Operating Mode and Function Control 2,‖: reset is active for time.TSWRST On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit: Figure 17. POR Glitch Parameters Table 21. POR Parameters Parameter Symbol Comment Min Typ Max Units Release Reset Voltage VRR 0.85 1.3 1.75 V Power-On VDD Slope SVDD tested VDD slope region 0.03 300 V/ms 0.03 Low VDD Limit VLD VLD<VRR is guaranteed 0.7 1 1.3 V Software Reset Pulse TSWRST 470 us Threshold Voltage VTSD 0.4 V Reference Slope k 0.2 V/ms VDD Glitch Reset Pulse TP 50 Also occurs after SDN, and initial power on 5 15 40 ms The reset will initialize all registers to their default values. The reset signal is also available for output and use by the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on GPIO_1. 41 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.2. Microcontroller Clock The crystal oscillator frequency is divided down internally and may be output to the microcontroller through GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock frequency is selectable from one of 8 options, as shown below. Except for the 32.768 kHz option, all other frequencies are derived by dividing the Crystal Oscillator frequency. The 32.768 kHz clock signal is derived from an internal RC Oscillator or an external 32 kHz Crystal, depending on which is selected. The GPIO2 default is the microcontroller clock with a 1 MHz microcontroller clock output. Add R/W 0A R/W Function/Descr iption D7 D6 Microcontroller Output Clock D5 D4 D3 D2 D1 D0 clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] mclk[2:0] Modulation Source 000 30 MHz 001 15 MHz 010 10 MHz 011 4 MHz 100 3 MHz 101 2 MHz 110 1 MHz 111 32.768 KHz POR Def. 0Bh If the microcontroller clock option is being used there may be the need of a System Clock for the microcontroller while the RFM31 is in SLEEP mode. Since the Crystal Oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called Enable Low Frequency Clock and is enabled by the enlfc bit. When enlfc = 1 and the module is in SLEEP mode then the 32.768 kHz clock will be provided to the microcontroller as the System Clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the microcontroller as the System Clock in all IDLE or RX states. When the module is commanded to SLEEP mode, the System Clock will become 32.768 kHz. Another available feature for the microcontroller clock is the Clock Tail, clkt[1:0]. If the Enable Low Frequency Clock feature is not enabled (enlfc = 0), then the System Clock to the microcontroller is disabled in SLEEP mode. However, it may be useful to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdown of the System Clock signal. Setting the clkt[1:0] field will provide additional cycles of the System Clock before it shuts off. clkt[1:0] Modulation Source 00 0 cycles 01 128 cycles 10 256 cycles 11 512 cycles If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon as the interrupt is read the state machine will then move to the selected mode. For instance, if the module is commanded to Sleep mode but an interrupt has occurred the 30 MHz XTAL will not disable until the interrupt has been cleared. 42 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.3. General Purpose ADC An 8-bit SAR ADC is integrated onto the module for general purpose use, as well as for digitizing the temperature sensor reading. ―Register 0Fh. ADC Configuration,‖ must be configured depending on the use of the GP ADC before use. The architecture of the ADC is demonstrated in Figure 18. First the input of the ADC must be selected by setting the ADCSEL[2:0] depending on the use of the ADC. For instance, if the ADC is going to be used to read out the internal temperature sensor, then ADCSEL[2:0] should be set to 000. Next, the input reference voltage to the ADC must be chosen. By default, the ADC uses the bandgap voltage as a reference so the input range of the ADC is from 0–1.02 V with an LSB resolution of 4 mV (1.02/255). Changing the ADC reference will change the LSB resolution accordingly. Every time the ADC conversion is desired, the ADCStart bit in ―Register 0Fh. ADC Configuration,‖ must be set to 1. This is a self clearing bit that will be cleared at the end of the conversion cycle of the ADC. The conversion time for the ADC is 350 us. After the 350 us or when the ADCstart/busy bit is cleared, then the ADC value may be read out of "Register 11h. ADC Value". Setting the "Register 10h. ADC Sensor Amplifier Offset", ADC Sensor Amplifier Offset is only necessary when the ADC is configured to used as a Bridge Sensor as described in the following section. Figure 18. General Purpose ADC Architecture Add R/W 0F R/W 10 R/W 11 R Function/D D7 D6 D5 D4 ADC adcstart/ad adcsel adcsel adcsel Configuration cbusy [2] [1] [0] POR D3 D2 D1 D0 adcref[1] adcref[0] adcgain[1] adcgain[0] 00h ADC Sensor adcoffs[3 adcoffs[ adcoffs[1] adcoffs[0] 00h Amplifier Offset ] 2] adc[3] adc[2] adc[1] adc[0] — escription ADC Value adc[7] adc[6] adc[5] adc[4] Def. 43 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.3.1. ADC Differential Input Mode—Bridge Sensor Example The differential input mode of ADC8 is designed to directly interface any bridge-type sensor, which is demonstrated in the figure below. As seen in the figure the use of the ADC in this configuration will utilize two GPIO pins. The supply source of the bridge and module should be the same to eliminate the measuring error caused by battery discharging. For proper operation one of the VDD dependent references (VDD/2 or VDD/3) should be selected for the reference voltage of ADC8. VDD/2 reference should be selected for VDD lower than 2.7 V, VDD/3 reference should be selected for VDD higher than 2.7 V. The differential input mode supports programmable gain to match the input range of ADC8 to the characteristic of the sensor and VDD proportional programmable offset adjustment to compensate the offset of the sensor. Figure 19. ADC Differential Input Example—Bridge Sensor The adcgain[1:0] bits in "Register 0Eh. I/O Port Configuration" determine the gain of the differential/single ended amplifier. This is used to fit the input range of the ADC8 to bridge sensors having different sensitivity: adcgain[1] adcgain[0] 0 Differential Gain Input Range (% of VDD) adcref[0] = 0 adcref[0] = 1 0 22/13 33/13 16.7 0 1 44/13 66/13 8.4 1 0 66/13 99/13 5.6 1 1 88/13 132/13 4.2 Note: The input range is the differential voltage measured between the selected GPIO pins corresponding to the full ADC range (255). The gain is different for different VDD dependent references so the reference change has no influence on input range and digital measured values. 44 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 The differential offset can be coarse compensated by the adcoffs[3:0] bits found in "Register 11h. ADC Value". Fine compensation should be done by the microcontroller software. The main reason for the offset compensation is to shift the negative offset voltage of the bridge sensor to the positive differential voltage range. This is essential as the differential input mode is unipolar. The offset compensation is VDD proportional, so the VDD change has no influence on the measured value. Figure 20. ADC Differential Input Offset for Sensor Offset Coarse Compensation 45 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.4. Temperature Sensor An analog temperature sensor is integrated into the module. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus. The temperature sensor value may be digitized using the general-purpose ADC and read out over the SPI through "Register 10h. ADC Sensor Amplifier Offset". The range of the temperature sensor is selectable to configure to the desired application and performance. The table below demonstrates the settings for the different temperature ranges and performance. To use the Temp Sensor: 1. Set input for ADC to be Temperature Sensor, "Register 0Fh. ADC Configuration"—adcsel[2:0] = 000 2. Set Reference for ADC, "Register 0Fh. ADC Configuration"—adcref[1:0] = 00 3. Set Temperature Range for ADC, "Register 12h. Temperature Sensor Calibration"—tsrange[1:0] 4. Set entsoffs = 1, "Register 12h. Temperature Sensor Calibration" 5. Trigger ADC Reading, "Register 0Fh. ADC Configuration"—adcstart = 1 6. Read-out Value—Read Address in "Register 11h. ADC Value" Add R/W 12 R/W 13 R/W Function/Descr iption POR D7 D6 D5 D4 D3 D2 D1 D0 tsrange[1] tsrange[0] entsoffs entstrim vbgtrim[3] vbgtrim[2] vbgtrim[1] vbgtrim[0] 20h tvoffs[7] tvoffs[6] tvoffs[5] tvoffs[4] tvoffs[3] tvoffs[2] tvoffs[1] tvoffs[0] 00h Temperature Def. Sensor Control Temperature Value Offset Table 22. Temperature Sensor Range entoff tsrange[1] tsrange[0] Temp. range Unit Slope ADC8 LSB 1 0 0 –64 … 64 °C 8 mV/°C 0.5 °C 1 0 1 –64 … 192 °C 4 mV/°C 1 °C 1 1 0 0 … 128 °C 8 mV/°C 0.5 °C 1 1 1 –40 … 216 °F 4 mV/°F 1 °F 0* 1 0 0 … 341 °K 3 mV/°K 1.333 °K *Note: Absolute temperature mode, no temperature shift. This mode is only for test purposes. POR value of EN_TOFF is 1. Control to adjust the temperature sensor accuracy is available by adjusting the bandgap voltage. By enabling the envbgcal and using the vbgcal[3:0] bits to trim the bandgap the temperature sensor accuracy may be fine tuned in the final application. The slope of the temperature sensor is very linear and monotonic but the exact accuracy or offset in temperature is difficult to control better than ±10 °C. With the vbgtrim or bandgap trim though the initial temperature offset can be easily adjusted and be better than ±3 °C. The different ranges for the temperature sensor and ADC8 are demonstrated in Figure 21. The value of the ADC8 may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64. 46 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Figure 21. Temperature Ranges using ADC8 47 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the module. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller will then need to verify the interrupt by reading "Register 03h. Interrupt/Status 1" and ―Register 04h. Interrupt/Status 2,‖If the LBD is enabled while the module is in SLEEP mode, it will automatically enable the RC oscillator which will periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be read out through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The Low Battery Detect function is enabled by setting enlbd=1 in "Register 07h. Operating Mode and Function Control 1". Ad R/W 1A R/W 1B R Function/Descri ption D7 D6 D5 Low Battery Detector Threshold Battery Voltage Level 0 0 0 POR D4 D3 D2 D1 D0 lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] — Def. The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled, enlbd = 1 in "Register 07h. Operating Mode and Function Control 1", the battery voltage may be read at anytime by reading "Register 1Bh. Battery Voltage Level". A Battery Voltage Threshold may be programmed to register 1Ah. When the battery voltage level drops below the battery voltage threshold an interrupt will be generated on nIRQ pin to the microcontroller if the LBD interrupt is enabled in ―Register 06h. Interrupt Enable 2,‖. The microcontroller will then need to verify the interrupt by reading the interrupt status register, Addresses 03 and 04H. The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled every 1 s for approximately 250 μs to measure the voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated four consecutive readings are required. BatteryVoltage =1.7+50mV × ADCValue ADC Value VDD Voltage [V] 0 < 1.7 1 1.7–1.75 2 1.75–1.8 …… …… 29 3.1–3.15 30 3.15–3.2 31 >3.2 48 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.6. Wake-Up Timer The module contains an integrated wake-up timer which periodically wakes the module from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified by the Wake-Up Timer Period in Registers 10h–12h. At the expiration of this period an interrupt will be generated on the nIRQ pin if this interrupt is enabled. The microcontroller will then need to verify the interrupt by reading the Interrupt Status Registers 03h–04h. The wake-up timer value may be read at any time by the wtv[15:0] read only registers 13h–14h. The formula for calculating the Wake-Up Period is the following: WUT = 32 X M X 2R ms 32.768 WUT Register Description wtr[3:0] R Value in Formula wtd[1:0] D Value in Formula wtm[15:0] M Value in Formula Use of the D variable in the formula is only necessary if finer resolution is required than the R value gives. Ad 14 15 16 R/W R/W Function/Descri ption D7 D6 D4 D3 D2 D1 D0 wtr[3] wtr[2] wtr[1] wtr[0] wtd[1] wtd[0] 00h wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] — wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] — Wake-Up Timer Period 1 R/W R/W 17 R 18 R Wake-Up Timer wtm Period 2 [15] Wake-Up Timer wtm Period 3 [7] Wake-Up Timer wtv[ Value 1 15] Wake-Up Timer wtv[ Value 2 7] POR D5 Def. There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in ―Register 06h. Interrupt Enable 2,‖. If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The module will also change state so that the 30 M XTAL is enabled so that the microcontroller clock output is available for the microcontroller to use process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the module will not change state until commanded by the microcontroller. The two different modes of operation of the WUT are demonstrated in Figure 22. A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in 07h, GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be connected to this pin and the XTAL should be physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, micro-controller clock, and LDC mode will use the 32 K XTAL and not the 32 kHz RC oscillator. 49 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Interrupt Enable enwut=1 (Reg 06h) Interrupt Enable enwut=0 (Reg 06h) Figure 22. WUT Interrupt and WUT Operation 50 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.7. Low Duty Cycle Mode The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync word is not detected the module will return to sleep mode until the beginning of a new WUT period. If a valid preamble and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to receive all of the packet. The time of the TLDC is determined by the formula below: 2×(R-D)×32 TLDC = ldc[7 : 0]× ms 32.768 Figure 23. Low Duty Cycle Mode 51 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.8. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, Antenna Diversity Switch control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. Note: The ADC should not be selected as an input to the GPIO in Standby or Sleep Modes and will cause excess current consumption. Add R/W 0B R/W 0C R/W 0D R/W 0E R/W Function/D D7 D6 GPIO0 gpio0 gpio0dr Configuration drv[1] v[0] GPIO1 Gpio1 gpio1dr Configuration drv[1] v[0] GPIO2 Gpio2 gpio2dr Configuration drv[1] v[0] escription I/O Port extitst[2] Configuration POR D5 D4 D3 D2 D1 D0 pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h Pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h Pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h extitst[0] itsdo dio2 dio1 dio0 00h extitst[ 1] Def. The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default setting. The default settings for each GPIO are listed below: GPIO 00000—Default Setting GPIO0 POR GPIO1 POR Inverted GPIO2 Microcontroller Clock This application uses antenna diversity so a GPIO is used to control the antenna switch The module is configured to provide the System Clock output to the microcontroller so that only one crystal is needed in the system, therefore reducing the BOM cost. Direct mode instead of the FIFO and programming the RX data and RX Bit clock onto the GPIO. For a complete list of the available GPIO's see ―Register 0Ch. GPIO Configuration 1,‖ , ―Register 0Dh. GPIO Configuration 2,‖, and ―Register 0Eh. I/O Port Configuration,‖. 52 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.9. Antenna-Diversity For RF31 IC To mitigate the problem of frequency-selective fading due to multi-path propagation, some radio systems use a scheme known as Antenna Diversity. In this scheme, two antennas are used. Each time the radio enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet. The antenna with the strongest received signal is then used for the remainder of that RX packet. This module fully supports Antenna Diversity with an integrated Antenna Diversity Control Algorithm. By setting GPIOx[4:0] = 10111 and 11000, the required signal needed to control an external SPDT RF switch (such as PIN diode or GaAs switch) is made available on the GPIOx pins. The operation of these switches is programmable to allow for different Antenna Diversity architectures and configurations. The antdiv[2:0] register is found in register 08h. The GPIO pin is capable of sourcing up to 5 mA of current, so it may be used directly to forward-bias a PIN diode if desired. When the arrival of the packet is unknown by the receiver the antenna diversity algorithm (antdiv[2:0] = 100 or 101) will detect both packet arrival and selects the antenna with the strongest signal. The recommended preamble length to obtain good antenna selection is 8 bytes. A special antenna diversity algorithm (antdiv[2:0] = 110 or 111) is included that allows for shorter preamble for TDMA like systems where the arrival of the packet is synchronized to the receiver enable. The recommended preamble length to obtain good antenna selection for synchronized mode is 4 bytes. Add 08 R/W Function/Des D7 D6 D5 D4 antdiv[2] antdiv[1] antdiv[0] rxmpk cription Operating & R/W Function Control 2 D3 Reserv ed D2 D1 enldm ffclrrx POR D0 Def. Reserv ed 00h Table 23. Antenna Diversity Control antdiv[2:0] RX State Non RX State GPIO Ant1 GPIO Ant2 GPIO Ant1 GPIO Ant2 000 0 1 0 0 001 1 0 0 0 010 0 1 1 1 011 1 0 1 1 100 Antenna Diversity Algorithm 0 0 101 Antenna Diversity Algorithm 1 1 110 Antenna Diversity Algorithm in Beacon Mode 0 0 111 Antenna Diversity Algorithm in Beacon Mode 1 1 53 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 8.10. RSSI and Clear Channel Assessment The RSSI (Received Signal Strength Indicator) signal is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit. Figure 24 demonstrates the relationship between input power level and RSSI value. The RSSI may be read at anytime, but an incorrect error may rarely occur. The RSSI value may be incorrect if read during the update period. The update period is approximately 10 ns every 4 Tb. For 10 kbps, this would result in a 1 in 40,000 probability that the RSSI may be read incorrectly. This probability is extremely low, but to avoid this, one of the following options is recommended: majority polling, reading the RSSI value within 1 Tb of the RSSI interrupt, or using the RSSI threshold described in the next paragraph for Clear Channel Assessment. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 26 R Received Signal Strength Indicator rssi[7] rssi[6] rssi[5] rssi[4] rssi[3] rssi[2] rssi[1] rssi[0] RSSI Threshold for Clear Channel rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] rssith[2] rssith[1] rssith[0] 27 R/W POR Def. — 00h Indicator For Clear Channel Assessment a threshold is programmed into rssith[7:0] in "Register 27h. RSSI Threshold for Clear Channel Indicator". After the RSSI is evaluated in the preamble, a decision is made if the signal strength on this channel is above or below the threshold. If the signal strength is above the programmed threshold then a 1 will be shown in the RSSI status bit in "Register 02h. Device Status", "Register 04h. Interrupt/Status 2", or configurable GPIO (GPIOx[3:0] = 1110). Figure 24. RSSI Value vs. Input Power 54 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 9. Reference Design Figure 33. RFM31 Reference Design Schematic 55 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 10. Measurement Results Note: Sensitivity is BER measured, GFSK modulation, BT = 0.5, H = 1. Figure 29. Sensitivity vs. Data Rate 56 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Figure 30. Receiver Selectivity 57 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 RF31 Figure 31. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz Figure 32. Synthesizer Phase Noise (VCOCURR = 11) 58 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 11. Reference Material 11.1. Complete Register Table and Descriptions Table 27. Register Descriptions 59 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 27. Register Descriptions (Continued) 60 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 00h. Device Type Code (DT) Bit D7 D6 Name D5 D4 D3 Reserved Type D2 D1 D0 D1 D0 dt[4:0] R R Reset value = 00001000 Bit Name 7:5 Reserved 4:0 dt[4:0] Function Reserved. Device Type Code. Register 01h. Version Code (VC) Bit D7 D6 Name D5 D4 D3 vc[4:0] Reserved Type D2 R R Reset value = xxxxxxxx Bit Name 7:5 Reserved Function Reserved. Version Code. 4:0 vc[4:0] Code indicating the version of the module. Rev A0: 00100 61 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 02h. Device Status Bit D7 D6 D5 D4 D3 D2 Name ffovfl ffunfl rxffem headerr Reserved Reserved Type R R R R R R D1 D0 cps[1:0] R R Reset value = xxxxxxxx Bit Name Function 7 ffovfl RX FIFO Overflow Status. 6 ffunfl RX FIFO Underflow Status. 5 rxffem RX FIFO Empty Status. 4 Reserved headerr Header Error Status. Indicates if the received packet has a header check error. 3:2 Reserved Reserved. 1:0 cps[1:0] Module Power State. 00: Idle State 01: TX State 62 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 03h. Interrupt/Status 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ifferr Reserved Reserved irxffafull iext Reserved ipkvalid icrerror Type R R R R R R R R Reset value = xxxxxxxx Bit Name 7 ifferr 6:5 Reserved 4 irxffafull Function FIFO Underflow/Overflow Error. When set to 1 the TX FIFO has overflowed or underflowed. Reserved. RX FIFO Almost Full.When set to 1 the RX FIFO has met its almost full threshold and needs to be read by the microcontroller. External Interrupt. 3 iext When set to 1 an interrupt occurred on one of the GPIO‘s if it is programmed so. The status can be checked in register 0Eh. See GPIOx Configuration section for the details. 2 Reserved 1 ipkvalid 0 icrerror Reserved. Valid Packet Received. When set to 1 a valid packet has been received. CRC Error. When set to 1 the cyclic redundancy check is failed. When any of the Interrupt/Status 1 bits change state from 0 to 1 the device will notify the microcontroller by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 1 register. The nIRQ pin will go to HIGH and all the enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled in the Interrupt Enable 1 register then it becomes a status signal that can be read anytime in the same location and will not be cleared by reading the register. 63 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 28. Interrupt or Status 1 Bit Set/Clear Description Bit Status Set/Clear Conditions Name 7 ifferr 6:5 Reserved 4 irxffafull 3 iext 2 Reserved 1 ipkvalid 0 icrcerror Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset. Reserved. Set when the number of bytes in the RX FIFO is greater than the Almost Full threshold. Cleared when the number of bytes in the RX FIFO is below the Almost Full threshold. External interrupt source. Reserved. Set up the successful reception of a packet (no RX abort). Cleared upon receiving and acknowledging the Sync Word for the next packet. Set if the CRC computed from the RX packet differs from the CRC in the TX packet. Cleared at the start of reception for the next packet. Table 29. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts? Bit Status Set/Clear Conditions Name 7 ifferr 6:5 Reserved Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO reset to the specific FIFO that caused the condition. Reserved. Will be set when the number of bytes received (and not yet read-out) in RX 4 irxffafull FIFO is greater than the Almost Full threshold set by SPI. It is automatically cleared when we read enough data from RX FIFO so that the number of data bytes not yet read is below the Almost Full threshold. 3 iext 2 Reserved 1 ipkvalid External interrupt source Reserved. Goes high once a packet is fully received (no RX abort). It is automatically cleaned once we receive and acknowledge the Sync Word for the next packet. Goes High once the CRC computed during RX differs from the CRC sent in the 0 icrcerror packet by the TX. It is cleaned once we start receiving new data in the next packet. 64 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 04h. Interrupt/Status 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor Type R R R R R R R R Reset value = xxxxxxxx Bit Name 7 iswdet 6 ipreaval Function Sync Word Detected. When a sync word is detected this bit will be set to 1. Valid Preamble Detected. When a preamble is detected this bit will be set to 1. Invalid Preamble Detected. 5 ipreainval When the preamble is not found within a period of time set by the invalid preamble detection threshold in Register 54h, this bit will be set to 1. 4 irssi 3 iwut RSSI. When RSSI level exceeds the programmed threshold this bit will be set to 1. Wake-Up-Timer. On the expiration of programmed wake-up timer this bit will be set to 1. Low Battery Detect. 2 ilbd When a low battery event is been detected this bit will be set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled. 1 ichiprdy Module Ready (XTAL). When a module ready event has been detected this bit will be set to 1. Power-on-Reset (POR). 0 ipor When the module detects a Power on Reset above the desired setting this bit will be set to 1. When any of the Interrupt/Status Register 2 bits change state from 0 to 1 the control block will notify the microcontroller by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 2 register. The nIRQ pin will go to HIGH and all the enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled in the Interrupt Enable 2 register then it becomes a status signal that can be read anytime in the same location and will not be cleared by reading the register. 65 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 30. Interrupt or Status 2 Bit Set/Clear Description Bit Name 7 iswdet 6 ipreaval 5 ipreainval 4 irssi 3 iwut Set/Clear Conditions Goes high once the Sync Word is detected. Goes low once we are done receiving the current packet. Goes high once the preamble is detected. Goes low once the sync is detected or the RX wait for the sync times-out. Self cleaning, user should use this as an interrupt source rather than a status. Should remain high as long as the RSSI value is above programmed threshold level Wake time timer interrupt. Use as an interrupt, not as a status. Low Battery Detect. When a low battery event is been detected this bit will be 2 ilbd set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled. Probably the status is cleared once the battery is replaced. 1 ichiprdy 0 ipor Module ready goes high once we enable the xtal, RX and a settling time for the Xtal clock elapses. The status stay high unless we go back to Idle mode. Power on status. Table 31. Detailed Description of Status Registers when not Enabled as Interrupts Bit Name 7 iswdet 6 ipreaval 5 ipreainval 4 irssi 3 iwut Set/Clear Conditions Goes high once the Sync Word is detected. Goes low once we are done receiving the current packet. Goes high once the preamble is detected. Goes low once the sync is detected or the RX wait for the sync times-out. Self cleaning, user should use this as an interrupt source rather than a status. Should remain high as long as the RSSI value is above programmed threshold level Wake time timer interrupt. Use as an interrupt, not as a status. Low Battery Detect. When a low battery event is been detected this bit will be 2 ilbd set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled. Probably the status is cleared once the battery is replaced. 1 ichiprdy 0 ipor Module ready goes high once we enable the xtal, RX, and a settling time for the Xtal clock elapses. The status stay high unless we go back to Idle mode. Power on status. 66 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 05h. Interrupt Enable 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name enfferr Reserved Reserved entxffafull enext Reserved enpkvalid encrcerror Type R/w R/w R/w R/w R/w R/w R/w R/w Reset value = 00000000 Bit Name 7 enfferr 6:5 Reserved 4 entxffafull 3 enext 2 Reserved 1 enpkvalid 0 encrcerror Function Enable FIFO Underflow/Overflow. When set to 1 the FIFO Underflow/Overflow interrupt will be enabled. Reserved. Enable RX FIFO Almost Full. When set to 1 the RX FIFO Almost Full interrupt will be enabled. Enable External Interrupt. When set to 1 the External Interrupt will be enabled. Reserved. Enable Valid Packet Received. When ipkvalid = 1 the Valid Packet Received Interrupt will be enabled. Enable CRC Error. When set to 1 the CRC Error interrupt will be enabled. 67 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 06h. Interrupt Enable 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor Type R R R R/ w R R/w R/w R/w Reset value = 00000011 Bit Name 7 enswdet 6 enpreaval 5 enpreainval 4 enrssi 3 enwut 2 enlbd 1 enchiprdy 0 enpor Function Enable Sync Word Detected. When mpreadet =1 the Preamble Detected Interrupt will be enabled. Enable Valid Preamble Detected. When mpreadet =1 the Valid Preamble Detected Interrupt will be enabled. Enable Invalid Preamble Detected. When mpreadet =1 the Invalid Preamble Detected Interrupt will be enabled. Enable RSSI. When set to 1 the RSSI Interrupt will be enabled. Enable Wake-Up Timer. When set to 1 the Wake-Up Timer interrupt will be enabled. Enable Low Battery Detect. When set to 1 the Low Battery Detect interrupt will be enabled. Enable Module Ready (XTAL). When set to 1 the Module Ready interrupt will be enabled. Enable POR. When set to 1 the POR interrupt will be enabled. 68 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 07h. Operating Mode and Function Control 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name swres enlbd enwt x32ksel Reserved rxon pllon xton Type R/w R/w R/w R/w R/w R/w R/w R/w Reset value = 00000001 Bit Name Function Software Register Reset Bit. 7 swres This bit may be used to reset all registers simultaneously to a DEFAULT state, without the need for sequentially writing to each individual register. The RESET is accomplished by setting swres = 1. This bit will be automatically cleared. Enable Low Battery Detect. 6 enlbd When this bit is set to 1 the Low Battery Detector circuit and threshold comparison will be enabled. Enable Wake-Up-Timer. 5 enwt Enabled when enwt = 1. If the Wake-up-Timer function is enabled it will operate in any mode and notify the microcontroller through the GPIO interrupt when the timer expires. 32,768 kHz Crystal Oscillator Select. 4 x32ksel 0: RC oscillator 1: 32 kHz crystal 3 Reserved 2 rxon Reserved. RX on in Manual Receiver Mode. Automatically cleared if Multiple Packets config. is disabled and a valid packet received. TUNE Mode (PLL is ON). 1 pllon When pllon = 1 the PLL will remain enabled in Idle State. This will for faster turn-around time at the cost of increased current consumption in Idle State. 0 xton READY Mode (Xtal is ON). 69 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 08h. Operating Mode and Function Control 2 Bit D7 D4 D3 D2 D1 D0 Name antdiv[2:0] D6 D5 rxmpk Reserved enldm ffclrrx Reserved Type R/w R/w R/w R/w R/w R/w Reset value = 00000001 Bit Name Function Enable Antenna Diversity. The GPIO must be configured for Antenna Diversity for the algorithm to work properly. 7:5 antdiv[2:0] RX state non RX state GPIO Ant1 GPIO Ant2 GPIO Ant1 GPIO Ant2 000: 0 1 0 0 001: 1 0 0 0 010: 0 1 1 1 011: 1 0 1 1 100: antenna diversity algorithm 0 0 101: antenna diversity algorithm 1 1 110: ant. div. algorithm in beacon mode 0 0 111: ant. div. algorithm in beacon mode 1 1 RX Multi Packet. When the module is selected to use FIFO Mode (dtmod[1:0]) and RX Packet 4 rxmpk Handling (enpacrx) then it will fill up the FIFO with multiple valid packets if this bit is set, otherwise the receiver will automatically leave the RX State after the first valid packet has been received. 3 Reserved Reserved. Enable Low Duty Cycle Mode. If this bit is set to 1 then the module turns on the RX regularly. The frequency 2 enldm should be set in the Wake-Up Timer Period register, while the minimum ON time should be set in the Low-Duty Cycle Mode Duration register. The FIFO mode should be enabled also. RX FIFO Reset/Clear. 1 ffclrrx This has to be a two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0 will clear the contents of the RX FIFO. 0 Reserved Reserved. 70 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 09h. 30 MHz Crystal Oscillator Load Capacitance Bit D7 Name xtalshft Type R/w D6 D5 D4 D3 D2 D1 D0 xlc[6:0] R/w Reset value = 01111111 Bit Name 7 xtalshft 6:0 xlc[6:0] Function Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. Not binary with xlc[6:0]. Tuning Capacitance for the 30 MHz XTAL. 71 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 0Ah. Microcontroller Output Clock Bit Name Type D7 D6 D5 Reserved D4 D3 clkt[1:0] R/w R D2 D1 enlfc mclk[2:0] R/w R/w D0 Reset value = xx000110 Bit Name 7:6 Reserved Function Reserved. Clock Tail. If enlfc = 0 then it can be useful to provide a few extra cycles for the microcontroller to complete its operation. Setting the clkt[1:0] register will 5:4 clkt[1:0] provide the addition cycles of the clock before it shuts off. 00: 0 cycle 01: 128 cycles 10: 256 cycles 11: 512 cycles Enable Low Frequency Clock. When enlfc = 1 and the module is in Sleep mode then the 32.768 kHz clock will 3 enlfc be provided to the microcontroller no matter what the selection of mclk[2:0] is. For example if mclk[2:0] = ‗000‘, 30 MHz will be available through the GPIO to output to the microcontroller in all Idle or TX states. When the module is commanded to Sleep mode the 30 MHz clock will become 32.768 kHz. Microcontroller Clock. Different clock frequencies may be selected for configurable GPIO clock output. All clock frequencies are created by dividing the XTAL except for the 32 kHz clock which comes directly from the 32 kHz RC Oscillator. The mclk[2:0] setting is only valid when xton = 1 except the 111. 2:0 mclk[2:0] 000: 30 MHz 001: 15 MHz 010: 10 MHz 011: 4 MHz 100: 3 MHz 101: 2 MHz 110: 1 MHz 111: 32.768 kHz 72 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 0Bh. GPIO Configuration 0 Bit D7 Name Type D6 D5 gpiodrv0[1:0] R/w D4 D3 D2 D1 pup0 gpio0[4:0] R/w R/w D0 Reset value = 00000000 Bit Name 7:6 gpiodrv0[1:0] Function GPIO Driving Capability Setting. Pullup Resistor Enable on GPIO0. 5 pup0 When set to 1 the a 200 KΩ resistor is connected internally between VDD and the pin if the GPIO is configured as a digital input. GPIO0 pin Function Select. 00000: Power-On-Reset (output) 00001: Wake-Up Timer: 1 when WUT has expired (output) 4:0 gpio0[4:0] 00010: Low Battery Detect: 1 when battery is below threshold setting (output) 00011: Direct Digital Input 00100: External Interrupt, falling edge (input) 00101: External Interrupt, rising edge (input) 00110: External Interrupt, state change (input) 00111: ADC Analog Input 01000: Reserved (Analog Test N Input) 01001: Reserved (Analog Test P Input) 01010: Direct Digital Output 01011: Reserved (Digital Test Output) 01100: Reserved (Analog Test N Output) 01101: Reserved (Analog Test P Output) 01110: Reference Voltage (output) 01111: RX Data CLK output to be used in conjunction with RX Data pin (output) 10000: Reserved 10001: External Retransmission Request (input) 10010: Reserved 10011: Reserved 10100: RX Data (output) 10101: RX State (output) 10110: RX FIFO Almost Full (output) 10111: Antenna 1 Switch used for antenna diversity (output) 11000: Antenna 2 Switch used for antenna diversity (output) 11001: Valid Preamble Detected (output) 11010: Invalid Preamble Detected (output) 11011: Sync Word Detected (output) 11100: Clear Channel Assessment (output) 11101: VDD else : GND 73 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 0Ch. GPIO Configuration 1 Bit D7 Name Type D6 D5 gpiodrv1[1:0] R/w D4 D3 D2 D1 pup1 Gpio1[4:0] R/w R/w D0 Reset value = 00000000 Bit Name 7:6 gpiodrv1[1:0] Function GPIO Driving Capability Setting. Pullup Resistor Enable on GPIO1. 5 Pup1 When set to 1 the a 200 KΩ resistor is connected internally between VDD and the pin if the GPIO is configured as a digital input. GPIO1 pin Function Select. 00000: Inverted Power-On-Reset (output) 00001: Wake-Up Timer: 1 when WUT has expired (output) 4:0 gpio1[4:0] 00010: Low Battery Detect: 1 when battery is below threshold setting (output) 00011: Direct Digital Input 00100: External Interrupt, falling edge (input) 00101: External Interrupt, rising edge (input) 00110: External Interrupt, state change (input) 00111: ADC Analog Input 01000: Reserved (Analog Test N Input) 01001: Reserved (Analog Test P Input) 01010: Direct Digital Output 01011: Reserved (Digital Test Output) 01100: Reserved (Analog Test N Output) 01101: Reserved (Analog Test P Output) 01110: Reference Voltage (output) 01111: RX Data CLK output to be used in conjunction with RX Data pin (output) 10000: Reserved 10001: External Retransmission Request (input) 10010: Reserved 10011: Reserved 10100: RX Data (output) 10101: RX State (output) 10110: RX FIFO Almost Full (output) 10111: Antenna 1 Switch used for antenna diversity (output) 11000: Antenna 2 Switch used for antenna diversity (output) 11001: Valid Preamble Detected (output) 11010: Invalid Preamble Detected (output) 11011: Sync Word Detected (output) 11100: Clear Channel Assessment (output) 11101: VDD else : GND 74 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 0Dh. GPIO Configuration 2 Bit D7 Name Type D6 D5 gpiodrv2[1:0] R/w D4 D3 D2 D1 pup2 Gpio2[4:0] R/w R/w D0 Reset value = 00000000 Bit Name 7:6 gpiodrv2[1:0] Function GPIO Driving Capability Setting. Pullup Resistor Enable on GPIO2. 5 Pup2 When set to 1 the a 200 KΩ resistor is connected internally between VDD and the pin if the GPIO is configured as a digital input. GPIO2 pin Function Select. 00000: Microcontroller Clock 00001: Wake-Up Timer: 1 when WUT has expired (output) 4:0 gpio2[4:0] 00010: Low Battery Detect: 1 when battery is below threshold setting (output) 00011: Direct Digital Input 00100: External Interrupt, falling edge (input) 00101: External Interrupt, rising edge (input) 00110: External Interrupt, state change (input) 00111: ADC Analog Input 01000: Reserved (Analog Test N Input) 01001: Reserved (Analog Test P Input) 01010: Direct Digital Output 01011: Reserved (Digital Test Output) 01100: Reserved (Analog Test N Output) 01101: Reserved (Analog Test P Output) 01110: Reference Voltage (output) 01111: RX Data CLK output to be used in conjunction with RX Data pin (output) 10000: Reserved 10001: External Retransmission Request (input) 10010: Reserved 10011: Reserved 10100: RX Data (output) 10101: RX State (output) 10110: RX FIFO Almost Full (output) 10111: Antenna 1 Switch used for antenna diversity (output) 11000: Antenna 2 Switch used for antenna diversity (output) 11001: Valid Preamble Detected (output) 11010: Invalid Preamble Detected (output) 11011: Sync Word Detected (output) 11100: Clear Channel Assessment (output) 11101: VDD else : GND 75 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 0Eh. I/O Port Configuration Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 Type R R R R R/w R/w R/w R/w Reset value = 00000000 Bit 7 Name Reserved Function Reserved External Interrupt Status. 6 extitst[2] If the GPIO2 is programmed to be external interrupt sources then the status can be read here. External Interrupt Status. 5 extitst[1] If the GPIO1 is programmed to be external interrupt sources then the status can be read here. External Interrupt Status. 4 extitst[0] If the GPIO0 is programmed to be external interrupt sources then the status can be read here. Interrupt Request Output on the SDO Pin. 3 itsdo nIRQ output is present on the SDO pin if this bit is set and the nSEL input is inactive (high). Direct I/O for GPIO2. 2 dio2 If the GPIO2 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO2 is configured to be a direct input then the value of the pin can be read here. Direct I/O for GPIO1. 1 dio1 If the GPIO1 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO1 is configured to be a direct input then the value of the pin can be read here. Direct I/O for GPIO0. 0 dio0 If the GPIO0 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO0 is configured to be a direct input then the value of the pin can be read here. 76 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 0Fh. ADC Configuration Bit Name Type D7 D6 adcstart/ adcdone D5 D4 D3 D2 adcsel[2:0] adcref[1:0] R/w R/w R/w D1 D0 adcgain[1:0] R/w Reset value = 00000000 Bit 7 Name adcstart/adcdone Function ADC Measurement Start Bit. Reading this bit gives 1 if the ADC measurement cycle has been finished. ADC Input Source Selection. The internal 8-bit ADC input source can be selected as follows: 6:4 adcsel[2:0] 000: Internal Temperature Sensor 001: GPIO0, single-ended 010: GPIO1, single-ended 011: GPIO2, single-ended 100: GPIO0(+) – GPIO1(–), differential 101: GPIO1(+) – GPIO2(–), differential 110: GPIO0(+) – GPIO2(–), differential 111: GND ADC Reference Voltage Selection. The reference voltage of the internal 8-bit ADC can be selected as follows: 3:2 adcref[1:0] 0X: bandgap voltage (1.2 V) 10: VDD / 3 11: VDD / 2 ADC Sensor Amplifier Gain Selection. The full scale range of the internal 8-bit ADC in differential mode (see adcsel) 1:0 adcgain[1:0] can be set as follows: adcref[0] = 0: adcref[0] = 1: FS = 0.014 x (adcgain[1:0] + 1) x VDD FS = 0.021 x (adcgain[1:0] + 1) x VDD 77 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 10h. ADC Sensor Amplifier Offset Bit D7 D6 D5 Name Reserved Type R D4 D3 D2 D1 D0 adcoffs[3:0] R/ w Reset value = xxxx0000 Bit 7：4 3：0 Name Function Reserved Reserved. adcoffs[3:0] ADC Sensor Amplifier Offset*. *Note: The offset can be calculated as Offset = adcoffs[2:0] x VDD / 1000; MSB = adcoffs[3] = Sign bit. Register 11h. ADC Value Bit D7 D6 D5 D4 D3 Name adc[7:0] Type R D2 D1 D0 Reset value = xxxxxxxx Bit Name 7：0 adc[7:0] Function Internal 8 bit ADC Output Value. 78 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 12h. Temperature Sensor Calibration Bit D7 D5 D4 Name tsrange[1:0] D6 entsoffs entstrim D3 Type R/w R/w R/w D2 D1 D0 tstrim[3:0] R/w Reset value = 00100000 Bit Name Function tsrange[1:0] Temperature Sensor Range Selection. (FS range is 0..1024 mV) 00: 7：6 –40℃ .. 64℃ (full operating range), with 0.5℃ resolution (1 LSB in the 8-bit ADC) 01: –40℃… 85℃, with 1℃ 11: 0 ℃ … 85℃, with 0.5℃ 10: –40 F … 216 F, with 1 o o resolution (1 LSB in the 8-bit ADC) resolution (1 LSB in the 8-bit ADC) o F resolution (1 LSB in the 8-bit ADC) 5 entsoffs Temperature Sensor Offset to Convert from K to ºC. 4 entstrim Temperature Sensor Trim Enable. 3：0 tstrim[3:0] Temperature Sensor Trim Value. Register 13h. Temperature Value Offset Bit D7 D6 D5 D4 D3 Name tvoffs[7:0] Type R/W D2 D1 D0 Reset value = 00000000 Bit Name 7：0 tvoffs[7:0] Function Temperature Value Offset. This value is added to the measured temperature value. (MSB, tvoffs[8]: sign bit) 79 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Note: If a new configuration is needed (e.g., for the WUT or the LDC), proper functionality is required. The function must first be disabled, then the settings changed, then enabled back on. Register 14h. Wake-Up Timer Period 1 Bit D7 Name D6 D5 D4 D3 Reserved D1 D0 wtr[4:0] R/w Type D2 R/w Reset value = xxx00011 Bit Name 7：5 Reserved Function Reserved. Wake Up Timer Exponent (R) Value*. 4：0 wtr[4:0] Maximum value for R is decimal 20. A value greater than 20 will yield a result as if 20 were written. R Value = 0 can be written here. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. R = 0 is allowed, and the maximum value for R is decimal 20. A value greater than 20 will result in the same as if 20 was written. Register 15h. Wake-Up Timer Period 2 Bit D7 D6 D5 D4 D3 Name wtm[15:8] Type R/W D2 D1 D0 D1 D0 Reset value = 00000000 Bit Name 7：0 wtm[15:8] Function Wake Up Timer Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. Register 16h. Wake-Up Timer Period 3 Bit D7 D6 D5 D4 D3 Name wtm[7:0] Type R/W D2 Reset value = 00000001 Bit Name 7：0 wtm[7:0] Function Wake Up Timer Mantissa (M) Value*. M[7:0] = 0 is not valid here. Write at least decimal 1. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. 80 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 17h. Wake-Up Timer Value 1 Bit D7 D6 D5 D4 D3 Name wtm[15:8] Type R D2 D1 D0 D1 D0 D1 D0 Reset value = xxxxxxxx Bit Name 7：0 wtm[15:8] Function Wake Up Timer Current Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. Register 18h. Wake-Up Timer Value 2 Bit D7 D6 D5 D4 D3 Name wtm[7:0] Type R D2 Reset value = xxxxxxxx Bit Name 7：0 wtm[7:0] Function Wake Up Timer Current Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as TWUT = (4 x M x 2R ) / 32.768 ms. Register 19h. Low-Duty Cycle Mode Duration Bit D7 D6 D5 D4 D3 Name ldc [7:0] Type R/W D2 Reset value = 00000001 Bit Name Function Low-Duty Cycle Mode Duration (LDC)*. If enabled, the LDC will start together when the WUT is supposed to start, and 7：0 ldc [7:0] the duration of the LDC is specified by the address 19h and the equation that goes with it. In order for the LDC to work, the LDC value has to be smaller than the M value specified in registers 15h and 16h. LDC = 0 is not allowed here. Write at least decimal 1. *Note: The period of the low-duty cycle ON time can be calculated as TLDC_ON = (4 x LDC x 2R ) / 32.768 ms. R is the same as in the wake-up timer setting in "Register 14h. Wake-Up Timer Period 1". 81 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 1Ah. Low Battery Detector Threshold Bit D7 Name D6 D5 D4 D3 Reserved Type D2 D1 D0 lbdt[4:0] R/w R Reset value = xxx10100 Bit Name Function 7：5 Reserved Reserved. Low Battery Detector Threshold. 4：0 lbdt[4:0] This threshold is compared to Battery Voltage Level. If the Battery Voltage is less than the threshold the Low Battery Interrupt is set. Default = 2.7 V.* *Note: The threshold can be calculated as Vthreshold = 1.7 + lbdt x 50 mV. Register 1Bh. Battery Voltage Level Bit D7 Name D6 D5 D4 D3 Reserved Type D2 D1 D0 vbat[4:0] R R Reset value = xxxxxxxx Bit Name 7：5 Reserved Function Reserved. Battery Voltage Level. 4：0 vbat[4:0] The battery voltage is converted by a 5 bit ADC. In Sleep Mode the register is updated in every 1 s. In other states it measures continuously. 82 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 1Ch. Battery Voltage Level Bit D7 Name dwn3_bypass D6 ndec_exp[2:0] D5 D4 Type R/W R/W D3 D2 D1 D0 filset[3:0] R/W Reset value = 00000001 Bit Name Function 7 dwn3_bypass Bypass Decimator by 3 (if set). 6:4 ndec_exp[2:0] IF Filter Decimation Rates. 3:0 filset[3:0] IF Filter Coefficient Sets. Defaults are for Rb = 40 kbps and Fd = 20 kHz so Bw = 80 kHz. Register 1Dh. Battery Voltage Level Bit D7 D6 Name afcbd enafc Type R/W D5 D4 D3 D2 afcgearh[2:0] R/W D1 D0 afcgearl[2:0] R/W R/W Reset value = 01000000 Bit Name Function 7 afcbd If set, the tolerated AFC frequency error will be halved. 6 enafc AFC Enable. 5:4 afcgearh[2:0] AFC High Gear Setting. 3:0 afcgearl[2:0] AFC Low Gear Setting. 83 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 1Eh. AFC Timing Control Bit Name Type D7 D6 D5 Reserved D4 D3 D2 shwait[2:0] R D1 D0 anwait[2:0] R/W R/W Reset value = xx001010 Bit Name 7:6 Reserved Function Reserved. Short Wait Periods after AFC Correction. 5:3 shwait[2:0] Used before preamble is detected. Short wait = (RegValue + 1) x 2T b. If set to 0 then no AFC correction will occur before preamble detect, i.e. AFC will be disabled. 2:0 anwait[2:0] Antenna Switching Wait Time. Value corresponds to number of bits. 84 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 1Fh. Clock Recovery Gearshift Override Bit D7 D6 Name Reserved rxready D5 Type R/W R/W D4 D3 D2 crfast[2:0] D1 D0 crslow[2:0] R/W R/W Reset value = 00000011 Bit Name 7 Reserved Function Reserved. Improves Receiver Noise Immunity when in Direct Mode. 6 rxready It is recommended to set this bit after preamble is detected. When in FIFO mode this bit should be set to ―0‖ since noise immunity is controlled automatically. 5:3 crfast[2:0] Clock Recovery Fast Gearshift Value. 2:0 crslow[2:0] Clock Recovery Slow Gearshift Value. The gear-shift register controls BCR loop gain. Before the preamble is detected, BCR loop gain is as follows: crgain BCRLoopGain = crfast 2 Once the preamble is detected, internal state machine automatically shift BCR loop gain to the following: crgain BCRLoopGain = 2crslow crfast = 3‘b000 and crslow = 3‘b101 are recommended for most applications. The value of ―crslow‖ should be greater than ―crfast‖. 85 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 20h. Clock Recovery Oversampling Rate Bit D7 D6 D5 D4 D3 Name rxosr[7:0] Type R/W D2 D1 D0 Reset value = 01100100 Bit Name 7：0 rxosr[7:0] Function Oversampling Rate. 3 LSBs are the fraction, default = 0110 0100 = 12.5 clock cycles per data bit The oversampling rate can be calculated as rxosr = 500 kHz/(2 ndec_exp x RX_DR). The ndec_exp and the dwn3_bypass values found at Address: 1Ch – IF Filter Bandwidth register together with the receive data rate (Rb) are the parameters needed to calculate rxosr: rxosr = 500×(1+2×dwn3_bypass) 2 ×Rb×（1+enmanch） ndec_exp-3 The Rb unit used in this equation is in kbps. The enmanch is the Manchester Coding parameter (see Reg. 70h, enmach is 1 when Manchester coding is enabled, enmanch is 0 when disabled). The number found in the equation should be rounded to an integer. The integer can be translated to a hexadecimal. For optimal modem performance it is recommended to set the rxosr to at least 8. A higher rxosr can be obtained by choosing a lower value for ndec_exp or enable dwn3_bypass. A correction in filset might be needed to correct the channel select bandwidth to the desired value. Note that when ndec_exp or dwn3_bypass are changed the related parameters (rxosr, ncoff and crgain) need to be updated. 86 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 21h. Clock Recovery Offset 2 Bit D7 D6 D5 D4 D3 D2 D1 Name rxosr[10:8] stallctrl ncoff[19:16] Type R/W R/W R/W D0 Reset value = 00000001 Bit Name 7:5 rxosr[10:8] 4 stallctrl 3:0 ncoff[19:16] Function Oversampling Rate. Upper bits. Used for BCR Purposes. NCO Offset. See formula above. The offset can be calculated as follows: ncoff = Rb×（1+enmanch）×220+ndec_exp 500×(1+2×dwn3_bypass) The default values for register 20h to 23h gives 40 kbps RX_DR with Manchester coding is disenabled. Register 22h. Clock Recovery Offset 1 Bit D7 D6 D5 D4 D3 Name ncoff[15:8] Type R/W D2 D1 D0 Reset value =01000111 Bit Name 7:5 ncoff[15:8] Function NCO Offset. See formula above 87 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 23h. Clock Recovery Offset 0 Bit D7 D6 D5 D4 D3 Name ncoff[7:0] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 10101110 Bit Name 7:5 ncoff[7:0] Function NCO Offset. See formula above Register 24h. Clock Recovery Timing Loop Gain 1 Bit D7 D6 D5 D4 D3 Name Reserved crgain[10:8] Type R/W R/W Reset value = 00000010 Bit Name 7:3 Reserved 2:0 crgain[10:8] Function Reserved. Clock Recovery Timing Loop Gain. The loop gain can be calculated as follows: crgain = 2+ 215 ×Rb×（1+enmanch） rxsor×Fd Register 25h. Clock Recovery Timing Loop Gain 0 Bit D7 D6 D5 D4 D3 Name crgain[7:0] Type R/W D2 D1 D0 Reset value = 10001111 Bit Name 7:0 crgain[7:0] Function Clock Recovery Timing Loop Gain. 88 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 26h. Received Signal Strength Indicator Bit D7 D6 D5 D4 Name D3 D2 D1 D0 D2 D1 D0 D1 D0 rssi [7:0] Type R Reset value = 00000000 Bit Name 7:0 rssi [7:0] Function Received Signal Strength Indicator Value. Register 27h. RSSI Threshold for Clear Channel Indicator Bit D7 D6 D5 D4 D3 Name rssith[7:0] Type R/W Reset value = 00011110 Bit Name 7:0 rssith[7:0] Function RSSI Threshold. Interrupt is set if the RSSI value is above this threshold. Register 28h. Antenna Diversity 1 Bit D7 D6 D5 Name D4 D3 D2 adrssi[7:0] Type R Reset value = 00000000 Bit Name 7:0 adrssi[7:0] Function Measured RSSI Value on Antenna 1. 89 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 29h. Antenna Diversity 2 Bit D7 D6 D5 D4 Name D3 D2 D1 D0 D2 D1 D0 adrssi2[7:0] Type R Reset value = 00000000 Bit Name 7:0 adrssi2[7:0] Function Measured RSSI Value on Antenna 2. Register 2Ah. AFC Limiter Bit D7 D6 D5 D4 D3 Name Afclim[7:0] Type R/W Reset value = 00101010 Bit Name 7:0 Afclim[7:0] Function AFC Limiter. AFC limiter value. For the following registers (addresses 2Bh and 2Ch), use the following equation: ook_cnt_ val = 3×500[kHz] Rb×(enmanch+1) where Rb's unit is in kHz and ―enmanch‖ is the Manchester Enable bit (found at address 71h bit [1]). Therefore, the minimal data rate that this register can support without Manchester is 0.366 kbps. Register 2Bh. AFC Correction (LSBs) Bit D7 D6 D5 Name D4 D3 D2 D1 D0 afc_corr[9:2] Type R Reset value = 00101011 Bit Name Function AFC Correction Values. 7:0 afc_corr[9:2] AFC loop correction values [9:2] (MSBs only). Values are updated once, after sync word is found during receiving. See also address 2Ch. 90 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 2Ch. OOK Counter Value 1 Bit D7 Name D6 afc_corr[1:0] Type D5 D4 D3 D2 D1 D0 ookfrzen peakdeten madeten ookcnt[10] ookcnt[9] ookcnt[8] R/w R/w R/w R/w R R/w R/w Reset value = 00101100 Bit Name Function AFC Correction Values. 7:6 afc_corr[1:0] AFC loop correction values [1:0] (LSBs). Values are updated once, after sync word is found during receiving. See also address 2Bh. 5 ookfrzen 4 peakdeten 3 madeten 2:0 ookcnt[10] OOK Freeze. OOK AGC freeze if this bit is set. Peak Detector Enable. Peak detector enable if high. MA_Enable. MA block enable if high. OOK Counter [10:8]. OOK counter value MSBs. Register 2Dh. OOK Counter Value 2 Bit D7 D6 D5 D4 D3 Name ookcnt[7:0] Type R/w D2 D1 D0 Reset value = 00101101 Bit Name 7:0 afc_corr[9:2] Function OOK Counter [7:0]. OOK counter value LSBs. 91 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 2Eh. Slicer Peak Holder Bit D7 Name Reserved D6 D5 R/w Type D4 D3 D2 attack[2:0] D1 D0 D1 D0 decay[3:0] R/w R/w Reset value = 00101110 Bit Name Function 7 Reserved Reserved. 6:4 attack[2:0] Attack. 3:0 decay[3:0] Decay. Register 30h. Data Access Control Bit D7 D6 D5 D4 D3 D2 Name enpacrx lsbfrst crcdonly Reserved Reserved encrc R/w R/w Type R/w R/w R/w R/w crc[1:0] R/w Reset value = 00101100 Bit Name Function Enable Packet RX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be 7 enpacrx enabled. Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register 30–4D allow for various configurations of the packet structure. Setting enpacrx = 0 will not do any packet handling in the RX path. It will only receive everything after the sync word and fill up the RX FIFO. LSB First Enable. 6 lsbfrst 5 crcdonly 4 Reserved Reserved. 3 Reserved Reserved. 2 encrc The LSB of the data will be received first if this bit is set. CRC Data Only Enable. When this bit is set to 1 the CRC is checked against the packet data fields only. CRC Enable. Cyclic Redundancy Check generation is enabled if this bit is set. CRC Polynomial Selection. 1:0 crc[1:0] 00: CCITT 01: CRC-16 (IBM) 10: IEC-16 11: Biacheva 92 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 31h. EZMAC® Status Bit D7 D6 D5 D4 D3 D2 Name Reserved rxcrc1 pksrch pkrx pkvalid crcerror Type R R R R R D1 R D0 Reserved R Reset value = 00000000 Bit Name 7 Reserved 6 rxcrc1 5 pksrch 4 pkrx Function Reserved. If high, it indicates the last CRC received is all one’s. May indicated Transmitter underflow in case of CRC error. Packet Searching. When pksrch = 1 the radio is searching for a valid packet. Packet Receiving. When pkrx = 1 the radio is currently receiving a valid packet. Valid Packet Received. 3 pkvalid When a pkvalid = 1 a valid packet has been received by the receiver. (Same bit as in register 03, but reading it does not reset the IRQ) CRC Error. 2 crcerror When crcerror = 1 a Cyclic Redundancy Check error has been detected. (Same bit as in register 03, but reading it does not reset the IRQ) 1:0 Reserved Reserved. 93 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 32h. Header Control 1 Bit D7 D6 D5 D4 D3 D2 D1 Name bcen[3:0] hdch[3:0] Type R/w R/w D0 Reset value = 00001100 Bit Name Function Broadcast Address (FFh) Check Enable. If it is enabled together with Header Byte Check then the header check is OK if the incoming header byte equals with the appropriate check byte or FFh). One hot encoding. 7：4 bcen[3:0] 0000: No broadcast address enable. 0001: Broadcast address enable for header byte 0. 0010: Broadcast address enable for header byte 1. 0011: Broadcast address enable for header bytes 0 & 1. 0100: … Received Header Bytes to be Checked Against the Check Header Bytes. One hot encoding. The receiver will use hdch[2:0] to know the position of the Header Bytes. 3：0 hdch[3:0] 0000: No Received Header check 0001: Received Header check for byte 0. 0010: Received Header check for bytes 1. 0011: Received header check for bytes 0 & 1. 0100: … 94 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 33h. Header Control 2 Bit D7 Name Reserved Type D6 D5 D4 D3 hdlen[2:0] R/w R D2 fixpklen D1 synclen[1:0] R/w R/w D0 prealen[8] R/w Reset value = 00100010 Bit Name 7 Reserved Function Reserved. Header Length. Length of header used if packet handler is enabled for RX (enpacrx). Headers are received in descending order. 6:4 hdlen[2:0] 000: No RX header 001: Header 3 010: Header 3 and 2 011: Header 3 and 2 and 1 100: Header 3 and 2 and 1 and 0 Fix Packet Length. 3 fixpklen When fixpklen = 1 the packet length (pklen[7:0]) is not included in the header. When fixpklen = 0 the packet length is included in the header. Synchronization Word Length. The value in this register corresponds to the number of bytes used in the Synchronization Word. The synchronization word bytes are transmitted in 2:1 synclen[1:0] descending order. 00: Synchronization Word 3 01: Synchronization Word 3 and 2 10: Synchronization Word 3 and 2 and 1 11: 0 prealen[8] Synchronization Word 3 and 2 and 1 and 0 MSB of Preamble Length. See register Preamble Length. 95 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 34h. Preamble Length Bit D7 D6 D5 Name D4 D3 D2 D1 D0 prealen[7:0] R/w Type Reset value = 00001000 Bit Name Function Preamble Length. The value in the prealen[8:0] register corresponds to the number of nibbles (4 bits) in the packet. For example prealen[8:0] = ‗000001000‘ corresponds to a 7：0 prealen[7:0] preamble length of 32bits (8 x 4bits) or 4 bytes. The maximum preamble length is prealen[8:0] = 111111111 which corresponds to a 255 bytes Preamble. Writing 0 will have the same result as if writing 1, which corresponds to one single nibble of preamble. Register 35h. Preamble Detection Control 1 Bit D7 D6 D5 Name preath[4:0] Type R/w D4 D3 D2 D1 D0 rssi_offset[2:0] R/w Reset value = 00101010 Bit Name 7：3 preath[4:0] Function Number of nibbles processed during detection. rssi_offset[2:0] 2:0 rssi_offset[2:0] Value added as offset to RSSI calculation. Every increment in this register results in an increment of +4 dB in the RSSI. 96 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 36h. Synchronization Word 3 Bit D7 D6 D5 D4 D3 Name sync[31:24] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset value = 00101101 Bit Name 7：0 sync[31:24] Function Synchronization Word 3. 4th byte of the synchronization word. Register 37h. Synchronization Word 2 Bit D7 D6 D5 D4 D3 Name sync[23:16] Type R/W Reset value = 11010100 Bit Name 7：0 sync[23:16] Function Synchronization Word 2. 3rd byte of the synchronization word. Register 38h. Synchronization Word 1 Bit D7 D6 D5 Name D4 D3 sync[15:8] R/w Type Reset value = 00000000 Bit Name 7：0 sync[15:8] Function Synchronization Word 1. 2nd byte of the synchronization word. 97 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 39h. Synchronization Word 0 Bit D7 D6 D5 D4 D3 Name sync[7:0] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 00000000 Bit Name 7：0 sync[7:0] Function Synchronization Word 0. 1st byte of the synchronization word. Register 3Eh. Packet Length Bit D7 D6 D5 D4 D3 Name pklen[7:0] Type R/W Reset value = 00000000 Bit Name Function Packet Length. The value in the pklen[7:0] register corresponds directly to the number of bytes in the Packet. For example pklen[7:0] = ‗00001000‘ corresponds to a packet 7：0 pklen[7:0] length of 8 bytes. The maximum packet length is pklen[7:0] = ‗11111111‘, a 255 byte packet. Writing 0 is possible, in this case we do not send any data in the packet. During RX, if fixpklen = 1, this will specify also the Packet Length for RX mode. Check Header bytes 3 to 0 are checked against the corresponding bytes in the Received Header if the check is enabled in "Register 31h. EZMAC® Status". 98 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 3Fh. Check Header 3 Bit D7 D6 D5 D4 D3 Name chhd [31:24] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset value = 00000000 Bit Name 7：0 chhd[31:24] Function Check Header 3. 4th byte of the check header. Register 40h. Check Header 2 Bit D7 D6 D5 Name D4 D3 chhd[23:16] R/w Type Reset value = 00000000 Bit Name 7：0 chhd[23:16] Function Check Header 2. 3rd byte of the check header. Register 3Ch. Transmit Header 1 Bit D7 D6 D5 D4 D3 Name chhd[15:8] Type R/W Reset value = 00000000 Bit Name 7：0 chhd[15:8] Function Check Header 1. 2nd byte of the check header. 99 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 42h. Check Header 0 Bit D7 D6 D5 D4 D3 Name chhd[7:0] Type R/W D2 D1 D0 Reset value = 00000000 Bit Name 7：0 chhd[7:0] Function Check Header 0. 1st byte of the check header. Header Enable bytes 3 to 0 control which bits of the Check Header bytes are checked against the corresponding bits in the Received Header. Only those bits are compared where the enable bits are set to 1. Register 43h. Header Enable 3 Bit D7 D6 D5 D4 D3 Name hden[31:24] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 00000000 Bit Name 7：0 hden[31:24] Function Header Enable 3. 4th byte of the check header. Register 44h. Header Enable 2 Bit D7 D6 D5 Name D4 D3 hden[23:16] R/w Type Reset value = 00000000 Bit Name 7：0 hden [23:16] Function Header Enable 2. 3rd byte of the check header. 100 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 45h. Header Enable 1 Bit D7 D6 D5 D4 D3 Name hden [15:8] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset value = 00000000 Bit Name 7：0 hden [15:8] Function Header Enable 1. 2nd byte of the check header. Register 46h. Header Enable 0 Bit D7 D6 D5 D4 D3 Name hden [7:0] Type R/W Reset value = 00000000 Bit Name 7：0 hden [7:0] Function Header Enable 0. 1st byte of the header to be transmitted. Register 47h. Received Header 3 Bit D7 D6 D5 D4 D3 Name rxhd [31:24] Type R Reset value = 00000000 Bit Name 7：0 rxhd [31:24] Function Received Header 3. 4th byte of the received header. 101 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 48h. Received Header 2 Bit D7 D6 D5 D4 D3 Name rxhd [23:16] Type R D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset value = 00000000 Bit Name 7：0 rxhd [23:16] Function Received Header 2. 3rd byte of the received header. Register 49h. Received Header 1 Bit D7 D6 D5 D4 D3 Name rxhd [15:8] Type R Reset value = 00000000 Bit Name 7：0 rxhd [15:8] Function Received Header 2nd 1. byte of the received header. Register 4Ah. Received Header 0 Bit D7 D6 D5 D4 D3 Name rxhd [7:0] Type R Reset value = 00000000 Bit Name 7：0 rxhd [7:0] Function Received Header 1st 0. byte of the received header. 102 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 4Bh. Received Packet Length Bit D7 D6 D5 D4 D3 Name rxplen[7:0] Type R D2 D1 D0 Reset value = 11111111 Bit Name Function Length Byte of the Received Packet during fixpklen = 0. (Specifies the number of Data bytes in the last received packet) This will be 7：0 relevant ONLY if fixpklen (address 33h, bit[3]) is low during the receive time. If rxplen[7:0] fixpklen is high, then the number of received Data Bytes can be read from the pklen register (address h3E). Register 4Fh. ADC8 Control Bit D7 Name Type D6 D5 Reserved[7:6] D4 D3 D2 D1 D0 adc8[5:0] R/W R/W Reset value = 00000000 Bit Name 7：6 Reserved[7:6] 5:0 adc8[5:0] Function Reserved. ADC8 Control Bits. 103 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 50h. Analog Test Bus Select Bit D7 D6 D5 Name Reserved Type R/W D4 D3 D2 D1 D0 atb[4:0] R/W Reset value = 00000000 Bit Name 7:5 Reserved Function Reserved. Analog Test Bus. 4:0 atb[4:0] The selection of internal analog testpoints that are muxed onto TESTp and TESTn. 104 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 32. Internal Analog Signals Available on the Analog Test Bus atb[4:0] GPIOx GPIOx 1 MixIp MixIn 2 MixQp MixQn 3 PGA_Ip PGA_In 4 PGA_QP PGA_Qn 5 ADC_vcm ADC_vcmb 6 ADC_ipoly10u ADC_ref 7 ADC_Refdac_p ADC_Refdac_n 8 ADC_ipoly10 ADC_ipoly10 9 ADC_Res1Ip ADC_Res1In 10 ADC_Res1Qp ADC_Res1Qn 11 Reserved Reserved 12 Reserved Reserved 13 Reserved Reserved 14 Reserved Reserved 15 Reserved Reserved 16 Reserved Reserved 17 Reserved Reserved 18 ICP_Test PLL_IBG_05 19 PLL_VBG VSS_VCO 20 Vctrl_Test PLL_IPTAT_05 21 PA_vbias Reserved 22 DIGBG DIGVFB 23 IFBG IFVFB 24 PLLBG PLLVReg 25 IBias10u IBias5u 26 32KRC_Ucap 32KRC_Ures 27 ADC8_VIN ADC8_VDAC 28 LBDcomp LBDcompref 29 TSBG TSVtemp 30 RFBG RFVREG 31 VCOBG VCOVREG 105 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 51h. Digital Test Bus Select Bit D7 D6 Name Reserved ensctest D5 D4 D3 dtb[5:0] D2 Type R/W R/W R/W D1 D0 Reset value = 00000000 Bit Name 7 Reserved 6 ensctest 5:0 dtb[5:0] Function Reserved. Scan Test Enable. When set to 1 then GPIO0 will be the ScanEn input. Digital Test Bus. GPIO must be configured to Digital Test Mux output. Table 33. Internal Digital Signals Available on the Digital Test Bus 106 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Table 33. Internal Digital Signals Available on the Digital Test Bus (Continued) 107 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 The total settling time (cold start) of the PLL after the calibration can be calculated as TCS = TS + TO. Register 53h. PLL Tune Time Bit D7 D6 D5 D4 D3 D2 D1 Name pllts[4:0] pllt0 Type R/w R/w D0 Reset value = 01010010 Bit Name Function PLL Soft Settling Time (TS). This register will set the settling time for the PLL from a previous locked 7:3 frequency in Tune mode. The value is configurable between 0 μs and 310 μs, pllts[4:0] in 10 μs intervals. The default plltime corresponds to 100 μs. See formula above. PLL Settling Time (TO). 2:0 This register will set the time allowed for PLL settling after the calibrations are pllt0 completed. The value is configurable between 0 μs and 70 μs, in 10 μs steps. The default pllt0 corresponds to 20 μs. See formula above. Register 54h. PA Boost Bit D7 Name Type D6 D5 D4 Reserved[7:6] D3 D2 inv_pre_th R/w R/w D1 D0 ldo_pa_boost pa_vbias_boost R/w R/w Reset value = 01010100 Bit Name Function 7:6 Reserved[7:6] Reserved. 5:2 inv_pre_th[5:2] Invalid Preamble Threshold. 1 ldo_pa_boost 0 pa_vbias_boost LDO PA Boost. PA VBIAS Boost. Invalid preamble will be evaluated during this period: (invalid_preamble_Threshold x 4) x Bit Rate period. 108 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 55h. Calibration Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved xtalstarthalf adccaldone enrcfcal rccal vcocaldp vcocal skipvco Type R R/w R R/w R/w R/w R/w R/w Reset value = x1x00100 Bit Name 7 Reserved 6 xtalstarthalf 5 adccaldone 4 enrcfcal Function Reserved. If Set, the Xtal Wake Time Period is Halved. Delta-sigma ADC Calibration Done. Reading this bit gives 1 if the calibration process has been finished. RC Oscillator Fine Calibration Enable. If this bit is set to 1 then the RC oscillator performs fine calibration in every app. 30 s. RC Calibration Force. If setting rccal = 1 will automatically perform a forced calibration of the 32 kHz RC Oscillator. The RC OSC will automatically be calibrated if the 3 rccal Wake-Up-Timer is enabled or if in the Wake-on-Receiver state. The calibration takes 2 ms. The 32 kHz RC oscillator must be enabled to perform a calibration. Setting this signal from a 0 to 1 will initiate the calibration. This bit is cleared automatically. VCO Calibration Double Precision Enable. 2 vcocaldp When this bit is set to 1 then the VCO calibration measures longer thus calibrates more precisely. VCO Calibration Force. 1 vcocal If in Idle Mode and pllon = 1, setting vcocal = 1 will force a one time calibration of the synthesizer VCO. This bit is cleared automatically. Skip VCO Calibration. 0 skipvco Setting skipvco = 1 will skip the VCO calibration when going from the Idle state to the RX state. 109 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 56h. Modem Test Bit D7 D6 D5 D4 D3 D2 D1 D0 Name bcrfbyp slicfbyp dttype oscdeten ookth refclksel refclkinv distogg Type R/w R/w R/w R/w R/w R/w R/w R/w Reset value = 00000000 Bit Name Function 7 bcrfbyp If set, BCR phase compensation will be bypassed. 6 slicfbyp If set, slicer phase compensation will be bypassed. 5 dttype Dithering Type. If low and dither enabled, we add +1/0, otherwise if high and dithering enabled, we add ±1. 4 oscdeten 3 ookth If low, the ADC Oscillation Detection mechanism is allowed to work. If set, we disable the function. If set, in OOK mode, the slicer threshold will be estimated by 8 bits of preamble. By default, this bit is low and the demod estimate the threshold after 4 bits. Delta-Sigma Reference Clock Source Selection 2 refclksel 1: 0: 10 MHz PLL 1 refclkinv Delta-Sigma Reference Clock Inversion Enable. 0 distogg If reset, the discriminator toggling is disabled. 110 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 57h. Charge Pump Test Bit D7 D6 D5 D4 D3 Name pfdrst fbdiv_rst cpforceup cpforcedn cdonly Type R/w R/w R/w R/w D2 D1 D0 cdcurr[2:0] R/w R/w Reset value = 00000000 Bit Name Function 7 pfdrst Direct Control to Analog. 6 fbdiv_rst Direct Control to Analog. 5 cpforceup Charge Pump Force Up. 4 cpforcedn Charge Pump Force Down. 3 cdonly 2:0 cdcurr[2:0] Charge Pump DC Offset Only. Charge Pump DC Current Selection. Register 58h. Charge Pump Current Trimming/Override Bit D7 D6 Name cpcurr[1:0] Type R/w D5 D4 D3 cpcorrov D2 D1 D0 cporr[4:0] R/w R/w Reset value = 100xxxxx Bit Name Function Charge Pump Current (Gain Setting). 7:6 cpcurr[1:0] 5 cpcorrov Changing these bits will change the BW of the PLL. The default setting is adequate for all data rates. Charge Pump Correction Override Enable. Charge Pump Correction Value. 4:0 cporr[4:0] During read, you read what the Charge Pump sees. If cpcorrov = 1, then the value you write will go to the Charge Pump, and will also be the value you read. By default, cpcorr[4:0] wakes up as all Zeros. 111 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 59h. Divider Current Trimming/Delta-Sigma Test Bit D7 D6 Name Reserved fbdivhc Type R/w D5 D4 D3 d3trim[1:0] R/w D2 d2trim[1:0] R/w D1 D0 d1p5trim[1:0] R/w R/w Reset value = 10000000 Bit Name 7 Reserved Function 6 fbdivhc 5:4 d3trim[1:0] Divider 3 Current Trim Value. 3:2 d2trim[1:0] Divider 2 Current Trim Value. 1:0 d1p5trim[1:0] Reserved. Feedback (fractional) Divider High Current Enable (+5 μA). Divider 1.5 (div-by-1.5) Current Trim Value. Register 5Ah. VCO Current Trimming Bit D7 D6 Name Reserved vcocorrov D5 D4 vcocorr[3:0] D3 D2 D1 vcocur[1:0] D0 Type R/w R/w R/w R/w Reset value = 00000011 Bit Name 7. Reserved Function Reserved. 6 vcocorrov VCO Current Correction Override. 5:2 vcocorr[3:0] VCO Current Correction Value. 1:0 vcocur[1:0] VCO Current Trim Value. 112 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 5Bh. VCO Calibration/Override Bit D7 Name vcocalov/vcdone Type D6 D5 D4 D3 D2 D1 D0 vcocal[6:0] R/w R/w Reset value = 00000000 Bit Name Function VCO Calibration Override/Done. When vcocalov = 0 the internal VCO calibration results may be viewed by 7. reading the vcocal register. When vcocalov = 1 the VCO results may be vcocalov/vcdone overridden externally through the SPI by writing to the vcocal register. Reading this bit gives 1 if the calibration process has been finished. 6:0 VCO Calibration Results. vcocal[6:0] Register 5Ch. Synthesizer Test Bit D7 D6 D5 D4 Name dsmdt vcotype enoloop dsmod dsorder[1:0] Type R/w R R/w R/w R/w D3 D2 D1 D0 dsrstmode dsrst R/w R/w Reset value = 0x001110 Bit Name 7 dsmdt Function Enable DSM Dithering. If low, dithering is disabled. VCO Type. 6 vcotype 0: basic, constant K 1: single varactor, changing K 5 enoloop Open Loop Mode Enable. Delta-Sigma Modulus. 4 dsmod 0: 64 000 1: 65 536 Delta-Sigma Order. 3:2 dsorder[1:0] 1 dsrstmode 0 dsrst 00: 0 order 01: 1st order 10: 2nd order 11: Mash 111 Delta-Sigma Reset Mode. Delta-Sigma Reset. 113 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 5Dh. Block Enable Override 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name enmix enina enpga Reserved enbf5 endv32 enbf12 enmx2 R/W R/W R/W R/W R/W R/W Type R/W R/W Reset value = 00000000 Bit Name Function 7 enmix Mixer Enable Override. 6 enina LNA Enable Override. 5 enpga PGA Enable Override. 4 Reserved 3 enbf5 2 endv32 Divider 3_2 Enable Override. 1 enbf12 Buffer 1_2 Enable Override. 0 enmx2 Multiplexer 2 Enable Override. Reserved. Buffer 5 Enable Override. Register 5Eh. Block Enable Override 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ends enldet enmx3 enbf4 enbf3 enbf11 enbf2 pllreset Type R/W R/W R/W R/W R/W R/W R/W R/W Reset value = 01000000 Bit Name Function 7 ends 6 enldet 5 enmx3 Multiplexer 3 Enable Override. 4 enbf4 Buffer 4 Enable Override. 3 enbf3 Buffer 3 Enable Override. 2 enbf11 Buffer 1_1 Enable Override. 1 enbf2 Buffer 2 Enable Override. 0 pllreset Delta-Sigma Enable Override. Lock Detect Enable. (direct control, does not need override!) PLL Reset Enable Override. 114 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 5Fh. Block Enable Override 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name enfrdv endv31 endv2 endv1p5 dvbshunt envco encp enbg Type R/W R/W R/W R/W R/W R/W R/W R/W Reset value = 00000000 Bit Name Function 7 enfrdv Fractional Divider Enable Override. 6 endv31 Divider 3_1 Enable Override. 5 endv2 Divider 2 Enable Override. 4 endv1p5 Divider 1.5 (div-by-1.5) Enable Override. 3 dvbshunt VCO Bias Shunt Enable Override Mode. 2 envco VCO Enable Override. 1 encp Charge Pump Enable Override. 0 enbg Bandgap Enable Override. Register 60h. Channel Filter Coefficient Address Bit D7 D6 D5 D4 D3 D2 D1 Name Reserved chfiladd[3:0] Type R/W R/W D0 Reset value = 00000000 Bit Name 7:4 Reserved 3:0 chfiladd[3:0] Function Reserved. Channel Filter Coefficient Look-up Table Address. The address for channel filter coefficients used in the RX path. 115 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 61h. Channel Filter Coefficient Value Bit D7 D6 D5 D4 D3 D2 Name Reserved chfilval[5:0] Type R/W R/W D1 D0 Reset value = 00000000 Bit Name Function 7:6 Reserved 5:0 chfilval[5:0] Reserved. Filter Coefficient Value in the Look-up Table Addressed by the chfiladd[3:0]. Register 62h. Crystal Oscillator/Power-on-Reset Control Bit D7 D6 D5 D4 D3 D2 D1 D0 bufovr enbuf R/W R/W Name pwst[2:0] clkhyst enbias2x enamp2x Type R R/W R/W R/W Reset value = xxx00100 Bit Name Function Internal Power States of the Module. LP: 7:5 pwst[2:0] 000 RDY: 001 Tune: 011 TX: 010 4 clkhyst 3 enbias2x 2 Times Higher Bias Current Enable. 2 enamp2x 2 Times Higher Amplification Enable. Clock Hysteresis Setting. Output Buffer Enable Override. 1 bufovr If set to 1 then the enbuf bit controls the output buffer. 0: output buffer is controlled by the state machine. 1: output buffer is controlled by the enbuf bit. 0 enbuf Output Buffer Enable. This bit is active only if the bufovr bit is set to 1. 116 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 63h. RC Oscillator Coarse Calibration/Override Bit D7 Name rccov Type R/W D6 D5 D4 D3 D2 D1 D0 rcc[6:0] R/W Reset value = 00000000 Bit Name Function RC Oscillator Coarse Calibration Override. 7 When rccov = 0 the internal Coarse Calibration results may be viewed by rccov reading the rcccal register. When rccov = 1 the Coarse results may be overridden externally through the SPI by writing to the rcccal register. 6:0 rcc[6:0] RC Oscillator Coarse Calibration Override Value/Results. Register 64h. RC Oscillator Fine Calibration/Override Bit D7 D6 D5 D4 D3 Name rcfov rcf[6:0] Type R/W R/W D2 D1 D0 Reset value = 00000000 Bit Name Function RC Oscillator Fine Calibration Override. 7 rcfov When rcfov = 0 the internal Fine Calibration results may be viewed by reading the rcfcal register. When rcfov = 1 the Fine results may be overridden externally through the SPI by writing to the rcfcal register. 6:0 rcf[6:0] RC Oscillator Fine Calibration Override Value/Results. 117 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 65h. LDO Control Override Bit D7 D6 D5 D4 D3 D2 D1 D0 Name enspor enbias envcoldo enifldo enrfldo enpllldo endigldo endigpwdn Type R/W R/W R/W R/W R/W R/W R/W R/W Reset value = 10000001 Bit Name Function 7 enspor Smart POR Enable. 6 enbias Bias Enable. 5 envcoldo 4 enifldo IF LDO Enable. 3 enrfldo RF LDO Enable. 2 enpllldo PLL LDO Enable. 1 endigldo Digital LDO Enable. 0 endigpwdn VCO LDO Enable. Digital Power Domain Powerdown Enable in Idle Mode. Register 66h. LDO Level Settings Bit D7 D6 D5 D4 D3 D2 D1 Name enovr enxtal ents enrc32 Reserved diglvl Type R/W R/W R/W R/W R R/W D0 Reset value = 00000011 Bit Name 7 enovr Function Enable Overrides. If high, ovr values are output to the blocks and can enable or disable them, if low, some ovr value can only enable the blocks. 6 enxtal 5 ents 4 enrc32 3 Reserved 2:0 diglvl Xtal Override Enable Value. Temperature Sensor Enable. 32K Oscillator Enable. Reserved. Digital LDO Level Setting. 118 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 67h. Delta-Sigma ADC Tuning 1 Bit D7 D6 D5 D4 Name adcrst enrefdac enadc adctuneovr D3 D2 adctune[3:0] D1 Type R/W R/W R/W R/W R/W D0 Reset value = 00011101 Bit Name Function 7 adcrst 6 enrefdac 5 enadc 4 adctuneovr Resonator RC Calibration Value Override Enable. 3:0 adctune[3:0] Resonator RC Calibration Value. Delta-Sigma ADC Reset. Delta-Sigma ADC Reference DAC Enable Override. Delta-Sigma ADC Enable Override. Register 68h. Delta-Sigma ADC Tuning 2 Bit D7 Name D6 D5 Reserved Type R D4 D3 envcm adcoloop R/W D2 R/W D1 D0 adcref[2:0] R/W Reset value = 00000011 Bit Name 7:5 Reserved 4 envcm 3 adcoloop Function Reserved. Delta-Sigma ADC VCM Enable Override. Delta-Sigma ADC Open Loop Enable. Delta-Sigma ADC Reference Voltage. 2:0 adcref[2:0] 000: 0.5 V 001: 0.6 V 010: 0.7 V … 111: 1.2 V 119 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 69h. AGC Override 1 Bit D7 Name D6 Reserved Type D5 D4 agcen lnagain pga[3:0] R/W R/W R/W R D3 D2 D1 D0 Reset value = 00100000 Bit Name 7:5 Reserved 4 agcen Function Reserved. Automatic Gain Control Enable. When this bit is set then the result of the control can be read out from bits [4:0], otherwise the gain can be controlled manually by writing into bits [4:0]. 3 LNA Gain Select. lnagain 0 – min. gain = 5 dB 1 – max. gain = 25 dB PGA Gain Override Value. 2:0 pga[3:0] 000: 0 dB 001: 3 dB 010: 6 dB ... 101: 24 dB max. Register 6Ah. AGC Override 2 Bit D7 D6 D5 Name agcovpm agcslow Type R/W D4 D3 D2 D1 lnacomp[3:0] R/W D0 pgath[1:0] R/W R/W Reset value = 10011101 Bit Name 7 agcovpm Function If set, AGC will ignore the Preamble Detection. AGC Slow Gain Increase Enable. 6 agcslow When this bit is set then the AGC loop will slow down the gain increase in the receiver. The speed of the gain reduction is not affected. 5:2 lnacomp[3:0] 1:0 pgath[1:0] LNA Gain Compensation. This bit is used for smoothing RSSI value when LNA gain is switched. Window Comparator Reference Voltage Adjust in the PGA. 120 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 6Fh. TX Data Rate 0 Bit D7 D6 D5 D4 D3 Name txdr[7:0] Type R/W D2 D1 D0 Reset value = 00111101 Bit Name 7:0 txdr[7:0] Function Data Rate Lower Byte. See formula above. Defaults = 40 kbps. Register 70h. Modulation Mode Control 1 Bit Name Type D7 D6 Reserved R D5 D4 D3 D2 D1 D0 Reserved enphpwdn manppol enmaninv enmanch enwhite R/W R/W R/W R/W R/W R/W Reset value = 00001100 Bit Name Function 7:6 Reserved Reserved. 5 Reserved Reserved. 4 enphpwdn If set, the Packet Handler will be powered down when module is in low power mode. Manchester Preamble Polarity (will transmit a series of 1 if set, or series of 0 if 3 manppol reset). This bit affects ONLY the transmitter side, not the receiver. This is valid ONLY if Manchester Mode is enabled. 2 enmaninv Manchester Data Inversion is Enabled if this bit is set. 1 enmanch Manchester Coding is Enabled if this bit is set. 0 enwhite Data Whitening is Enabled if this bit is set. 121 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 71h. Modulation Mode Control 2 Bit Name D7 D6 D5 Reserved Type D4 Reserved R/W R/W D3 D2 eninv fd[8] R/W R/W D1 D0 Reserved R/W Reset value = 00000000 Bit Name 7:4 Reserved 3 eninv 2 fd[8] 1:0 Reserved Function Reserved. RX Data. MSB of Frequency Deviation Setting, see "Register 72h. Frequency Deviation". Reserved. The frequency deviation can be calculated: Fd = 625 Hz x fd[8:0]. 122 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 72h. Frequency Deviation Bit D7 D6 D5 D4 D3 Name fd[7:0] Type R/W D2 D1 D0 Reset value = 00100000 Bit Name 7:0 fd[7:0] Function Frequency Deviation Setting. See formula above. Note: It's recommended to use modulation index of 1 or higher (maximum allowable modulation index is 32). The modulation index is defined by 2FN/FR were FD is the deviation and RB is the data rate. When Manchester coding is enabled the modulation index is defined by FD/RB. Register 73h. Frequency Offset 1 Bit D7 D6 D5 D4 D3 Name fo[7:0] Type R/W D2 D1 D0 Reset value = 00000000 Bit Name Function Frequency Offset Setting. 7:0 fo[7:0] The frequency offset can be calculated as Offset = 156.25 Hz x (hbsel + 1) x fo[7:0]. fo[9:0] is a twos complement value. Reading from this register will give the AFC correction last results, not this register value. Reading from this register will give the AFC correction last results, not this register value. 123 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 74h. Frequency Offset 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Reserved fo[9:8] Type R R/W Reset value = 00000000 Bit Name 7:2 Reserved Function Reserved. Upper Bits of the Frequency Offset Setting. 1:0 fo[9:8] fo[9] is the sign bit. The frequency offset can be calculated as Offset = 156.25 Hz x (hbsel + 1) x fo[7:0]. fo[9:0] is a twos complement value. Reading from this register will give the AFC correction last results, not this register value. Register 75h. Frequency Band Select Bit D7 D6 D5 Name Reserved sbsel hbsel fb[4:0] R/W R/W R/W Type R D4 D3 D2 D1 D0 Reset value = 01110101 Bit Name 7 Reserved 6 sbse Function Reserved. Side Band Select. High Band Select. 5 hbsel Setting hbsel = 1 will choose the frequency range from 480–930 MHz (high bands). Setting hbsel = 0 will choose the frequency range from 240–479.9 MHz (low bands). Frequency Band Select. Every increment corresponds to a 10 MHz Band for the Low Bands and a 20 MHz Band 4:0 fb[4:0] for the High Bands. Setting fb[4:0] = 00000 corresponds to the 240–250 MHz Band for hbsel = 0 and the 480–500 MHz Band for hbsel = 1. Setting fb[4:0] = 00001 corresponds to the 250–260 MHz Band for hbsel = 0 and the 500–520 MHz Band for hbsel = 1. The RF carrier frequency can be calculated as follows: fcarrier = (fb+24+(fc+fo) / 64000) x 10000 x (hbsel+1) + (fhch x fhs x 10) [kHz], where parameters fc, fo, fb and hb_sel come from registers 73h–77h. Parameters fhch and fhs come from register 79h and 7Ah. 124 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 76h. Nominal Carrier Frequency Bit D7 D6 D5 D4 D3 Name fc[15:8] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset value = 10111011 Bit Name 7:0 fc[15:8] Function Nominal Carrier Frequency Setting. See formula above. Register 77h. Nominal Carrier Frequency Bit D7 D6 D5 D4 D3 Name fc[7:0] Type R/W Reset value = 10000000 Bit Name 7:0 fc[7:0] Function Nominal Carrier Frequency Setting. See formula above. Register 78h. Miscellaneous Settings Bit D7 D6 Name D5 D4 D3 Reserved[7:4] Type R/W Alt_PA_Seq rcosc_cal[2:0] R/W R/W Reset value = 01111000 Bit Name 7:0 Reserved[7:4] 3 Alt_PA_Seq Function Reserved. Alternative PA sequencing. If set, we will enable the alternative PA sequence. By default, this is not enabled. rcosc_cal[2:0]. 2:0 rcosc_cal[2:0] Fine changes on the RC OSC Calibration target frequency, to help compensate for ―calibration biases.‖ This register should not be changed by costumers. 125 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 79h. Frequency Hopping Channel Select Bit D7 D6 D5 D4 D3 Name fhch[7:0] Type R/W D2 D1 D0 D2 D1 D0 Reset value = 00000000 Bit Name 7:0 fhch[7:0] Function Frequency Hopping Channel Number. Register 7Ah. Frequency Hopping Step Size Bit D7 D6 D5 D4 D3 Name fhs[7:0] Type R/W Reset value = 00000000 Bit Name Function Frequency Hopping Step Size in 10 kHz Increments. 7:0 fhs[7:0] See formula for the nominal carrier frequency at "Register 76h. Nominal Carrier Frequency". 126 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 7Bh. Turn Around and 15.4 Length Compliance Bit D7 Name 15.4 Length D6 Reserved[6:3] D5 D4 Type R/W R/W D3 D2 D1 turn_around_en D0 phase[1:0] R/W R/W Reset value = 01111011 Bit Name Function 15.4 Packet Length Compliance. 7 If set, then PK Length definition for both TX and RX will also include the CRC bytes, 15.4 Length If reset, then the Length refers ONLY to the DATA payload. For example, writing ―9‖ to this register when it is set, means we are sending/expecting ―7‖ bytes of DATA, and the other ―2‖ should be the CRC (CRC should be enabled separately). 6:3 Reserved[6:3] 2 turn_around_en Reserved. Turn Around Enable. Enabling for the turn around functionality. Turn Around Phase. The RX to TX and vice-versa change in frequency will happen (if bit [2] is set) at the 1:0 phase[1:0] last byte, and these two registers set the bit position in which the frequency shifts should occur. Make sure it does not happen to early otherwise the last bits will be missed. Register 7Eh. TX FIFO Control 2 Bit Name Type D7 D6 D5 D4 Reserved D3 D2 D1 D0 rxafthr[5:0] R/W R/W Reset value = 00110111 Bit Name Function 7：6 Reserved Reserved. 5：0 rxafthr[5:0] RX FIFO Almost Full Threshold 127 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 Register 7Fh. FIFO Access Bit D7 D6 D5 Name D4 D3 D2 D1 D0 fifod[7:0] Type R/W Reset value = NA Bit Name 7：0 fifod[7:0] Function FIFO Data. A Read (R/W = 0) to this address will begin a burst read of the RX FIFO. 128 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 12. Pin Descriptions: RFM31 RFM31S1 RFM31S2 RFM31D IC 129 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 VCC S +1.8 to +3.6 V supply voltage. The recommended VCC supply voltage is +3.3 V. GND S Ground reference. GPIO_0 I/O GPIO_1 I/O General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. See the SPI GPIO Configuration Registers, GPIO_2 I/O SDO O Address 0Bh, 0Ch, and 0Dh for more information. 0–VCC V digital output that provides a serial readback function of the internal control registers. Serial Data input. 0–VCC V digital input. This pin provides the serial data stream for the 4-line SDI I serial data bus. Serial Clock input. 0–VDD V digital input. This pin provides the serial data clock function for SCLK I the 4-line serial data bus. Data is clocked into the RFM31 on positive edge transitions. Serial Interface Select input. 0– VCC V digital input. This pin provides the Select/Enable nSEL I function for the 4-line serial data bus. The signal is also used to signify burst read/write mode. General Microcontroller Interrupt Status output. When the RFM31 exhibits anyone of the Interrupt Events the nIRQ pin will be set low=0. Please see the Control Logic registers nIRQ O section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding SPI Interrupt Status Registers, Address 03h and 04h. I SDN Shutdown input pin. 0–VCC V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. ANT I/O NC RF signal input.(50 OHM input Impedance) No Connection 130 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 13. Mechanical Dimension: RFM31 SMD PACKAGE（S1） SMD PACKAGE（S2） 131 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 DIP PACKAGE（D） 132 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 14. Ordering Information Part Number=module type—operation band—package type RFM31—433—D module type operation band Package example：1，RFM31 module at 433MHz band, DIP : RFM31-433-D。 2，RFM31 module at 868MHZ band, SMD, thickness at 4.9mm: RFM31-868-S1。 133 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 15. Errata Status Summary Title Errata # 1 2 3 4 5 6 7 Some non-standard frequencies are not supported. Radio does not return to the low power state when in Low Duty Cycle Mode. Additional tuning steps required for proper RX mode operation. Potential modem failure with default settings. Default register settings for optimal current consumption. Wake Up Timer and Low Duty Cycle mode not functional. False preamble detection issue. Impact Status Major Will be fixed in the next revision. Minor Will be fixed in the next revision. Minor Will be fixed in the next revision. Minor Will be fixed in the next revision. Minor Will be fixed in the next revision. Minor Use the micro or 32 kHz option for these functions. Will be fixed in the next revision Minor Software workaround available. Impact Definition: Each erratum is marked with an impact, as defined below: Minor: Workaround exists. Major: Errata that do not conform to the data sheet or standard. Information: The device behavior is acceptable the data sheet will be changed to match the device behavior. 134 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 16.Errata Details 1. Description: Some non-standard frequencies are not supported. Impacts: Operation in frequencies between 240-280 MHz and 480-560 MHz should be avoided. Workaround: These are non-standard bands and should result in no customer impact; no workaround at this time. Resolution: Will be fixed in the next revision. 2. Description: Radio does not return to the low power state when in Low Duty Cycle mode. Impacts: When using the Low Duty Cycle mode, the radio will not automatically return to the low power state. Workaround: The radio mode control can be implemented on the external MCU for controlling the RX power state. Resolution: Will be fixed in the next revision. 3. Description: Additional tuning steps are required for proper RX mode operation. Impacts: Tuning can fail if additional steps are not implemented in customer firmware. Workaround: The following steps should be followed to ensure proper operation: 1. Program desired RX frequency minus 937.5kHz: Program registers 75h, 76h, and 77h 2. Program tune mode: Program register 07h bit 1 (pllon = 1) 3. Disable VCO calibration: Program register 55h bit 0 (skipvco = 1) 4. Program desired RX frequency: Program registers 75h, 76h, and 77h 5. Program RX mode: Program register 07h bit 2 (rxon = 1) 6. Implement normal operation Resolution: Will be fixed in the next revision 4. Description: Potential modem failure in receive mode with default settings. Impacts: Under strong blocker conditions, the modem can fail unless the listed workaround is followed. Workaround: Operate the radio with AFC enabled: Program register 56h to C1h Resolution: Will be fixed in the next revision. 5. Description: Default register settings for optimal current consumption. Impacts: Current consumption. Workaround: Program register 57h bits 2:0 (cdcurr[2:0] = 001), register 59 bit 6 (fbdivhc = 0), register 5Ah bits 1:0 (vcocur[1:0] = 01). Resolution: Will be fixed in the next revision. 135 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 6. Description: Wake-up Timer and Low Duty Cycle Modes not functional. Impacts: These features are not supported. Workaround: Use the external microcontroller or the 32 kHz XTAL option on the RF22 to implement these functions. Resolution: Will be fixed in the next revision. 7. Description: If a false preamble is detected the chip will remain in the sync detection state indefinitely or until a valid sync word is detected. Impacts: RX link performance and batter life. Workaround: Extend the preamble detection threshold to prevent false preamble detection or implement a software work around and perform the sync timeout on the microcontroller. Resolution: Will be fixed in the next revision. HOPE MICROELECTRONICS CO.,LTD Add:4/F, Block B3, East Industrial Area, Huaqiaocheng, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: [email protected] [email protected] Website: http://www.hoperf.com http://hoperf.en.alibaba.com This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved. 136 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com RFM31 137 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com